******************************************************************************* * * The purpose of this demo application is to present a usage of the ADC_SAR and * BCTU IP Driver for the S32K3xx MCU. * * The example uses the PIT0 trigger to trigger BCTU conversion list. Five standard * ADC channels are selected to be converted. * Converted result from BCTU data register are moved by DMA into result array. * This result array should be placed into no cacheable area if data cache is enabled. * * ADC channel S10 is connected to board's potentiometer, and converted value is * used to dim board's LED. * * * ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: RTD 1.0.0 * Debugger: Lauterbach * Target: internal_FLASH ********************************************************************************

  EV/HEV is the mega trend and NXP focused area. E-Compressor controller is a key and additional component of EV/HEV vs. traditional vehicle. While S32K14x is the perfect product for mainstream E-compressor application. To accelerate customer develop period in automotive E-compressor application, we develop the S32K142-ECC RDB. Actually, S32K142-ECC is not only suitable for E-compressor, but also can be used in other high voltage PMSM/BLDC application in automotive industry. This RDB (Reference Design Board) hardware is based on NXP S32K142 high-performance automotive-grade MCU and UJA1075A SBC (system basic chip) provides the following features: ◼ Support high voltage up to 400V and power range up to 3.7kW BLDC/PMSM applications. ◼ Support high voltage isolated 12V power supply, which for SBC, IPM and MCU power supply. ◼ Hardware support 3 types of current sampling solutions: single shunt, dual shunts and triple shunts; software support dual shunts in V1.0. ◼ Support multiple diagnose and protection covering UV, OV, OT, OC, Short, Stall Detection, etc.; ◼ Support speed/control commands from CAN/LIN/FreeMASTER; ◼ Support external watch dog for safety. the RDB hardware system block diagram is as below: The software package of S32K142-ECC RDB is available to enable user to evaluate the S32K142 based high voltage e-compressor motor control performance with out-of-box and build their own e-compressor motor control product prototype as a general high voltage motor control hardware platform. The software package has the following features: ◼ Support e-compressor control by FreeMASTER CAN/UART; ◼ Support e-compressor speed control and state feedback by CAN DBC file; ◼ Implemented advanced motor control algorithm, including low speed torque compensation, MTPA, 2-stage current alignment and enhanced ATO to make sure the motor robust start up and high efficiency; ◼ Support rich motor control diagnostic and protection: OV, UV, OC, OT, stall and phase loss and so on; ◼ Provide S32DS IDE and IAR for ARM IDE projects, support U-Multilink and J-LINK debugger; We have several S32K142-ECC RDB in stock, if you have the project and need the RDB for evaluation, please contact your local NXP or NXP dist FAE, Sales and Marketing. For technique support, contact raymond.tang@nxp.com  thanks, Best regards, Raymond

Hi Everyone, Here I'd like to share three S32K1xx SDK FlexCAN PD and PAL component sample projects to demonstrate its basic and advanced features: 1. S32K144_CAN_PAL_SamplePrj_Basic_TxRx_ID_FiltersConfig_SDKRTM3P0 Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PAL driver: 1. Configure to receiver the following exact 16 standard ID CAN message with RxFIFO 8x ID filter table with format type-B(2x 16-bit ID) Standard ID: 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x111, 0x222, 0x333, 0x444, 0x555, 0x666, 0x777, 0x788 The RxFIFO is configured to use CPU interrupt for CAN message receive, and CAN_PAL cannot support DMA for RxFIFO directly. Note: A. FlexCAN of S32K1xx dose not support to receive CAN-FD message frame with RxFIFO, so no CAN-FD support in this demo project. B. All the filter table elements must be configured to contain only standard or extend ID, if it contains both standard and extend ID, the IDE-bit mask will be ignored.  C. After RxFIFO enabled, MB0~MB5 is used as the RX FIFO, at least MB6~MB7 are used as the ID filter table(to store the acceptance ID), the actual available MB number is determined by RxFIFO ID filter table size, details please refer to section--55.4.6 Rx FIFO structure of S32K1xx RM Rev.12.1  2. Configure two extra individual MBs to receive: RX_MB1: 16 standard ID CAN 2.0 message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F and  RX_MB2: 4 standard ID CAN 2.0 message with the ID8 and ID9 masked(mask=0x4FF, acceptance ID = 0x256): 0x056, 0x156, 0x256 and 0x356 Both the RxFIFO and individual MBs RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure one individual MB to blocking transmit a standard CAN 2.0 message with ID = 0x100 periodically(period = 5ms), and also send back the received CAN messages(if it's available) to the CAN bus as a response. 4. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is commented by default, so manual recovery codes does not work. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is not done this sample project!!!  5. There 3 on-board RGB LED are used to indicate the FlexCAN working status: red RGB LED will be toggled after RXFIFO received a CAN message; blue RGB LED will be toggled after individual MB received a CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB 2.S32K144_CAN_PAL_CANFD_ClassicCAN_Mix_TxRx_Wakeup_SDKRTM3P0 Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PAL driver: 1. Configure to enable CAN-FD with 500 Kbit/s arbitration phase bitrate and 2Mbit/s data phase bitrate, so it can support both classic CAN 2.0 A/B and CAn-FD message frame transfer. Note: A. The RxFIFO is disabled to work with CAN-FD message frame. B. After CAN-FD enabled, CAN-FD message frame data length can support up to 64 Bytes, so the actual available MB number is determined by the max frame data length need to support, details please refer to section--55.4.5 FlexCAN message buffer memory map of S32K1xx RM Rev.12.1  C. In order to support bitrate bigger than 1Mbit/s for CAN-FD data phase with bitrate switch enabed, PE clock source of CAN_PAL should be configured to use peripheral clock(80MHz generated from SPLL) instead of 8MHz oscillator clock; 2. Configure 3 individual MBs to receive: RX_MB0: 16 extend ID CAN 2.0/FD message with the lower 4LSB masked(mask=0x1FFFFFF0, acceptance ID = 0xfff021): 0xfff020 ~ 0xfff02F RX_MB1: 16 standard ID CAN 2.0/FD message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F RX_MB2: 4 standard ID CAN 2.0/FD message with the ID8 and ID9 masked(mask=0x4FF, acceptance ID = 0x256): 0x056, 0x156, 0x256 and 0x356 Both the RxFIFO and individual MBs RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure 3 individual MBs to transmit: TX_MB0: send back any CAN(2.0/FD) messages received from RX_MB0; TX_MB1: send back any CAN(2.0/FD) messages received from RX_MB1; TX_MB2: send back any CAN(2.0/FD) messages received from RX_MB2; 4. Configure one individual MB(TX_MB3) to blocking transmit a standard CAN FD message with ID = 0x100 periodically(period = 5ms) and length = 64 bytes, and also send back the received CAN messages(if it's available) to the CAN bus as a response. 5. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is commented by default, so manual recovery codes does not work. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is not done this sample project!!!  6. Provided the sample codes of how to configure FlexCAN as the VLPS low-power mode wakeup source, RXD of FlexCAN0 is configured as GPIO IRQ interrupt with falling edge trigger before entering VLPS mode, and after wakeup, re-configure it back to RXD function. Note: A. S32K1xx FlexCAN is unable to work as the VLPS wakeup source B. After wakeup, it's necessary to call SDK clock_manager's API--CLOCK_SYS_UpdateConfiguration() to reconfigure the system clock, or it will use 8MHz SIRC, 48 MHZ FIRC and SPLL are disabled after wakeup. c. By default, after receive ID = 0x123(it can be configured via macro LP_REQUEST_ID in /include/Config.h ) standard CAN(CAN 2.0 or CAN-FD), the MCU will go to VLPS mode 7. There 3 on-board RGB LED are used to indicate the FlexCAN working status: blue RGB LED will be toggled after individual MB received a CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB 3.S32K144_FlexCAN_PD_SamplePrj_RxFIFO_DMA_Receive_SDKRTM3P0 Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PD driver: 1. Configure to receiver the following exact 16 standard ID CAN message with RxFIFO 8x ID filter table with format type-B(2x 16-bit ID) Standard ID: 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x111, 0x222, 0x333, 0x444, 0x555, 0x666, 0x777, 0x788 The RxFIFO is also configured to use eDMA channel 0 for CAN message receive, user can easily change to use CPU interrupt for RxFIFO in processor expert flexcan component configuration if required. Note: A. FlexCAN of S32K1xx dose not support to receive CAN-FD message frame with RxFIFO, so no CAN-FD support in this demo project. B. all the filter table elements must be configured to contain only standard or extend ID, if it contains both standard and extend ID, the IDE-bit mask will be ignored.  C. After RxFIFO enabled, MB0~MB5 is used as the RX FIFO, at least MB6~MB7 are used as the ID filter table(to store the acceptance ID), the actual available MB number is determined by RxFIFO ID filter table size, details please refer to section--55.4.6 Rx FIFO structure of S32K1xx RM Rev.12.1  2. Configure one extra individual MB(MB8) to receive 16 standard ID CAN 2.0 message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F; Both RxFIFO and individual MB RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure one individual MB(MB9) to blocking transmit a standard CAN 2.0 message with ID = 0x100 periodically(period = 5ms), and also send back the received CAN messages(if it's available) to the CAN bus as a response. 4. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is enabled by default, and manual recovery codes works. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is already done this sample project!!!  5. There 3 on-board RGB LED are used to indicate the FlexCAN working status: red RGB LED will be toggled after RXFIFO received any CAN message; blue RGB LED will be toggled after individual MB received any CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB Attached are the sample project for your reference, and details can also be fiound with the detailed comments in source codes. Hope it can help you, and any comments/questions are welcomed, and you can just ask in this thread and I will try to anwser them. Best regard, Enwei Hu(胡恩伟).  

Hello,      NXP does a big change on document structure.     Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM.   For example on S32K.    You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.'    Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC.     These steps are also fit for MPC57xx , S32R family. Cheers! Oliver

Dear all, I'd like to share some useful tips about S32DS for ARM v2018.R1 IDE and S32K1xx development  in Chinese as below: 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》； 《S32K SDK使用详解之S32 SDK软件编程思想详解》； 《S32K SDK使用详解之S32 SDK软件架构详解》； 《 S32K1xx系列MCU使用Tips--功能介绍及软件开发和硬件设计FAQ》； 《 S32K1xx系列MCU使用Tips--Flash加密后不断复位无法连接调试器的问题解决》； 《S32DS使用Tips--S32DS for Power V1.2 链接文件和启动过程详解》； 《S32K1xx系列MCU使用Tips之SDK软件架构和使用详解》； 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》； 《S32DS IDE使用Tips--应用工程调试常见问题(FAQ)答疑》； 《 S32DS 使用Tips之S32DS for Power不同版本之间的GNU工具链差异与外设寄存器位域访问问题总结》； 《 S32DS使用Tips之S32DS for Power v1.1应用工程升级到v1.2重新编译运行程序跑飞问题解决》； 《S32DS 使用tips--S32DS for ARM v1.3工程到S32DS for ARM V2.0迁移升级方法和注意事项》； 《  S32DS 使用 tips--工程属性配置(编译选项和C编译器、汇编器及链接器设置)》； 《 S32DS使用Tips--如何编译生成和调用静态库》； 《S32DS使用Tips--如何通过创建新的编译目标(Build Target)在同一个S32DS工程中同时编译静态库和应用程序》； 《 S32DS使用Tips--如何配置和使能Attach功能定位软件程序bug和完成bootloader与应用程序工程的联合调试》； 《 CodeWarrior与S32DS IDE使用 Tips之如何在应用工程中保留定义但未使用的全局常量、变量(用于参数标定)》； 《 S32DS 使用 tips--使用Flash from file下载S19或elf文件》； 《S32DS for ARM v2018.R1安装IAR Eclipse插件调用IAR工具链开发S32K系列MCU应用程序详解》 For more contents, please follow below link: “汽车电子expert成长之路”微信公众号最新最全原创技术分享文章列表 ; Hope this can help you and have a nice day~! Best regard, Enwei Hu(胡恩伟)

I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 

Where can I get s32k14x data sheet or reference manual???

***************************************************************************** *Detailed Description: *This example will show you how to configure Sbc_fs23 Driver. *It initialization of Sbc_fs23 with watchdog window disabled. The Sbc_fs23_InitDevice() must be done within the dedicated 256 ms INIT window. *It Disable regulator V2, then re-enable it again. FS0b pin is asserted due to V2 Undervoltage reaction setting configured in FailSafe Init Configuration tab. *If the example runs without errors, the D12 LED on S32K31XEVB-Q100 will light up Green; otherwise, it will light up Red. *The SPI data between FS23 and S32K311 are captured and attached to the project. *Use the analog input of a logic analyzer or an oscilloscope to monitor the signals of FS23_V2 (TP27) and FS23_FS0 (TP8) on the KITFS23SKTEVM board. *This example is migrated from Sbc_fs23_example_HLD_S32K344 *The method of migrating refers to the video "2.S32DS CT MCAL demo porting K344 to K312 based on RTD500": https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Tools-Part-How-to-port-RTD-s-existing-MCAL-demo-to-other/ta-p/1966315 *------------------------------------------------------------------------------ *Test HW: * S32K31XEVB-Q100 Board SCH-55131 REV A P32K311HV 0P98C * KITFS23SKTEVM Dev-kit SCH-53096 REV B2 MFS2320BMBB1EP * My S32K31XEVB-Q100 has an onboard PFS2320A0L1W1, but Step 13/14 of AN14041 mention that A0 devices are not supported, so S32K311 communicate with the FS23 on the KITFS23SKTEVM. *Connections: KITFS23SKTEVM | S32K31XEVB-Q100 ------------------------------|-------------------- SPI_CSB J28-2 | J12-5(PTB-17) SPI_MOSI J29-2 | J12-7(PTB-16) SPI_SCK J31-2 | J12-11(PTB-14) SPI_MISO J32-2 | J12.9(PTB-15) VCC J6-1 | J40-15 GND J6-2 | J40-13 - KITFS23SKTEVM: SW1 - position 2-3 , J30 - ON, J26 5-6 ON, J26 9-10 ON . - Connect KITFS23SKTEVM Dev-kit and S32K3 MCU via on-board Arduino headers. *SDK: * S32K3 RTD 4.0.0 (SW32K3_S32M27x_RTD_R21-11_4.0.0_D2311_DS_updatesite.zip) * FS23 RTD 1.0.0 (S32K3xx_SBC_FS23_R21-11_1.0.0_DS_updatesite_D2402_updated_D250115.zip) *Debugger: S32DS 3.5.8, OpenSDA/ PEmicro Multilink Universal FX *Target: internal_FLASH *Reference Documentation: * AN14041 FS23 quick start guide (Rev. 2.0 23 January 2025) * AN14129 FS23 implementation and behaviors (Rev. 2.0 13 December 2024) * FS23, Safety System Basis Chip (SBC) with Power Management, CAN FD and LIN Transceivers Data Sheet (Rev. 8.0 30 June 2025) *****************************************************************************

**************************************************************************************************** * Detailed Description: * This code demonstrates how to inject an ECC (Error Correction Code) fault into either DTCM0 * (Data Tightly Coupled Memory) or SRAM0 using the EIM (ECC Injection Module). * * When the processor reads corrupted data from DTCM0 or SRAM0, an ECC error is detected, resulting in: * - A Bus Fault exception raised by the core. * - An error report generated by the ERM (Error Reporting Module), which can also trigger an interrupt. * * By default, the ERM interrupt has a lower priority than the Bus Fault exception. In this example, * the Bus Fault exception priority is intentionally lowered so that the ERM interrupt is serviced first. * This ensures the system can respond to the ERM interrupt before the core's Bus Fault handler executes. * * IMPORTANT: The interrupt vector table must not reside in SRAM0 or DTCM0 when injecting an * uncorrectable ECC fault into these memories. Otherwise, the ECC fault would corrupt the vector * table during a fetch, leading to unpredictable behavior. * Always check the VTOR (Vector Table Offset Register) * to confirm the vector table location before performing ECC fault injection. * * Memory Selection: * You can select which memory to inject the ECC fault into using the following macros: * #define SRAM0 * #define DTCM0 *************************************************************************************************** * ------------------------------------------------------------------------------------------------* * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: NA * Debugger: Lauterbach Trace32 * Target: internal_FLASH ****************************************************************************************************

Hi everyone, Welcome to the NXP Tech Days 2025 training session AUT-T437: Hands - On Workshop: Explore Ethernet Integration on the S32K3 Microcontroller. My name is Alejandro Flores Triana (Alex) and I will be your guide during this conference. I am an Automotive Applications Engineer supporting different OEMs, Tier1s, Partners and other internal NXP teams on topics related to communication protocols (e.g. CAN, LIN, SPI, I2C, Ethernet, etc.). The idea of this session is for you to understand how to program the S32K3 Ethernet interface using NXP Real-Time Drivers (RTDs) – Autosar MCAL Layer. We will use a base project and together modify it to create a simple Ethernet application. Therefore, to be ready follow the steps below to get your environment up and running before the session. On your laptop, install the NXP Software environment described in the attached presentation: Hands - On Workshop: S32K3 Ethernet Prerequisites.   Once you have the NXP software environment installed, download the attached project: S32K344_ETH_MCAL_TechDays.exe.   Run the .exe project with administrator rights. Accept the license and install in the desired folder.         Open the NXP Design Studio. Click File -> Import -> Existing Projects into Workspace.   Select root directory and browse the folder where you downloaded the project.   Select Copy projects into workspace. Then, click Finish.   Select the project. Click on the arrow next to the hammer. Click on Debug_FLASH. Then you are ready for the session! See you soon. Best Regards, Alejandro Flores Triana

This document provides a brief explanation of the Excel-based calculator developed to assist with the computation of TX Arbitration Start Delay as described in the S32K3 reference manual. The tool implements the formula provided in the datasheet, allowing users to input relevant parameters and automatically calculate the delay values. It is intended to support engineers in evaluating CAN transmission timing and optimizing arbitration performance in S32K3-based applications.   1.Fill in the clock and CBT and FDCBT configuration parameters according to your requirements. For example, we fill the parameters according Case 3:  Then we can get the TASD value for non-FD frames is 24.05.   Please note that this summary is not officially released by NXP. It is a personal summary for reference only. If there are any errors, please contact me.

****************************************************************************************************** * Detailed Description: These demos showcase how to configure the eMIOS module on the S32K3 series, highlighting various operational modes and their implementations using the RTD high-level drivers, commonly known as MCAL drivers. The implementations demonstrated in these examples follow the approach outlined in the community thread:  S32M27x/S32K3 – eMIOS Usage. * Connections:  ******************************************************************************************************* * Test HW: S32K31XEVB-Q100 * MCU: S32K311 * Debugger: S32DS 3.6.2, OpenSDA/ PEmicro Multilink Universal FX  * Target: internal_FLASH ******************************************************************************************************* * Important information:  The OPWMT channel does not support the notification function. In this mode, the Sn[FLAG] bit is only set upon an AS2 match, which defines the generation of a trigger event within the PWM period. As a result, OPWMT mode cannot support notifications based on signal edges. A bus exception may occur during the execution of Mcl_Init() if the eMIOS clock is not properly enabled. To avoid this issue, ensure that the eMIOS peripheral clock is activated in the configuration settings under: MCU driver → McuModuleConfiguration → McuModeSettingConf → McuPeripheral *******************************************************************************************************

**************************************************************************************************** * Detailed Description: * * - CMU errors cannot be injected by any means other than manipulating the CMU thresholds, * except for FXOSC_CLK, which can be physically disrupted on the PCB. * * - CMU_FC_0 (FXOSC_CLK) is configured for **synchronous interrupt** on both LFF and HFF CMU events. * - CMU_FC_3 (CORE_CLK) is configured for **asynchronous destructive reset** triggered only by the LFF event; the HFF event is ignored. * - CMU_FC_4 (CORE_CLK) is configured identically to CMU_3: **asynchronous destructive reset** on LFF only; HFF is ignored. * - CMU_FC_5 (HSE_CLK) can be configured by the HSE_B core only. * Refer to the Reference Manual rev.10, Figure 122. Frequency checking (FC) instances * * - The configuration must be identical in both the MCU MCAL driver and the Clock Configuration Tool (clock details). * - To inject a specific CMU error, define one of the following macros: `INJECT_CMU_0`, `INJECT_CMU_3`, or `INJECT_CMU_4`. * * Behavior After Destructive Reset: * - Following a destructive reset (either `MCU_CORE_CLK_FAIL_RESET` or `MCU_AIPS_PLAT_CLK_FAIL_RESET`), * execution will halt in the `while(wait)` loop. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: RTD 6.0.0 * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************

[S32K3 tool part]：How to use IAR compiler or IAR project to compile MCAL project   1.    Abstract      Through regular observation, it has been found that there are still many customers using platforms such as MCAL+IAR, including those using IAR compilers and those directly using IAR IDEs. In fact, when I was working on industrial MCUs in the past, I also particularly liked IAR IDE for its fast compilation speed, high compilation efficiency, and small code generation. However, when I came to auto MCU, I found that its popularity was not very high, and I also noticed that some customers encountered various problems when importing MCAL into IAR. Therefore, I will directly write a tool article on how to use IAR compiler or IAR IDE project to compile NXP S32K MCAL in combination with EB tresos MCAL. This article uses S32K344 combined with RTD600 to illustrate the compilation of MCAL projects using IAR compiler and the direct import of MCAL into IAR IDE projects 2. IAR Complier with S32K3 RTD MCAL project 2.1 S32K3 HW and SW SW32K3_S32M27x_RTD_R21-11_6.0.0 S32K3X4-EVB Based on Dio_TS_T40D34M60I0R0 IAR：IAR EW for Arm 9.70.1 EB tresos29.0.0 2.2 Compile MCAL project steps using IAR compiler CMD method 2.2.1 Copy one RTD MCAL new project Open path C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins Copy Dio_TS_T40D34M60I0R0 , rename it as Dio_TS_T40D34M60I0R0_IAR Fig 1 2.2.2 Complie EB tresos project Use EB tresos tool open the following EB tresos project ： C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0_IAR\examples\EBT\S32K3XX\Dio_Example_S32K344\TresosProject Generate code: Fig 2 2.2.3 Vscode open Dio_TS_T40D34M60I0R0_IAR project Use VS code open the following path folder: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0_IAR\examples\EBT\S32K3XX\Dio_Example_S32K344 Of course, you can also directly open this folder path using the command line, as long as you ensure that it is in the same layer path as the. mk and makefile scr Fig 3 2.2.4   Project_parameters.mk modification Mainly modify the following points: TOOLCHAIN = iar IAR_DIR = C:/IAR/ewarm-9.70.1 TRESOS_DIR = C:/EB/tresos_29_0_0 PLUGINS_DIR = C:/NXP/SW32K3_S32M27x_RTD_R21-11_6.0.0/eclipse/plugins The path of IAR must be consistent with the version of IAR software used to ensure that the corresponding IAR compiler can be found. Fig 4 2.2.5   Check_build_params.mk modification Add the following content to check_build_params.mk： else ifeq ($(TOOLCHAIN),iar) ifeq ("$(wildcard $(IAR_DIR)/arm/bin/iccarm.exe)","") $(error Invalid path set to the IAR compiler. \ The provided path: from project_parameters.mk IAR_DIR=$(IAR_DIR) is invalid!) Endif Fig 5 2.2.6        Makefile modification   Makefile need the following 5 points modification: （1）Compilier change ifeq (${TOOLCHAIN},iar) CC := $(IAR_DIR)/arm/bin/iccarm.exe LD := $(IAR_DIR)/arm/bin/ilinkarm.exe AS := $(IAR_DIR)/arm/bin/iasmarm.exe # Intel Hexadecimal Flash image tool GENHEX := $(IAR_DIR)/arm/bin/ielftool.exe HEX_OPTS := --ihex OUT_OPTS := -o endif Fig 6 (2) SRC_DIRS  add TOOLCHAIN SRC_DIRS += $(foreach mod,$(MCAL_MODULE_LIST),$(PLUGINS_DIR)/$(mod)_$(AR_PKG_NAME)/src) \ $(foreach mod,$(MCAL_MODULE_LIST_ADDON),$(PLUGINS_DIR_ADDON)/$(mod)_$(AR_PKG_NAME_ADDON)/src) \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src/m7 \ $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/startup/src/m7/$(TOOLCHAIN) Fig 7 (3) Linker file  modification ifeq ($(LOAD_TO),flash) ifeq (${TOOLCHAIN},iar) LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/${TOOLCHAIN}/linker_flash_$(DERIVATIVE_LOWER).icf else LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_flash_$(DERIVATIVE_LOWER).ld endif else ifeq (${TOOLCHAIN},iar) LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_ram_$(DERIVATIVE_LOWER).icf else LINKER_DEF:= $(PLUGINS_DIR)/Platform_$(AR_PKG_NAME)/build_files/$(TOOLCHAIN)/linker_ram_$(DERIVATIVE_LOWER).ld endif endif Fig 8 (4) Complier options change ifeq (${TOOLCHAIN},iar) ################################################################################ # iar Compiler options ################################################################################     clib        := $(IAR_DIR)/arm/lib     CCOPT           +=  --cpu=Cortex-M7 \                         -DAUTOSAR_OS_NOT_USED \                         -DUSE_MCAL_DRIVERS \                         --fpu=FPv5-SP \                         --cpu_mode=thumb \                         --endian=little \                         -e \                         -Ohz \                         --debug \                         --no_clustering \                         --no_mem_idioms \                         --do_explicit_zero_opt_in_named_sections \                         --require_prototypes \                         --no_wrap_diagnostics \                         --diag_suppress=Pa050 \                         $(MISRA) \                         -D$(PLATFORM) \                         -D$(DERIVATIVE) \                         -DIAR \                         -DUSE_SW_VECTOR_MODE  \                         -DENABLE_FPU \                         -DD_CACHE_ENABLE \                         -DI_CACHE_ENABLE                             LDOPT           :=  --entry _start \                         --enable_stack_usage \                         --skip_dynamic_initialization \                         --no_wrap_diagnostics \                         --cpu=Cortex-M7 \                         --fpu=FPv5-SP                             ASOPT           :=  $(ASOPT) \                         --cpu Cortex-M7 \                         --cpu_mode thumb \                         -g \                         -r \                         -DMULTIPLE_CORE   endif   Fig 9 Fig  10 So how did these IAR compilation options come about? You can refer to the release note of RTD600, which contains corresponding descriptions Fig 11 (5) Elf related change ifeq (${TOOLCHAIN},iar) %.elf: %.o $(LINKER_DEF)               @echo "Linking $@"               @$(LD) $(ODIR)/*.o $(LDOPT) --config $(LINKER_DEF) --map $(ODIR)/ -o $(ODIR)/$@@               @$(GENHEX) $(HEX_OPTS) "$(ODIR)/$(ELFNAME).elf" "$(ODIR)/$(ELFNAME).hex" else %.elf: %.o $(LINKER_DEF)               @echo "Linking $@"               @$(LD) -Wl,-Map,"$(MAPFILE)" $(LDOPT) -T $(LINKER_DEF) $(ODIR)/*.o -o $(ODIR)/$@@               @$(GENHEX) $(HEX_OPTS) "$(ODIR)/$(ELFNAME).elf" $(OUT_OPTS) "$(ODIR)/$(ELFNAME).hex" endif   Fig 12 2.2.7   Build to generate elf Commander: make clean make build to generate the elf files： Fig 13 After generation, the elf can be burned onto the S32K344 EVB board for testing. The test results show that the onboard red light is flashing, indicating that the IAR compiler can work in command-line mode. 3. Import RTD MCAL to IAR IDE project This chapter explains how to create an IAR IDE project and import MCAL drivers to implement S32K3 MCAL combined with EB tresos for running. 3.1 MCAL IAR IDE project 2 methods Difference between two methods and how to import MCAL drivers: (1) Directly copy the RTD MCAL driver to the IAR IDE project directory (2) Connect the IAR IDE project driver to the original RTD driver path Fig 14 3.2 MCAL IAR IDE project import steps 3.2.1 create the new RTD MCAL IAR project folder    Create a new folder, named as：S32K344_DIO_MCAL_RTD600_IAR 3.2.2 create the sub folder for IAR project       Generate：EB tresos project code       Include：app related include file       Mcal： mcal driver copy from RTD       src： project main file       Tresos_Project：EB tresos project Fig 15 3.2.3 create EB tresos project (1) Create the EB tresos project in the followign path：  S32K344_DIO_MCAL_RTD600_IAR\Tresos_Project\Mcal_Dio_S32K344_RTD600_IAR   (2)Add modules: BaseNXP, Dem, Dio, EcuC, Mcu, Platform, Port, Resource   (3)Copy RTD xdm files in the following path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\examples\EBT\S32K3XX\Dio_Example_S32K344\TresosProject\Dio_Example_S32K344\config to： S32K344_DIO_MCAL_RTD600_IAR\Tresos_Project\Mcal_Dio_S32K344_RTD600_IAR\config   (4)EB tresos Generate project EB tresos code will be generated to folder: S32K344_DIO_MCAL_RTD600_IAR\Generate Fig 16 3.2.4 Copy RTD related drivers to IAR project folder (1) BaseNXP: header, include, src (2)Det:  include, src (3)Dio:  include, src (4)Mcu:  include, src (5)Platform: build_files, include, src, startup (6)Port: include, src (7)Rte: include, src Copy RTD folder to IAR project is one method, if don’t want to copy the file, also can use the linker to add the RTD install path drivers directly. Fig 17 3.2.5 IAR IDE create IAR project   (1) Project->Create new project   (2) In the IAR project, add group   The related folder in project can be structured like the fig 18, which contains:   Generate: Include and src->EB tresos project generate code   Mcal:  Base, Det, Dio, Mcu, Platform, Port, Rte->Mcal driver   Src: Main.c->project main code      (3) Add RTD mcal related drivers to IAR project The RTD MCAL related driver files can be directly downloaded from the RTD installation path or copied to a folder in the IAR project, and both methods yield the same result. Fig 18 （4）IAR project platform folder added result: Fig 19 （5）main code add Main.c can copy from path: C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\examples\EBT\S32K3XX\Dio_Example_S32K344\src to S32K344_DIO_MCAL_RTD600_IAR\src Comment:  //#include "check_example.h"  // Exit_Example(TRUE);   3.2.6 IAR project options configuration (1)General options->Target->Device->NXP S32K344 (2)C/C++ Complier->Preprocessor Addional include directories: Use IAR project folder drivers which copied from RTD install path, the directories are： $PROJ_DIR$\Generate\include $PROJ_DIR$\mcal\BaseNXP_TS_T40D34M60I0R0\header $PROJ_DIR$\mcal\BaseNXP_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Mcu_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Rte_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\startup\include $PROJ_DIR$\mcal\Det_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Dio_TS_T40D34M60I0R0\include $PROJ_DIR$\mcal\Port_TS_T40D34M60I0R0\include $PROJ_DIR$\include If use the RTD install path drivers, use the following directories： $PROJ_DIR$\Generate\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\BaseNXP_TS_T40D34M60I0R0\header C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\BaseNXP_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Mcu_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Platform_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Rte_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Platform_TS_T40D34M60I0R0\startup\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Dio_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Port_TS_T40D34M60I0R0\include C:\NXP\SW32K3_S32M27x_RTD_R21-11_6.0.0\eclipse\plugins\Det_TS_T40D34M60I0R0\include $PROJ_DIR$\include   Defined symbols: S32K3XX S32K344 IAR USE_SW_VECTOR_MODE D_CACHE_ENABLE I_CACHE_ENABLE ENABLE_FPU   Extra options: --no_clustering --no_mem_idioms --do_explicit_zero_opt_in_named_sections --require_prototypes --no_wrap_diagnostics   Languate 1:   Check Require prototypes   Diagnostics Suppress these disgnostics: Pa050 Fig 20 (3)Linker: Two points need to be added： $PROJ_DIR$\mcal\Platform_TS_T40D34M60I0R0\build_files\iar\linker_flash_s32k344.icf Library->Entry symbols: _start Fig 21 (4)Debugger Setup: PE micro, run to main Extra Options: Use command line options: --drv_vector_table_base=__ENTRY_VTABLE Fig 22 3.2.7  Build IAR project Project->Rebuild All Fig 23 3.2.8  Test result Download and debug result: Fig 24 After downloading and running, the red led is blinking on the board, indicating that the IAR IDE MCAL import method project has been successfully run.  

* ================================================================================================== * Detailed Description: * * This example shows how to implement ADC continuous scan with DMA read. * ADC1 is set to perform continuous scan of 4 channels (S10/S11/S12,S13) with DMA request enabled * for last channel S13. DMA reads respective sequential ADC data registers in one major loop. * * ADC1 channel S10 is connected to board's potentiometer, converted value is used to dim board's LED. * * ================================================================================================== * Test HW: S32K312EVB-Q172 * MCU: S32K312_172LQFP * Compiler: S32DS 3.6.3 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: On-Board Debugger (J40), Lauterbach * Target: Internal_FLASH * ==================================================================================================   Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.  

Abstract This example presents an use case for complementary PWM outputs with dead-time insertion and hardware ADC triggering using eFlexPWM, TRGMUX, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs. Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_94 -> GPIO1_GPT J62-5 -> PTD2 -> pwm_0_a, 2 -> PWM1 J62-6 -> PTD3 -> pwm_0_b, 2 -> PWM2 J62-30 -> PTD24 -> pwm_0_a, 0 -> PWMT J62-2 -> PTC31 -> siul2_gpio_95 -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_102 -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB)   Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U)   Detailed Description: The Compare Value of GPT eMIOS 0 channel 0 generates a time-out period. Once time-out is reached its eMIOS notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eFlexPWM0 module is used for generating PWMs and hardware ADC triggering. The eFlexPWM0 Submodule 2 is employed to generate center-aligned complementary PWM outputs (PWM1 and PWM2) with dead-time insertion. The eFlexPWM0 Submodule 0 generates another independent PWM output (PWMT) and is utilized to generate the trigger signal for analog data capturing within the same PWM period —happens at half the time high in this case—using VAL0 register. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: • ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 • ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project   References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32K39-37-36 – eMIOS/BTCU/SAR-ADC/DMA – [RTD600] [S32K Knowledge Base]   Application Software: - S32K396_RTD600_eFlexPWM_TRGMUX_BCTU_SARADC_DMA Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

Abstract This example presents an use case for analogue data capturing using eMIOS, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs.   Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_xx -> GPIO1_GPT (D0) J58-1 -> PTE14 -> emios_0_ch_19_z -> PWM1 J58-2 -> PTG9 -> siul2_gpio_xx -> GPIO2_eMIOS_Trigger J62-2 -> PTC31 -> siul2_gpio_xx -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_xx -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB) Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U)   Detailed Description: The Compare Value of GPT eMIOS_0_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels, enabling synchronization between other them—there is just one PWM in this case. This synchronization ensures that channels share the same time base, thereby defining a common period for their operation. The emios_0_ch_19_g channel is configured as OPWMT mode, which offer more flexibility for triggering. An interrupt is requested on every flag event, during which GPIO2 is toggled—happens at half the time high in this case. This flag event, can be configured using Trigger parameter. For more details about eMIOS, please refer to S32M27x/S32K3 – eMIOS Usage, considering differences for porting from S32K3 to S32K39-37-36 in AN14301. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project   References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32M27x/S32K3 – eMIOS Usage [S32M Knowledge Base] S32M27x/S32K3 – eMIOS/BTCU/ADC/DMA – [RTD600] [S32M Knowledge Base] S32K39-37-36 – eFlexPWM/TRGMUX/BCTU/SAR-ADC/DMA – [RTD600] [S32M Knowledge Base] Application Software: - S32K396_RTD600_eMIOS_BCTU_SARADC_DMA_Ip_example Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

*******************************************************************************  The purpose of this demo application is to present a usage of the  FS26 watchdog timer refresh using the SBC_FS26 CDD  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * FS26 : CDD 2.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Please Modify attached code, and add this line of code, in this function Sbc_Wdg_Refresh_Notification  :-- Gpt_StopTimer(GptConf_GptChannelConfiguration_GptChannelConfiguration_0);     This change will make the example work for even starting FS26, driver at 6 msec and above.   Watchdog type :-- NXP eval boards has ASIL-D FS26 part with challenger watchdog. The OTP of FS26 on the board uses challenger watchdog. Change watchdog in code :-- FS26 watchdog is started in disabled mode (means infinite period). Later on we change the watchdog time in the code :--     Array Index for watchdog refresh timing  :-- Example will run once you press switch USER_SW0 connected on PTB26 on the Evaluation board :-- Please add this type of check in your code, during development process so that, avoid any error due to FS26 watchdog mis trigger. When you use Debug FLASH then in that case code goes to flash memory & can cause your MCU to frequent RESET, which caused issue for reprogramming the NEW firmware on the board FLASH memory. If we add this type of check then we can avoid the Faulty FS26 Software to stop misbehaving before flashing new firmware on the board.   In CDD-2.0.0, FS26 goes to INIT_FS state here  :--- Sbc_fs26_InitDevice() --> Sbc_fs26_CheckStateAndGotoInitFS()   In CDD-2.0.0, If we start the Watchdog in enabled mode, watchdog notification function to refresh watchdog is called from this function  :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() -->      In CDD 2.0.0, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() :--- --> Sbc_fs26_ExitDebugMode() --> Sbc_fs26_ReleaseSequence()   In CDD 2.0.1, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() --> Sbc_fs26_ExitDebugMode() ===================== CDD-2.0.1 example ================= RTD used :-- S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip Watchdog started in the Disabled mode (i.e infinite Period) then watchdog period is changed in the code main() function :--   Driver configuration :--   These function get executed :--       One bug in RTD   ---> S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip :-- RTD driver Bug is corrected like this :--   

******************************************************************************************************* * Detailed Description: This demo showcases how to use eMIOS in Input Capture mode with DMA. It demonstrates how timestamp data from captured input signals is stored and how a GPIO toggle provides a simple visual confirmation that the interrupt is being triggered as expected.   * eMIOS Pwm: Configures EMIOS 0 Channel 1 as OPWMB (Output Pulse Width Modulation Buffered). This channel generates a waveform that will be captured by Channel 9 * eMIOS Icu with DMA: Configures EMIOS 0 Channel 9 in ICU_MODE_TIMESTAMP using SAIC (Single Action Input Capture) mode. This channel captures the timestamps of the waveform generated by Channel 1. After a predefined number of captures, a DMA interrupt is triggered. ******************************************************************************************************* * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Debugger: S32DS 3.6.2, OpenSDA * Target: internal_FLASH *******************************************************************************************************

This post presents two complementary FlexCAN communication examples for the S32K3X4EVB-T172 evaluation board, showcasing both low-level IP layer and AUTOSAR MCAL layer implementations. These examples are basic routines for configuring the component in normal/user mode, as the RTD examples are configured for loopback mode. To test CAN communication, another board or a CAN analyzer must be used. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS 3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------  Example 1: FlexCAN IP Layer This project demonstrates a basic FlexCAN setup using the IP-level driver. It configures a standard CAN message; with transmission through polling and reception using interrupts. The TJA1153 transceiver is initialized through a custom configuration sequence. An ACK message is sent upon each reception. The GREEN LED toggles every 10 received messages. Message buffer is configured to accept STD ID 0x123 with  FlexCAN_Ip_SetRxIndividualMask()  &  FlexCAN_Ip_ConfigRxMb() .  Example 2: FlexCAN MCAL Layer This project uses the AUTOSAR MCAL stack, leveraging  Can_43_FLEXCAN  and  CanIf  modules for CAN communication. Transmission is done via polling, while reception is configured via interrupts. STD ID is set to 0x123, and acceptance mask is set to 0x0 (accept all IDs). The same TJA1153 transceiver is used. CAN messages are sent and received using  CanIf  callbacks. The GREEN LED toggles every 10 received messages. TJA1153 is used in both examples with macros TJA1153 & TJA1153_EVB_TRCV respectively. If not defined, standard transceiver initialization is done (CAN0_STB & CAN0_EN pins set to HIGH).  These examples are provided as is with no guarantees and no support. These are basic routines meant to be used as reference only.