https://community.nxp.com/docs/DOC-340244 

The NXPNCI-KDS_Example for the PN7120/PN7150 Arduino interface boards available in NXP webpage at the time of publishing this document includes a project compatible with KSDK v2.0 for FRDM-K64F platform. With the latest KSDK v2.1 some changes in the drivers along with the later FreeRTOS v9.0.0 make the build process fail when following the instructions in the application note AN11845 NXP NCI KDS Example due to incompatibilities. Meanwhile until the project in NXP webpage is updated there is a temporary project attached to this document fixed to work with KSDK v2.1. The steps to build this project are the same as explained in the appnote, summarized below: - Download and install KSDK v2.1 for FRDM-K64F using MCUXpresso SDK online builder: Welcome to MCUXpresso | MCUXpresso Config Tools  Create a new workspace in KDS IDE. Import the "NXPNCI-KDS_Example_KSDK2.1" project from the archive file. Update the PROJECT_KSDK_PATH build variable according to the installation path of KSDK v2.1. Build the project. For more details please refer to the application note AN11845. Regards! Jorge Gonzalez

https://community.nxp.com/docs/DOC-340389 

The latest NXP-NCI example is rev 1.6, and when you run this demo with the lpc11xx board, for example, lpc1115 rev A, and the OM5577, you may meet the following issue: The problem is due to two aspects: one is hardware and the other is software. For hardware solution, besides following what is described in AN11658 section 2.4 LPC11xx, you have to do one more thing: a) The I2C lines are not pulled-up: LPC11xx doesn't offer internal pull-up setting of the I2C lines so external pull-up resistors must be added. For software solution, the function of Sleep()( in tool.c) was optimized too much, and it didn't meet the timing requirement of OM5577, so we should let the IDE ignore it. The solution I use is as below: __attribute__((optimize("O0"))) void my_func() { blah } You may check the attachment for details. The result is shown as below: Original Attachment has been moved to: tool.c.zip

This porting guide is for FRDM-K82F, and it can also be used for any other platform supported by KSDK 2.2. The released NXPNCI-KDS_Example_KSDK2.2 is based on FRDM-K64F, so before porting, we need to configure and download KSDK 2.2 for FRDM-K82F. Please make sure you have selected Kinetis Design Studio before downloading. After downloading, extract the package to some folder like below: and change PROJECT_KSDK_PATH to this folder: Change project settings as below: Remove all files in the folder of drivers, and import new source files as below: and similar procedure for "startup" folder and "utilities" folder: Replace the source files in board folder with the files from some ksdk demo like hello_world: FRDM-K82F uses PTC3 for NCI_IRQ pin, PTC9 for NCI_VEN pin, and PTA1 and PTA2(I2C3) as the I2C interface. so add definition in board.c and modify BOARD_InitPins() as below: Change linker settings: -Build -Debug settings -Test Result:

In the case, the Reader output power cannot be further reduced with the help of the tuning and TXLDO settings (e.g. EMI reasons)  Then further reduction can be done using DPC settings. The idea is to use just one DPC entry and adjust the GSN value as shown below: DPC Settings:    The DPC Entries (1-19) have been deactivated (Index Activate ->0), and only Entry 00 stays active.    An example (RF Field measured using a scope probe): No DPC, TXLDO 5V    NO DPC, TXLDO 2.7V   DPC Activated, One Entry, GSN-> 0x05   DPC Activated, One Entry, GSN-> 0x01   Please consider that the reading performance will be impacted. 

This article describes how to evaluate ULPCD feature toghether with PN7642 EVK (OM27642EVK) and NFC Cockpit.  1// Disable DC-DC in EEPROM  OM27642EVK does not required any HW changes for ULPCD. User is only required to change the following settings in EEPROM  (disable DC-DC converter). Address: 0x0000 (Secure_Lib_Config) Value: 0x21  2//Set required ULPCD settings in EEPROM  The default settings can be used as a starting point as such. The optimum threshold for OM27642EVK is between 5-10. Below 5, user can observe higher occurrence of fake detection  Above 10, the detection range might drop significantly.  3// Perform "Reads HF Attenuator"  Once the required ULPCD settings is set (Guard times, Threshold....). Then User has to perform "Reads HF Attenuator". This will read and write the HF Attenuator value in the EEPROM at the address 0x63A (Secure_Lib_Config).  4//Enable that the RSSI value is calculated based on HF attenuator value  User is required to set most significant bit (7) to 1b. This will enable RSSI calculation based on the current HF attenuator value.  Example: If the HF Attenuator value is 0x0B, user has to write 0x8B in the eeprom field.  Note that if user reads the HF attenuator again, this step must be repeated.    Note: This has been updated in NFC Cockpit version 8.3.0. User needs to "check" the HF Attenuator check box.    5// Perform ULPCD Calibration and check RSSI Value  User can now perform the ULPCD Calibration and check the RSSI value by reading PCRM_ULPCD_STS register.  For OM27642EVK, the RSSI value for unloaded antenna is typically around 1500dec - 1550dec. 6//Enter ULPCD mode  User can enter the ULPCD mode. The board will be again connected once the load change is detected (e.g. NFC card or smarphone in the antenna proximity).

Prerequisites:  PN5190 instruction layer-> https://www.nxp.com/docs/en/user-manual/UM11942.pdf NFC Cockpit -> https://www.nxp.com/products/rfid-nfc/nfc-hf/nfc-readers/nfc-cockpit-configuration-tool-for-nfc-ics:NFC-COCKPIT   In case of PN5190, the NFC cockpit can only show a generic error messages. More detailed error description has to be decoded from the received "FrontEnd Packets" 1. See an example of the error returned after ULPCD calibration    2.  The Errors description is descibred in  PN5190 instruction layer UM. However, the error has to be "decoded"  →> Take the received packets before the error ntf. in NFC Cockpit → 80 00 0C 02 02 00 00 BB 07 00 00 23 00 00 00 Where:  2.1. Decode the "Event" 02 02 (Little endian format) → General_Error_Event + LPCD_Calibration_Done_Event   2.2 Check LPCD_CALIBRATION_DONE_EVENT  07 BB (Little endian format) → Measured RSSI Value    2.3. Check the GENERAL_ERROR_EVENT  00 23 (Little endian format) → Definition of the general error event → Error is : GPADC_ERROR, CLOCK_ERROR and XTAL_START_ERROR  

This article provides information on the expected NFC communication range for NXP products (Connected tags) when used with various mobile phones and the CLRC663 reader.   1// NFC Antenna 54 mm vs 27 mm (NTAG 5 Boost Antenna 10 mm vs 10 mm)    1.1// Used antenna   1.2// Results  Note: NTAG5 Link - Energy harvesting is disabled      2// NFC Antenna 25 mm vs 18 mm    2.1// Used antenna   2.2// Results Note: NTAG5 Link - Energy harvesting is disabled      3//NFC Antenna 25 mm vs 18 mm with "filling"    3.1// Used antenna    3.2// Results    Note: NTAG5 Link - Energy harvesting is disabled 

Step 1:  Disable the DCDC in settings (Valid for PNEV5190B and OM27642EVK) Write 0x21 into EEPROM PWR_CONFIG (address: 0x0000) This disables the DCDC. & selects that the VUP must be supplied with the same supply voltage as VBAT = VBATPWR. Do not enable RF afterwards, before the hardware is modified properly! Enabling the RF without supplying the VUP might kill the PN5190/PN7642! Step 2: Supply VUP = VBATPWR  Connect jumper J13 positions: 1-2: This supplies the VUP with VBATPWR = 3.3V PN5190 EVK: Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.    PN7642 EVK:  The OM27642EVK does not require any jumper settings (DC-DC is not used by default), the User must only disable DC-DC in EEPROM (address 0x0000, value 0x21) Then you can turn-on RF and perform ULPCD   Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.  Also, R8 shall be placed   

A user can evaluate the current consumption of PN7642 in low power modes with the help of the PN7642 Evaluation Board (OM27642) and:  MCUXpresso SKD example (LPCD)  NFC Cockpit or MCUXpresso SKD example (ULPCD) NXP defines the current consumption in ULPCD/LPCD as VBAT current + VDDIO current for the LPCD/ULPCD cycle time of 330 ms. Make sure that DC/DC is disabled.  Where:  VBAT current = VBAT_Current + VBATPWR_Current + VUP_Current See the snapshot from the PN7642 Datasheet below:    See where to measure the currents on PN7642 EVK: J63 and J64 are used for enabling/disabling the LEDs that are connected to PN7642 GPIOs. They must be disabled for VDDIO current measurement.  A modification of R69 and R70 is necessary to perform the current measurement on VDDIO in LPCD mode.   1. ULPCD current consumption evaluation For the ULPCD evaluation, the NFC Cockpit or SDK example can be used. In this article, we will focus on evaluation using the NFC Cockpit.  See the used ULPCD configuration:    Note: The current should be measured as an average over, e.g., 10 seconds.  The ULPCD current can be evaluated separately, as shown in the following chapters  2.1 VBAT Current measurement 2.2 VBATPWR Current measurement 2.3 VUP Current measurement  2.4 VDDIO Current measurement  This might be helpful to understand the contribution of each current in ULPCD.  The overall average current can also be measured directly, as shown in  2.5 Overall ULPCD current measurement    2.1 VBAT Current measurement    In this case, the VBAT current is approximately 13,7 μA. 2.2 VBATPWR Current measurement   In this case, the VBATPWR current is approximately 2,1 μA. 2.3 VUP Current measurement    In this case, the VUP current is approximately 5,5 μA. Note: This current depends on the ULPCD VDPPA settings + Antenna Impedance tuning and RF_ON time  2.4 VDDIO Current measurement  Note: Before VDDIO measurement, place jumpers J63 and J64 on PN7642 EVK. This will disable LEDs that are connected to PN7642 GPIOs.    In this case, the VDDIO current is approximately 3,7 μA.  Then the overall current comsumption in ULPCD is I_VBAT+I_VBATPWR+I_VUP + I_VDDIO= 13,7 + 2,1 + 5,5 + 3,7 μA = 25 μA 2.5 Overall ULPCD current measurement  To measure all currents together, a user can create a measurement fixture as shown below:  Real setup :  Then the overall results look as follows:   As can be seen, the directly measured ULPCD current consumption is around 24 μA. 2. LPCD current consumption evaluation The user has to import the example (pnev7642fama_nfc_low_power_mode_Pub) from the PN7642 SDK.  Before building it, the following change in the code has to be made:  -> Comment line 84   A user can adjust the LPCD cycle time as shown below:   1.1 VBAT Current measurement    In this case, the VBAT current is approximately 123 μA. 1.2 VBATPWR current measurement  In this case, the VBAT_PWR current is approximately 91,8 μA. 1.3 VUP Current measurement  In this case, the VBAT_PWR current is approximately 32,8 μA.  Note: This current depends on the LPCD VDPPA settings + Antenna Impedance tuning  1.4 VDDIO Current measurement Note: Before VDDIO measurement, place jumpers J63 and J64 on PN7642 EVK. This will disable LEDs that are connected to PN7642 GPIOs.  The VDDIO current measurement requires the following steps:  Run the "pnev7642fama_nfc_low_power_mode_Pub" example  Once the example is running, disconnect the debugger (J-link, LPC-Link...) from J21 (NFC Debug connector)    Remove R70  Populate a 10K resistor on the R69 position (it disables the SWD interface) Once the measurement is done, change it back to the default state (R70=0R, R69=Open). Note: It is recommended to prepare the board with the option to easily populate or remove R70 and R69 when the LPCD example is running. E.g., with the help of jumpers/pin headers as shown below.   Only then will the correct VDDIO be measured on PN7642 EVK.  See the VDDIO current measurement below:    In this case, the VDDIO current is approximately 5,48 μA.  Then the overall current comsumption in LPCD is I_VBAT + I_VDDIO= (123 + 91,8 + 32,8 + 5,48) = 253,08 μA Note: For this measurement, the NFC Cockpit is not suitable because the IC does not go into standby mode between LPCD RF pings. Meaning LPCD works normally, but a user can measure higher current consumption. Used Ampere meter -> Power Profiler Kit II Measurement has been performed with FW 2.6  Board supply (jumpers J1, J2 and J4) -> 3.3V Please note that this measurement is indication only! 

LPCD (Low Power Card Detection) works on the principle that the I and Q values are extracted from the RF signal captured on the RX pins. These values are then compared with the I and Q data obtained using LPCD calibration. If the difference is greater than the chosen I and Q threshold, the load is detected and the IC wakes up.  1// LPCD Way of working  Run LPCD Calibration  It is recommended to use an external power supply to supply the EVK board. If the USB supply is used, the value can fluctuate because of the transition effects.  Run "Single LPCD" and check the performance  Adjust the I and Q thresholds  Low value -> Better detection range, more false wake-ups  High value -> Worse detection range, fewer false wake-ups  The number of samples, RSSI, and VDDPA parameters typically remain at their default values.  2// Auto LPCD  When the "Auto LPCD" is used, the LPCD algorithm always performs LPCD Calibration before entering the LPCD. 3//Semi-autonomous LPCD mode (PN5190 only)   The user can evaluate the I and Q values behaviour under loaded/unloaded conditions. Based on that, the LPCD threshold can be properly selected.  Use the same "Register" RSSI Target and Hysteresis as for "EEPROM" Calibrate LPCD Run "Endless I/Q read"  Check how the I and Q values change With no card/object in the antenna proximity  with a NFC card/object in the antenna proximity

This document show the detail steps of following the Personalization example in AN12196. Tool : Pegoda3 and RFIDDiscover.    

RF power regulation is a critical factor in the development of NFC devices, as it directly influences performance, reliability, and compliance with industry standards. There are three main reasons for this:  If the PN7642 VUP current exceeds the limit given by the product Data sheet, the PN7642 can be damaged. If too high RF power is radiated from the antenna, there exists a risk for NFC Cards. Too high RF power might lead to exceeding a given RF limit (NFC Forum, ISO, EMVCo). NXP provides comprehensive documentation on Dynamic Power Control for the PN7642 and PN5190. Designers are expected to adhere to these guidelines, especially when aiming for compliance with standards such as EMVCo. PN5190 Dynamic Power Control Quick Calibration and TxShaping Demo Automatic DPC Calibration for PN7642 and PN5190 However, if the user's design is intended for infrastructure applications, such as a smart lock. At a minimum, Dynamic Power Control (DPC) should be enabled to serve as a current limiter. The evaluation can be done with the help of NFC Cockpit.  1// Start DPC Calibration  "Press" Start DPC Calibration  "Press" Load protocol  Make sure that the DPC is "Enabled" 2// Adjust current reduction table  Set all entries to "0" Write into EEPROM   3// Set the "Target" current Use approx. the same current as "TxLDO Vales"  Save to EEPROM   4// Check the power regulation  Start DPC Calibration  Place a card or any metal object in the antenna's proximity  Observe VDDPA and "TxLDO" current  The current should stay around the given target  The VDDPA will drop once the antenna is loaded  5// Set a minimum VDDPA in DPC  In the case that the current is still too high, a user can define a minimum VDDPA that is used for the DPC regulation. By default, this value is set to 2.2V. The user can decrease it up to 1.5V.  In that case, NXP also recommends disabling the RDOn control.  Note: The User has to consider the "DPC_TXLDO_MAX_DROPOUT" parameter, which defines the maximum voltage drop on TXLDO. By default, it is set to 3.6 V. That means if the user wants to use the minimum VDDPA 1.5 V, then the maximum TXLDO input shall not exceed 5.1 V. This feature protects the TXLDO from overheating.    Once the evaluation is done, the customer shall program the following EEPROM entries in their application. For more info, see PN7642 Product Data sheet.  DPC_CONFIG (Address: 0x0068) -> example: enabled -> 0x01 DPC_TARGET_CURRENT (Address: 0x0069) -> example: 229 mA -> 0xE5 DPC_TXLDO_MAX_DROPOUT (Addresses: 0x0073 - 0x0074) -> example: 3.6 V -> 0x10,0x0E DPC_TXLDOVDDPALow (Address: 0x006F) -> example: 1.5 V -> 0x00 DPC_HYSTERESIS_LOADING (Address: 0x006B) -> example: 20 mA -> 0x14 DPC_HYSTERESIS_UNLOADING (Address: 0x006E) -> example: 10 mA - 0x0A DPC lookup table entries (Addresses: 0x007D - 0x0125) -> example: for current limitation only -> all 0x00 If a user does not want to use a maximum range of VDDPA during DPC (5.7V), e.g., their system uses a 3.3V supply domain. Then, the maximum VDDPA in DPC can be limited by the following EEPROM settings:  TXLDO_VDDPA_MAX_RDR (Address: 0x0007)-> example: 3.0 V -> 0x0F Note: TXLDO has approx. 0.3V voltage drop. Always set this parameter 0.3V lower. Once this is done, the user has to check the "TxLDO" current and adjust the target current accordingly. In this case, to approximately 150 mA. If you don´t change it, the DPC starts to limit the power around 229 mA, as has been set in a previous step. 

The PN7642 includes a USB interface, which allows USB communication with the PC.  Once the PN7642 USB communication is established, the NFC Cockpit tool can be used for RF debugging.  Note: This also requires flashing the NFC Cockpit application with the help of the mass storage mode or SWD interface.  Basically, the user has to connect a USB cable/Connector to the following PN7642 pins.  USB Signal  PN7642 Pin  5V  USB_VBUS Data - ATX_D Data + ATX_C GND GND   See an example below. This is a very basic connection (for evaluation or debugging only) where the USB cable is directly connected to the PN7642 pads.  This situation may arise during debugging on customer hardware where the USB interface is not yet implemented on the PCB. But a user wants to debug with the help of NFC Cockpit.    Please note that the proper USB interface might require special layout rules, such as impedance, overvoltage protection, etc.. For more info, see the PN7642 EVK reference schematic or USB PCB design guide. 

This might be convenient if the user wants to use NFC Cockpit on their device.  See the photo of PNEV5190BP EVK with the instructions.          1. Place R5 and R7, keep R6 open    2. Place R20, keep R19 open Note: This step depends on the voltage domain used in the external hardware. If R19 is placed -> 1.8V domain, if R20 is placed -> 3.3V domain.    3. Remove VBAT, VBAT_PWR, and VUP jumpers to disconnect the "internal" PN5190 located on the EVK    4. Connect the following SPI lines to external PN5190 (e.g., customer HW) SPI_CLK SPI_MOSI SPI_MISO SPI_CS NFC_IRQ GND Note: It is also necessary to disconnect the external PN5190 from the customer MCU. 5. Connect VEN to the external PN5190  NFC_VEN   Now, the external PN5190 HW should communitate with the MCU located in PNEV5190BP, and the NFC Cockpit can be used. The user should see that the blue LED is on. If the red LED is blinking, there is an issue, and the user should check the connections/supply. 

PN5190-NTAG X DNA High Speed Communication Demo: This article describes important feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO/IEC14443-A between PN5190 and NTAG X DNA Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO14443 communication (up to 848 kbps) between a PN5190 reader IC and an NTAG X DNA when connected to MCXA153 host MCU, when simulating the transmission of a dummy file as big as 101 kbytes. ▪ Through MCUXpresso console, the user can configure the contactless bit rate: 106 kbps 212 kbps 424 kbps or 848 kbps The amount of data is fixed in this demo. ▪ transmission mode is implemented from NFC reader library at K82 MCU built in the PNEV5190BP evaluation kit. On the other side, NTAG X DNA + Level shifter (represented by evaluation kit NTAG-X-DNA-EVAL) is connected to a Freedom Board, equipped with MCXA153 - FRDM-MCXA153). ▪ The PN5190 prints on the MCUXpresso console (debug mode) the outcome of the transaction and average baud rate achieved. ▪ In order to handle full file transmission from K82 to MCXA153 (MCU <-> MCU communication), we are using NTAG X DNA GPIO wires as well as proper settings on the NTAG X DNA <-> MCXA153 side and hard coded timeout on the PN5190 + MCU side. For more details, please open attached file PN5190_NTAGXDNA_MCXA153_DualInterface_HBR_Demo_SetupInstructions_Q32025.pdf. Required hardware and software enablement: Hardware ▪ PNEV5190BP Development Board ▪ FRDM-MCXA153 Development Board ▪ NTAG X DNA Development Board ▪ 2 x USB micro cables (for PNEV5190BP dev. br., one for DC power, other for Jlink debug on MCUxpresso IDE) ▪ 1 x USB-C cable (for FRDM-MCXA153 dev. br., only for DC power) Software ▪ MCUxpresso project (firmware Source Code) for PNEV5190BP is attached to this article, containing keywork pn5190: pn5190-ntagxdna-highspeed-demo1.zip. Instructions will be given in from future release of NFC Reader Library public v07.14.00 (NxpNfcRdLib_PN5190_v07.14.00_Pub.zip). ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for FRDM-MCXA153 is attached to this article, containing keyword MCXA153: MCXA153.zip ▪ MCUXpresso IDE recent version, for instance v24.12.148 or above. Demonstrator bring up: Hardware assembly for FRDM-MCXA153: • Connect NTAG X DNA to level shifter (see Fig. 1) • Connect bundle NTAG X DNA+ level shifter bundle to flat cable (contained in demokit box) to FRDM-MCXA153 according to Fig. 2. • Make sure each wire is connected to proper position in Arduino socket: - black wire IO2 goes to J1-14 - white wire IO1 goes to J1-16 - gray wire SCL goes to J2-20 - violet wire SDA goes to J2-18 - blue wire GND goes to J3-14 - green wire VCC goes to J3-8 • Connect FRDM-MCXA153 via J15 (MCU-Link) to your computer (Debug Link Input), for the first time that you have to flash binary in it. Then after storing binary, you may just connect USB-C cable from a power supply to J6 port (named Ext-debugger). • No additional power source is needed. Hardware assembly for PNEV5190B: • Connect two USB micro cables to PNEV5190B board for power, flashing firmware and UART connection (see Fig. 3): • microUSB on J7 is necessary for DC power. Check that jumper J9 is in the position USB dc supply • microUSB on J20 is the Jlink debug port, and it will be connected to your Windows computer, where MCUxpresso has been installed. • Red LED indicates power is enabled • Green LED debugging/UART status Alternatively, if you have a DC power supply (voltage above 7 V), you may change Jumper J9 to Ext power supply, and avoid using second microUSB cable. Software loading on FRDM-MCXA153: 1. Create a new workspace for MCXA153 MCUxpresso example: 2. Make sure you have installed MCXA153 SDK: - install MCXA153 SDK which can be downloaded from: https://mcuxpresso.nxp.com/  3. Unzip "MCXA153.zip" file in local C: directory, with reasonable path length. 4. Import existing projects from file system, into MCUXpresso IDE: 5. Select proper root directory (keyword is MCXA153): 6. Click "Finish" 7. If you get this warning, simply click "OK": 8. Highlight project, click "build", and check that there are no errors: Finished building target: MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf Performing post-build steps arm-none-eabi-size "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf"; # arm-none-eabi-objcopy -v -O binary "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf" "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin" ; # checksum -p MCXA153 -d "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin";    text        data         bss         dec         hex     filename   23524          20        3684       27228        6a5c      MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf 16:27:26 Build Finished. 0 errors, 0 warnings. (took 5s.787ms) 9. Now, flash the binary into MCXA153 MCU using GUI Flash tool; select suitable  MCUxpresso probe (CMSIS-DAP). Make sure USB-c cable is connected to J15 in Freedom board (MCU-link port for flashing FW). 10. Select binary file *.axf as indicated below: It may happen that your MCXA153 has outdated FW on CMSIS-DAP, but you can continue, it will make no harm; click then Ok to flash. 11. After flashing, reboot your board. Following LEDs should be on: - D15 RGB led should be "white" lit. - D7 should be blinking "red" - D8 and D4 should be "green" lit. D15 will blink "white" only during file transmission. You may disconnect USB-c from J15 (the one used with MCUxpresso for flah and connect it to J8. Then, plug the other cable tip to any USB  5 volt battery charger. Now your Freedom board FRDM-MCXA153 is ready to receive data from PNEV5190 board, once project will be imported too in MCUxpresso. Software loading on PNEV5190BP: 1. Unzip *.zip file in directory with reasonable path length. 2. Import existing projects from file system 3. Select Example 12 "NfcrdlibEx12_NTAGXDNA" 4. Uncheck the choice "copy projects into workspace" 5. Install SDK_2.x_FRDM-K82F if not yet done. Such SDK is included in project file tree: • ...Examples\Platform\SDK_2.x_FRDM-K82F • This specific SDK can be obtained from https://mcuxpresso.nxp.com/ by selecting following K82F tab related "PN5180" : • FRDM-K82F-PN5180 (MK82FN256xxx15) • SDK 2.0 is no longer officially available, but SDK 2.2 and newer are backward compatible and recommended by NXP • Build project and check that there are no errors ("warnings" are allowed). • Start Debug session to see available bitrate options on the console. Hardware combination of PNEV5190B and NTAG X DNA connected to FRDM-MCXA153: Under MCUXpresso: 1. Click "Debug" icon on quick access left panel. Accept agreement in case of J-Link tool: 2. Click on icon "Run" on top side of MCUxpresso, and observe the following on "Console" tab: [MCUXpresso Semihosting Telnet console for 'NfcrdlibEx12_NTAGXDNA_mcux JLink DebugFRDMK82F' started on port 59973 @ 127.0.0.1] SEGGER J-Link GDB Server V8.12a - Terminal output channel *** NTAG X DNA Example *** Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : Menu options when two boards have NFC antennas facing each other: There are 5 options in console menu as soon as you "Run" the debug. 1 - options from 1 until and including 3 are related to crypto functionality (symmetric and asymmetric) and are out of the scope of this article. 2 - Then option 5 is used for the first time that you are configuring your NTAG X DNA product. It will set registers and GPIO properly for High bit rate transfer. Once you have run option 5, then go to option 4: 3 - Four options of bitrate are available for transfer a fixed amount of data from host (K82) to NTAG X DNA MCU (MCXA153) using PN5190 as tunnel: Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : Demonstration flow: Once one of these option is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking RGB LED D15 indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: 1 - 106 Kbps - Baud rate 7.6 kBytes/s - elapsed time: 13.99 s Type A Tag is discovered. ***** Perform Transfer sequence ******* Select Application Successful Select File Successful Data transferring NFC -> NTAG X DNA -> Microcontroller... Amount of data exchanged 101200 Bytes, Baudrate (total) = 7.6 kB/s, Time = 13.99 s Please Remove the Card   After removing the card, K82 firmware starts again prompting for a new selection, in the previous menu. First select 4 again and then chose again another new baud rate: 2 - 212 Kbps - Baud rate 10.51 kBytes/s - elapsed time: 9.39 s 3 - 424 Kbps - Baud rate 13.92 kBytes/s - elapsed time: 7.90 s 4 - 848 Kbps - Baud rate 16.60 kBytes/s - elapse time: 5.95 s   Using Example 12 of NFC Reader Library v.07.14.00 to prepare High Speed demo on PNEV5190BP and NTAG X DNA: 1. Go to https://nxp.com web site and type "NFC Reader Library" in Search tab. Follow the instructions until you get to this screenshot: 2. Start by downloading NFC Reader library V.07.14.00 from NXP website; agree with Terms and Conditions. Then download the bundle to your local C: drive: 3. Click on “down arrow” to download version 07.14.00. Once zip file is received, unzip previous bundle to a local drive directory.   4. Start a new workspace, then choose "Import from Existing Projects into Workspace": 5. De-select all useless Examples and keep only example 12; please including all other essential items; click "Finish": 6. If you find this error, it means you need to install K82F SDK: 7. Click install, then MCUxpresso SDKs pages will open. Select K82F from Processor tab: Click “Install” button; after installation is completed, you will get a screen showing all installed sdk's. Afterwards you may get the prompt "Make SDK persistent"; just click ok. 8. Highlight project NfcrdlibEx12_NTAGXDNA_mcux and click build; check if there are errors: Finished building target: NfcrdlibEx12_NTAGXDNA_mcux.axf Performing post-build steps arm-none-eabi-size "NfcrdlibEx12_NTAGXDNA_mcux.axf" ; arm-none-eabi-objcopy -O binary "NfcrdlibEx12_NTAGXDNA_mcux.axf" "NfcrdlibEx12_NTAGXDNA_mcux.bin" ; #checksum -p MK82FN256xxx15 -d "NfcrdlibEx12_NTAGXDNA_mcux.bin"    text        data         bss         dec         hex     filename  222400          92       86816     309308       4b83c      NfcrdlibEx12_NTAGXDNA_mcux.axf 17:32:59 Build Finished. 0 errors, 3 warnings. (took 33s.718ms) 9. Now, check in MCUxpresso the tab Windows > Preferences > Run/Debug. Untick the box related to General Options Build (if required) before launching; it will save you much time! Then, click button “Apply and Close”. 10. Using this Example 12 as it is given by NXP in this library, when you will debug it, you will realize that there are only 3 Menu options related to NTAG X DNA cryptography (and no high speed options). In order to “unlock” the high-speed demo option, please do the following. 11. Go to Quick Settings → Defined Symbols and open it in a new window: Now add after last symbol, the following line: "PH_EX12_ENABLE_DUALINTERFACE_HBR", by clicking on “add button” ("+" shown in green) on top right side of above window; add it manually then click OK two times. Now, build Ex12 again and check that there are no errors. 12. Debug Example 12, then press Run button and check if Console has 5 options in its Menu: Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator     with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder     with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 13. Let's focus on the last two options: 4 – perform HBR (high bit rate) transfer, and 5 – Configure your NTAG X DNA for HBR. 14. If this is the first time you are using this NTAG X DNA connected to MCXA153, then choose option 5 so that PN5190 will write proper configuration data to NTAG X DNA next to it. For this reason, turn on NTAG X DNA connected to FRDM-MCXA153 board (after powering it up with a simple 5V-USB source), and place NTAG X DNA antenna over PNEV5190BP board antenna (connected to MCUxpresso), as in picture shown above. Enter your option : 5 Ready to detect Type A Tag is discovered.       Select NDEF Application Successful       Authenticate Application Successful       SetConfig Successful       StdDataFile with File ID 0xE106 already exists. Please Remove the Card 15. Remove NTAG X DNA antenna from PN5190 antenna, until you get back to initial menu. Then, choose option 4 on previous menu: 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 4  Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : 16. Now, choose the lowest speed "1"; check final result: Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 5.72 kB/s, Time = 17.25 s Please Remove the Card 17. Separate both antennas, and then, choose option "2"; check final result: Enter your option : 2 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller… Amount of data exchanged 101200 Bytes, Baudrate (total) = 10.49 kB/s, Time = 9.41 s 18. Separate both antennas, and then, choose option "3"; check final result: Enter your option : 3 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 13.89 kB/s, Time = 7.11 s Please Remove the Card 19. Separate both antennas, and then, choose option "4"; check final result:  Enter your option : 4 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 16.57 kB/s, Time = 5.96 s Please Remove the Card Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG X DNA (NFC connected tag), making use of available commands described in its product support package (https://www.nxp.com/products/NTAG-X-DNA). Disclaimer:All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not yet official part of PN5190/NTAG X DNA standard product support packages currently available at nxp.com.