Autosar Os 示例 你好 我正在开发一个使用 S32K146 芯片和 Autosar 架构的 ECU 项目。我以前没有接触过 Os 模块的使用，如果您能提供一些与 Os 模块相关的例程，我将不胜感激。 谢谢！ Re: Autosar Os Example 能给我一个链接吗？ Re: Autosar Os Example 你好 AUTOSAR 操作系统软件包中有一个例子： Untitled.png 您可以在恩智浦 SW 账户中找到它：   Untitled.png S32K_AUTOSAR_OS_4_0_98_RTM_1_0_0.exe_ 它非常直观，你可以通过用户手册 AUTOSAR_OSS32K_UM.pdf 进行配置，它是软件包的一部分。 顺祝商祺！ Peter     Re: Autosar Os Example 我正在开发一个使用 S32K146 芯片的 Autosar 项目，配置工具是 EB Tresos。我配置了CAN堆栈并在环回模式下测试了上层的传输和接收过程（从Com层到MCAL），一切正常。 当我将 CAN 控制器配置为正常模式时，CAN 数据被写入寄存器（RAMn），但硬件并未启动传输。Tx 引脚上没有数据，因此，没有触发信号来清除 TX Buff 标志。这也导致前四帧数据成功写入 Buff，但从第五帧开始，数据无法写入，并返回 CAN BUSY 状态。 由于这个问题，我不知道如何解决。因此，我使用了 S32DS 中为 S32K146 提供的 Autosar CAN 示例，做了一些修改，并在相同的硬件上运行。然而，数据仍然无法传输，同样的问题再次出现。 您能帮我分析一下 CAN 传输在我的项目中出现故障的原因吗？谢谢。

SAF - ASIL 认证 您好，技术支持、 客户正在使用带有 SW32K3_SAF_1.0.5_D2503 的 S32K31。 他们要求我们提供 SAF ASIL 证书或任何文件，以证明其符合 ASIL"ready/compliance" 。 此致， 马库斯 SAFETY_SW Re: SAF - ASIL Certification 您好，技术支持、 有更新吗？ Re: SAF - ASIL Certification 你好 Marcus， 对于每个高级 SAF 软件包，都可以下载功能安全软件评估摘要报告。 适用于 SAF 1.0.5我也可以在 Flexera 上看到： S32K3_SAF_1.0.5_Safety_SW_Assessment_Summary.pdf 亲切的问候， Radoslav Re: SAF - ASIL Certification 你好@marcuslim, 目前，与客户共享文件在技术上和法律上都受到限制，我认为唯一合法的途径是通过销售人员。 总之，我想从 nxp.com 上的 SAF 产品页面截图，和我分享的一样，看看到底缺了什么。 客户如何获得版本？ 应该有功能安全评估，其他人都可以看到。 我在这里附上内部报告，让您找到如何合法地与客户共享文件的方法。 但请尽量向客户解释正确的获取方式 nxp.com=>Softwareaccounts= > 汽车软件-S32K3 高级软件= > 汽车软件-S32K3-功能安全软件框架 亲切的问候，拉多斯拉夫 Re: SAF - ASIL Certification 谢谢你，拉多斯拉夫！ 客户已找到文件。 我们可以关闭这个主题了。 此致， 马库斯

ADC DMA 示例不起作用 您好， 我正在使用 MBDT v1.5 在 S32K3X8EVB-Q289 上开发一个项目 我正在尝试使用 DMA 实现 ADC，经过一番努力后，我在网上找到了这张票： https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/DMA-enabling-in-MBDT/m-p/1819674 在此基础上，我尝试执行@Irina_Costachescu给出的所有指示。 当我尝试版本时出现问题... matlab 给我这个错误： simon98_0-1750087663761.png 我不知道如何解决这个问题......谁能告诉我如何解决这个问题，或者我是否遗漏了什么？ 谢谢！ 西蒙 Re: ADC DMA Example doesn't work 你好，@simon98、 最新的恩智浦 S32K3 基于模型的设计工具箱 1.8.0 版 包含一个使用 ADC 和 DMA 的更新模型示例：adc文件夹中的s32k344_pwm_adc_dma_s32ct 。 您可以将此模型用作应用程序的参考。 希望这能帮到您， 德拉古 Re: ADC DMA Example doesn't work 我从提供的示例中导入了配置，但还是遇到了这个问题： https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/ADC-DMA-Example-doesn-t-work-with-my-S32CT-Configuration/m-p/2124851#M10317 Re: ADC DMA Example doesn't work 嗨，@dragostoma、 我现在才能测试 MBDT 1.8 版本中带有 DMA 的 ADC 示例。 起初，我遇到了同样的问题：回调已执行，但在 FreeMASTER 中却看不到变量ADC_POT0的值在更新（与 1.6 版中的情况相同）。 经过多次尝试，我试着添加了以下 MCL 块，以检查 DMA 是否真正正常工作： 2.png 为了进一步调查，我用S32DS 3.6 打开了该项目。在调试时，我可以看到ADC_POT0根据电位器的位置发生变化，即使 Simulink 中的 MCL 块被注释掉也是如此。但是，在 FreeMASTER 中，ADC_POT0不会更新。 因此，我想知道造成这种行为的原因是什么，以及是否有可能以某种方式修复 FreeMASTER 的行为。 附件中是我用于这些测试的项目。 我期待您的反馈。 谢谢， Simon

i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) We designed a custom board based with MIMX8ML8XXXKZ SoC MT53E768M64D4DE-046 WT:C LPDDR4 BD71847 PMIC All SoC and DRAM power lanes seem to be powered properly Based on previous experience with i.MX8MM we attempted to generate timings for the DRAM using the DDR Mtool, but the result we got  Spoiler (Highlight to read) Download is complete Waiting for the target board boot... ===================hardware_init===================== hardware_init exit ************************************************************************* ************************************************************************* ************************************************************************* MX8 DDR Stress Test V3.30 Built on Nov 24 2021 13:52:12 ************************************************************************* Waiting for board configuration from PC-end... --Set up the MMU and enable I and D cache-- - This is the Cortex-A53 core - Check if I cache is enabled - Enabling I cache since it was disabled - Push base address of TTB to TTBR0_EL3 - Config TCR_EL3 - Config MAIR_EL3 - Enable MMU - Data Cache has been enabled - Check system memory register, only for debug - VMCR Check: - ttbr0_el3: 0x97d000 - tcr_el3: 0x2051c - mair_el3: 0x774400 - sctlr_el3: 0xc01815 - id_aa64mmfr0_el1: 0x1122 - MMU and cache setup complete ************************************************************************* ARM clock(CA53) rate: 1800MHz DDR Clock: 2000MHz ============================================ DDR configuration DDR type is LPDDR4 Data width: 32, bank num: 8 Row size: 17, col size: 10 One chip select is used Number of DDR controllers used on the SoC: 1 Density per chip select: 3072MB Density per controller is: 3072MB Total density detected on the board is: 3072MB ============================================ MX8M-plus: Cortex-A53 is found ************************************************************************* ============ Step 1: DDRPHY Training... ============ ---DDR 1D-Training @2000Mhz... PMU: Error: CA Training Failed. PMU: ***** Assertion Error - terminating ***** [Result] FAILED Download is completeWaiting for the target board boot...===================hardware_init=====================hardware_init exit***************************************************************************************************************************************************************************************************************************MX8 DDR Stress Test V3.30Built on Nov 24 2021 13:52:12*************************************************************************Waiting for board configuration from PC-end...--Set up the MMU and enable I and D cache--- This is the Cortex-A53 core- Check if I cache is enabled- Enabling I cache since it was disabled- Push base address of TTB to TTBR0_EL3- Config TCR_EL3- Config MAIR_EL3- Enable MMU- Data Cache has been enabled- Check system memory register, only for debug- VMCR Check:- ttbr0_el3: 0x97d000- tcr_el3: 0x2051c- mair_el3: 0x774400- sctlr_el3: 0xc01815- id_aa64mmfr0_el1: 0x1122- MMU and cache setup complete*************************************************************************ARM clock(CA53) rate: 1800MHzDDR Clock: 2000MHz============================================DDR configurationDDR type is LPDDR4Data width: 32, bank num: 8Row size: 17, col size: 10One chip select is usedNumber of DDR controllers used on the SoC: 1Density per chip select: 3072MBDensity per controller is: 3072MBTotal density detected on the board is: 3072MB============================================MX8M-plus: Cortex-A53 is found*************************************************************************============ Step 1: DDRPHY Training... ============---DDR 1D-Training @2000Mhz...PMU: Error: CA Training Failed.PMU: ***** Assertion Error - terminating *****[Result] FAILED A similar situation was with the Config tool. We tried to use the .ds script both generated by Config tool, as well as the RPA, neither worked Based on the discussion on the forum we attempted to disable the CA training. And calibration for single frequency setpoint started working Spoiler (Highlight to read) Download is complete Waiting for the target board boot... ===================hardware_init===================== hardware_init exit ************************************************************************* ************************************************************************* ************************************************************************* MX8 DDR Stress Test V3.30 Built on Nov 24 2021 13:52:12 ************************************************************************* Waiting for board configuration from PC-end... --Set up the MMU and enable I and D cache-- - This is the Cortex-A53 core - Check if I cache is enabled - Enabling I cache since it was disabled - Push base address of TTB to TTBR0_EL3 - Config TCR_EL3 - Config MAIR_EL3 - Enable MMU - Data Cache has been enabled - Check system memory register, only for debug - VMCR Check: - ttbr0_el3: 0x97d000 - tcr_el3: 0x2051c - mair_el3: 0x774400 - sctlr_el3: 0xc01815 - id_aa64mmfr0_el1: 0x1122 - MMU and cache setup complete ************************************************************************* ARM clock(CA53) rate: 1800MHz DDR Clock: 2000MHz ============================================ DDR configuration DDR type is LPDDR4 Data width: 32, bank num: 8 Row size: 17, col size: 10 Two chip selects are used Number of DDR controllers used on the SoC: 1 Density per chip select: 3072MB Density per controller is: 6144MB Total density detected on the board is: 6144MB ============================================ MX8M-plus: Cortex-A53 is found ************************************************************************* ============ Step 1: DDRPHY Training... ============ ---DDR 1D-Training @2000Mhz... [Process] End of initialization [Process] End of read enable training [Process] End of fine write leveling [Process] End of read DQ deskew training [Process] End of MPR read delay center optimization [Process] End of Write Leveling coarse delay [Process] End of write delay center optimization [Process] End of read delay center optimization [Process] End of max read latency training [Result] PASS ---DDR 2D-Training @2000Mhz... [Process] End of initialization [Process] End of 2D write delay/voltage center optimization [Process] End of 2D write delay/voltage center optimization [Process] End of 2D read delay/voltage center optimization [Process] End of 2D read delay/voltage center optimization [Result] PASS ============ Step 2: DDR memory accessing... ============ Verifying DDR frequency [email protected] [Result] OK ============ Step 3: DDR parameters processing... ============ [Result] Done Success: DDR Calibration completed!!! Download is completeWaiting for the target board boot...===================hardware_init=====================hardware_init exit***************************************************************************************************************************************************************************************************************************MX8 DDR Stress Test V3.30Built on Nov 24 2021 13:52:12*************************************************************************Waiting for board configuration from PC-end...--Set up the MMU and enable I and D cache--- This is the Cortex-A53 core- Check if I cache is enabled- Enabling I cache since it was disabled- Push base address of TTB to TTBR0_EL3- Config TCR_EL3- Config MAIR_EL3- Enable MMU- Data Cache has been enabled- Check system memory register, only for debug- VMCR Check:- ttbr0_el3: 0x97d000- tcr_el3: 0x2051c- mair_el3: 0x774400- sctlr_el3: 0xc01815- id_aa64mmfr0_el1: 0x1122- MMU and cache setup complete*************************************************************************ARM clock(CA53) rate: 1800MHzDDR Clock: 2000MHz============================================DDR configurationDDR type is LPDDR4Data width: 32, bank num: 8Row size: 17, col size: 10Two chip selects are usedNumber of DDR controllers used on the SoC: 1Density per chip select: 3072MBDensity per controller is: 6144MBTotal density detected on the board is: 6144MB============================================MX8M-plus: Cortex-A53 is found*************************************************************************============ Step 1: DDRPHY Training... ============---DDR 1D-Training @2000Mhz...[Process] End of initialization[Process] End of read enable training[Process] End of fine write leveling[Process] End of read DQ deskew training[Process] End of MPR read delay center optimization[Process] End of Write Leveling coarse delay[Process] End of write delay center optimization[Process] End of read delay center optimization[Process] End of max read latency training[Result] PASS---DDR 2D-Training @2000Mhz...[Process] End of initialization[Process] End of 2D write delay/voltage center optimization[Process] End of 2D write delay/voltage center optimization[Process] End of 2D read delay/voltage center optimization[Process] End of 2D read delay/voltage center optimization[Result] PASS============ Step 2: DDR memory accessing... ============Verifying DDR frequency [email protected][Result] OK============ Step 3: DDR parameters processing... ============[Result] DoneSuccess: DDR Calibration completed!!! If multiple frequency setpoints are set, the optimization keeps failing at the second setpoint And the stress test started passing correctly both in the Mtool and in the Config tool. However, the Diag read margin, diag write margin and CA eye tests keep failing One thing to note is that comparing to the IMX8MP-EVK we connected the CA and CB to their respective pins on the CPU (in the EVK they were reversed) Here are the respective lanes lengths and the delay deltas Spoiler (Highlight to read) 1. CAx_B, CKE_A, CK_CS_A - 20mm, <1ps 2. CAx_B, CKE_B, CK_CS_B - 19mm, <1ps 3. DQ07_A - 15mm, <1ps 4. DQ07_B - 14.5mm, <1ps 5. DQ815_A -10mm, <1ps 6. DQ815_B -10mm, <1ps 7. CKA - 21mm, DQS0 - 15mm (-22ps to CKA), DQS1 - 13mm (-55ps to CKA) 8. CKB - 21mm, DQS2 - 14mm (-24ps to CKA), DQS3 - 13mm (-54ps to CKA) 1. CAx_B, CKE_A, CK_CS_A - 20mm, <1ps2. CAx_B, CKE_B, CK_CS_B - 19mm, <1ps3. DQ07_A - 15mm, <1ps4. DQ07_B - 14.5mm, <1ps5. DQ815_A -10mm, <1ps6. DQ815_B -10mm, <1ps7. CKA - 21mm, DQS0 - 15mm (-22ps to CKA), DQS1 - 13mm (-55ps to CKA)8. CKB - 21mm, DQS2 - 14mm (-24ps to CKA), DQS3 - 13mm (-54ps to CKA) Can the CA/CB swap be the reason of the problem? 回复： i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) @AlexandrP , @sfatyushkin ,@JorgeCas ,Hi, We designed a custom board based with MIMX8ML4xxxKZ, However, when testing the DDR, even the initial phy init failed, and the error message was as follows: ```txt test-prefix : "C:/nxp/i.MX_CFG_25.12/bin/python3/python" "C:/nxp/i.MX_CFG_25.12/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.12/processors/MIMX8ML4xxxKZ/ksdk2_0/mem_validation/ddrc" -a "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test_app_phy_test_0_0_.log" -p "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy_training_phy_test_0_0_.log" -l INFO "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/HEJIAN~1.LIG/AppData/Local/Temp/mem_validation/ddrc_config_in.json INFO memtool.processor.imx8m.imx8_processor Xls mapping load time 0.011705 INFO memtool.processor.base_processor Config time 0.008170 INFO memtool.processor.base_processor DS file time 0.256190 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 INFO memtool.comm.serial_channel Using serial: COM23 WARNING memtool.comm.serial_channel Timeout waiting for response "[TARGET IS ALIVE]" ERROR memtool.common.base_test Application is not waiting for input state. WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" WARNING memtool.comm.serial_channel Timeout waiting for response "[READ FINISHED]" ERROR memtool.comm.serial_channel Read symbol failed after 3 tries {'app_state': -1, 'num_records': -1, 'records': [], 'debug': -1, 'err_capt_regs': -1, 'debug_regs': -1} ****DONE**** ``` Since this is my first time using IMX8, could you give me some advice? Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, According to constraint manager, the routing is under the recommended values: Screenshot 2025-06-20 124653.png Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) sfatyushkin_0-1750392487472.png 127 + 50 ps < 191ps Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, 1) A clock frequency reduction, but it is not a warranty that will work.  2) It is under the recommendation, ±50 ps. Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Jorge, thanks a lot! This helped us to understand the problem. When laying out the LpDDR lines, we used the same rules as before when laying out iMX8MM, without paying attention to the tightening of the requirements for the CAx lines (within 2 ps in groups), and did not take into account the Pkg delay. So, two questions. 1. Is it possible to configure the CA_x_y lines and run the board with a spread of CA lines times of about 20 ps (possibly at a slow speed), or it is impossible to do without redesigning the board? 2. In the i.MX 8M Plus Hardware Developer’s Guide, all timings seems like in EVK. But the delay on the CK_A lines is indicated to be about 107 ps (145 ps taking into account the Pkg delay). On the EVK board (directly in the project that you provided), I see a delay on the CKa lines of about 89 ps (127 ps taking into account the Pkg delay, and this is outside the 50 ps tolerance for the CA_A_0...4 lines). What is correct? Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, The issue you are mentioning could be caused by marginal signal integrity or timing violations. Please take a look in attached file for .alg file. Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Based on your response we decided to tackle the ODT parameters once again. We redid the Read/Write ODT and driver matrix in Optimization tab and noticed that some random ODT combinations drop 'Target a connection or exception in the script'. Saying random, I mean that from run to run they are different and don't occur every time. Otherwise, the rest of the combinations succeed, even up to 240 Ohm We also evaluated the "Diag Read/Write Margin tests results more closely. Before, only the fact that test showed "checkmark 100%" was viewed , and noticed that whenever test "passes" it demonstrates not all of the DQ lanes, and the number is different every time. See attached pictures (for some reason the forum doesn't let me attach pictures neither in text, nor as attachments, so adding link to drive folder https://drive.google.com/drive/folders/1U4-G1_Em-73UR1zrtUFAsVCRBpAlchGN?usp=sharing) Trying to investigate this, we observed the 1V1 power lane with the oscilloscope, didn't notice anything extra suspicious, but during that the "Diag Margin" test started to show the Eye diagrams for all of the DQ lanes in more or less okay shape, so we added 9.5pF capacitor (see the attachment with "cond" for reference), and the Margin Test results in all DQ lanes diagrams every time it shows anything CA Bus Signals Margin test as well shows "Checkmark 100%", but in the "Charts" tab it states "Collecting diagnostic data..." and in logs it shows error "CA data is missing!" See full log in spoiler Spoiler (Highlight to read) #################### Result for: ca_bus ###### Run 1 ############################################### Microsoft Windows [Version 10.0.19045.2965] (c) Microsoft Corporation. All rights reserved. C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix : test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_bus_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_bus_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.processor.base_processor freq_0 set to 667 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list INFO memtool.comm.serial_channel Using serial: COM3 DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel Channel is not alive DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn='' DEBUG memtool.comm.serial_channel ==================hardware_init======================= DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup... DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz... DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz... DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended... DEBUG memtool.comm.serial_channel ==================hardware_init exit================== DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write app log level DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a INFO memtool.common.base_test Write app state CONFIG_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa DEBUG test_app [DEBUG]: Initialize mailbox... DEBUG test_app [DEBUG]: Apply Init PHY Config... DEBUG test_app [DEBUG]: Execute PHY operation... DEBUG test_app [DEBUG]: Run PHY full init... DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000... DEBUG test_app [DEBUG]: End of load 1D imem image... DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0... DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e... DEBUG test_app [DEBUG]: End of load 1D dmem image... DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz... DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.912us... DEBUG test_app [DEBUG]: PHY operation ended with status 0... DEBUG memtool.comm.serial_channel Executing: mw92F918,1 DEBUG memtool.comm.serial_channel Result: 0x00000000 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Read phy status DEBUG memtool.comm.serial_channel Executing: mw92F91C,1 DEBUG memtool.comm.serial_channel Result: 0x00000059 INFO root Number of logged items 0x59 DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings DEBUG memtool.comm.serial_channel Executing: mb961000,400 DEBUG memtool.comm.serial_channel Executing: mb961400,400 DEBUG memtool.comm.serial_channel Executing: mb961800,400 DEBUG memtool.comm.serial_channel Executing: mb961C00,400 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write input param test = 200 DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8 INFO memtool.common.base_test Write app state INPUT_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544 DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe DEBUG memtool.comm.serial_channel Executing: mw92EABC,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol num_records = 0x1 INFO memtool.common.base_test App state WAIT_FOR_INPUT DEBUG memtool.comm.serial_channel Executing: mw92EF40,8 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF60,A DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF88,20 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol state = 1 DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1 DEBUG memtool.comm.serial_channel Result: 0x000000C8 INFO memtool.common.base_test Read symbol test_id = 200 INFO memtool.common.base_test Record 0 state TestStatus.PASS DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Test 200 finished with state 1 DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}] DEBUG memtool.common.base_test Number of records: 1 ERROR memtool.memtests.phy_diags_tests CA data is missing! {'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'} ****DONE**** #################### Result for: ca_bus ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965](c) Microsoft Corporation. All rights reserved.C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_bus_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_bus_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.jsonDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.processor.base_processor freq_0 set to 667INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dllDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listINFO memtool.comm.serial_channel Using serial: COM3DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channel Channel is not aliveDEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''DEBUG memtool.comm.serial_channel ==================hardware_init=======================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...DEBUG memtool.comm.serial_channel ==================hardware_init exit==================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write app log levelDEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000aINFO memtool.common.base_test Write app state CONFIG_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aaDEBUG test_app [DEBUG]: Initialize mailbox...DEBUG test_app [DEBUG]: Apply Init PHY Config...DEBUG test_app [DEBUG]: Execute PHY operation...DEBUG test_app [DEBUG]: Run PHY full init...DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...DEBUG test_app [DEBUG]: End of load 1D imem image...DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...DEBUG test_app [DEBUG]: End of load 1D dmem image...DEBUG test_app [INFO]: Execute Training Firmware for 1D [email protected] test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.912us...DEBUG test_app [DEBUG]: PHY operation ended with status 0...DEBUG memtool.comm.serial_channel Executing: mw92F918,1DEBUG memtool.comm.serial_channel Result: 0x00000000DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Read phy statusDEBUG memtool.comm.serial_channel Executing: mw92F91C,1DEBUG memtool.comm.serial_channel Result: 0x00000059INFO root Number of logged items 0x59DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.stringsDEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.stringsDEBUG memtool.comm.serial_channel Executing: mb961000,400DEBUG memtool.comm.serial_channel Executing: mb961400,400DEBUG memtool.comm.serial_channel Executing: mb961800,400DEBUG memtool.comm.serial_channel Executing: mb961C00,400DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write input param test = 200DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8INFO memtool.common.base_test Write app state INPUT_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read symbol app_state = 0x5588dcfeDEBUG memtool.comm.serial_channel Executing: mw92EABC,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol num_records = 0x1INFO memtool.common.base_test App state WAIT_FOR_INPUTDEBUG memtool.comm.serial_channel Executing: mw92EF40,8DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF60,ADEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF88,20DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol state = 1DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1DEBUG memtool.comm.serial_channel Result: 0x000000C8INFO memtool.common.base_test Read symbol test_id = 200INFO memtool.common.base_test Record 0 state TestStatus.PASSDEBUG memtool.comm.serial_channel Executing: mw92EAC8,10DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Test 200 finished with state 1DEBUG memtool.common.base_test App state: WAIT_FOR_INPUTDEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]DEBUG memtool.common.base_test Number of records: 1ERROR memtool.memtests.phy_diags_tests CA data is missing!{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}****DONE**** "CA Eye" always runs into timeout, I tried different values for "ATXImpedance" and with value of 20Ohm it's able to run longer for about one cycle, but in the end it still times out. See the full log in the spoiler Spoiler (Highlight to read) #################### Result for: ca_eye ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965] (c) Microsoft Corporation. All rights reserved. C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix : test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_eye_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_eye_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json" INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.processor.base_processor freq_0 set to 667 INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4 DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dll DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list INFO memtool.comm.serial_channel Using serial: COM3 DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive INFO memtool.comm.serial_channel Send reset to target DEBUG memtool.comm.serial_channel Executing: R DEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn='' DEBUG memtool.comm.serial_channel ==================hardware_init======================= DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup... DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz... DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz... DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended... DEBUG memtool.comm.serial_channel ==================hardware_init exit================== DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write app log level DEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000a INFO memtool.common.base_test Write app state CONFIG_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aa DEBUG test_app [DEBUG]: Initialize mailbox... DEBUG test_app [DEBUG]: Apply Init PHY Config... DEBUG test_app [DEBUG]: Execute PHY operation... DEBUG test_app [DEBUG]: Run PHY full init... DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000... DEBUG test_app [DEBUG]: End of load 1D imem image... DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0... DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e... DEBUG test_app [DEBUG]: End of load 1D dmem image... DEBUG test_app [INFO]: Execute Training Firmware for 1D pstate0@667MHz... DEBUG test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.898us... DEBUG test_app [DEBUG]: PHY operation ended with status 0... DEBUG memtool.comm.serial_channel Executing: mw92F918,1 DEBUG memtool.comm.serial_channel Result: 0x00000000 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Read phy status DEBUG memtool.comm.serial_channel Executing: mw92F91C,1 DEBUG memtool.comm.serial_channel Result: 0x00000059 INFO root Number of logged items 0x59 DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.strings DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.strings DEBUG memtool.comm.serial_channel Executing: mb961000,400 DEBUG memtool.comm.serial_channel Executing: mb961400,400 DEBUG memtool.comm.serial_channel Executing: mb961800,400 DEBUG memtool.comm.serial_channel Executing: mb961C00,400 DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read app state WAIT_FOR_INPUT INFO memtool.common.base_test Write input param test = 200 DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8 INFO memtool.common.base_test Write app state INPUT_RECEIVED DEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544 DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1 DEBUG memtool.comm.serial_channel Result: 0x5588DCFE INFO memtool.common.base_test Read symbol app_state = 0x5588dcfe DEBUG memtool.comm.serial_channel Executing: mw92EABC,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol num_records = 0x1 INFO memtool.common.base_test App state WAIT_FOR_INPUT DEBUG memtool.comm.serial_channel Executing: mw92EF40,8 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF60,A DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EF88,20 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1 DEBUG memtool.comm.serial_channel Result: 0x00000001 INFO memtool.common.base_test Read symbol state = 1 DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1 DEBUG memtool.comm.serial_channel Result: 0x000000C8 INFO memtool.common.base_test Read symbol test_id = 200 INFO memtool.common.base_test Record 0 state TestStatus.PASS DEBUG memtool.comm.serial_channel Executing: mw92EAC8,10 DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] INFO memtool.common.base_test Test 200 finished with state 1 DEBUG memtool.common.base_test App state: WAIT_FOR_INPUT DEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}] DEBUG memtool.common.base_test Number of records: 1 DEBUG memtool.processor.base_processor freq_0 set to 667 DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.json DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt DEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txt DEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWER DEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210) DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.c DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.json DEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445) DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465) DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.bin DEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869) DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885) DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.bin DEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txt DEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716) DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782) DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txt DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.json DEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389) DEBUG memtool.phyinit.out_parser Parse retention register list DEBUG memtool.common.factories new instance -> {inst} {'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'} DEBUG memtool.common.factories new instance -> {inst} DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel DEBUG memtool.comm.serial_channel Channel is alive INFO memtool.comm.serial_channel Send reset to target DEBUG memtool.comm.serial_channel Executing: R ERROR libusbsio.hidapi.dev HID device 'b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}'' opening failed. ERROR memtool.common.base_test Application load ended with exception: Download incomplete due to configuration error! DEBUG memtool.comm.serial_channel Executing: mw92F918,1 #################### Result for: ca_eye ###### Run 1 ###############################################Microsoft Windows [Version 10.0.19045.2965](c) Microsoft Corporation. All rights reserved.C:\nxp\i.MX_CFG_25.03\bin>prompt test-prefix :test-prefix : "C:/nxp/i.MX_CFG_25.03/bin/python3/python" "C:/nxp/i.MX_CFG_25.03/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_25.03/processors/MIMX8ML8xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy_training_ca_eye_lpddr4_0_0_.log" -i "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/figure_ca_eye_lpddr4_0_0_.png" -l DEBUG "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.json"INFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/connect.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/test.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/phy.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_registers.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config.jsonINFO memtool.utils.helper *****C:/Users/vboxuser/AppData/Local/Temp/mem_validation/ddrc_config_in.jsonDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.processor.base_processor freq_0 set to 667INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2020.06_lpddr4.dllDEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listINFO memtool.comm.serial_channel Using serial: COM3DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveINFO memtool.comm.serial_channel Send reset to targetDEBUG memtool.comm.serial_channel Executing: RDEBUG spsdk.utils.interfaces.device.usb_device Closing the Interface: SE Blank 865 (0x1FC9, 0x0146)path=b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}' sn=''DEBUG memtool.comm.serial_channel ==================hardware_init=======================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel [DEBUG]: Clock setup...DEBUG memtool.comm.serial_channel [INFO]: ARM core clock rate is 1800MHz...DEBUG memtool.comm.serial_channel [INFO]: DDR Dram frequency is 666MHz...DEBUG memtool.comm.serial_channel [DEBUG]: Clock setup ended...DEBUG memtool.comm.serial_channel ==================hardware_init exit==================DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write app log levelDEBUG memtool.comm.serial_channel Executing: Mw92F510,1:0000000aINFO memtool.common.base_test Write app state CONFIG_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:55aa55aaDEBUG test_app [DEBUG]: Initialize mailbox...DEBUG test_app [DEBUG]: Apply Init PHY Config...DEBUG test_app [DEBUG]: Execute PHY operation...DEBUG test_app [DEBUG]: Run PHY full init...DEBUG test_app [DEBUG]: Write 1D imem image, offset 0x00050000 size 0x00004000...DEBUG test_app [DEBUG]: End of load 1D imem image...DEBUG test_app [DEBUG]: Set DFI Clock for pstate 0...DEBUG test_app [DEBUG]: Write 1D dmem image, offset 0x00054000 size 0x0000033e...DEBUG test_app [DEBUG]: End of load 1D dmem image...DEBUG test_app [INFO]: Execute Training Firmware for 1D [email protected] test_app [INFO]: Training Firmware completed for 1D pstate0@667MHz with status 0; Execution ended in 0s.310ms.898us...DEBUG test_app [DEBUG]: PHY operation ended with status 0...DEBUG memtool.comm.serial_channel Executing: mw92F918,1DEBUG memtool.comm.serial_channel Result: 0x00000000DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Read phy statusDEBUG memtool.comm.serial_channel Executing: mw92F91C,1DEBUG memtool.comm.serial_channel Result: 0x00000059INFO root Number of logged items 0x59DEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4\lpddr4_pmu_train.stringsDEBUG memtool.memtests.snps_phy Using messages file C:\ProgramData\NXP\mcu_data_25.03\processors\MIMX8ML8xxxKZ\ksdk2_0\mem_validation\ddrc\firmware\2020.06\lpddr4_2d\lpddr4_2d_pmu_train.stringsDEBUG memtool.comm.serial_channel Executing: mb961000,400DEBUG memtool.comm.serial_channel Executing: mb961400,400DEBUG memtool.comm.serial_channel Executing: mb961800,400DEBUG memtool.comm.serial_channel Executing: mb961C00,400DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveDEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read app state WAIT_FOR_INPUTINFO memtool.common.base_test Write input param test = 200DEBUG memtool.comm.serial_channel Executing: Mw92EA10,1:000000c8INFO memtool.common.base_test Write app state INPUT_RECEIVEDDEBUG memtool.comm.serial_channel Executing: Mw92EAB8,1:77665544DEBUG memtool.comm.serial_channel Executing: mw92EAB8,1DEBUG memtool.comm.serial_channel Result: 0x5588DCFEINFO memtool.common.base_test Read symbol app_state = 0x5588dcfeDEBUG memtool.comm.serial_channel Executing: mw92EABC,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol num_records = 0x1INFO memtool.common.base_test App state WAIT_FOR_INPUTDEBUG memtool.comm.serial_channel Executing: mw92EF40,8DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug = [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF60,ADEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol err_capt_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EF88,20DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read symbol debug_regs = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.comm.serial_channel Executing: mw92EAC0,1DEBUG memtool.comm.serial_channel Result: 0x00000001INFO memtool.common.base_test Read symbol state = 1DEBUG memtool.comm.serial_channel Executing: mw92EAC4,1DEBUG memtool.comm.serial_channel Result: 0x000000C8INFO memtool.common.base_test Read symbol test_id = 200INFO memtool.common.base_test Record 0 state TestStatus.PASSDEBUG memtool.comm.serial_channel Executing: mw92EAC8,10DEBUG memtool.comm.serial_channel Result: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Read test data [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]INFO memtool.common.base_test Test 200 finished with state 1DEBUG memtool.common.base_test App state: WAIT_FOR_INPUTDEBUG memtool.common.base_test Err_caption_registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug: [0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Debug registers: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]DEBUG memtool.common.base_test Results: [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}]DEBUG memtool.common.base_test Number of records: 1DEBUG memtool.processor.base_processor freq_0 set to 667DEBUG memtool.phyinit.phy_init PHY config file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_config_final.jsonDEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.phy_init Retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse phyinit output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txtDEBUG memtool.phyinit.out_parser Parse retention output file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_training_out_1d2d_retention.txtDEBUG memtool.phyinit.out_parser Parse state A_BRING_UP_POWERDEBUG memtool.phyinit.out_parser Parse state C_PHY_INIT_CONFIG(210)DEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x32fb to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.cDEBUG memtool.phyinit.out_parser Write PHY CONFIG as txt size 0x15d4 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\phy_init.jsonDEBUG memtool.phyinit.out_parser Parse state LOAD_IMEM_1(445)DEBUG memtool.phyinit.out_parser Parse state D_LOAD_IMEM_1D(465)DEBUG memtool.phyinit.out_parser Write IMEM 1D as bin size 0x8000 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.binDEBUG memtool.phyinit.out_parser Write IMEM 1D as txt size 0x6eaf3 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\imem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.E_SET_DFI_CLOCK(16850)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1(16869)DEBUG memtool.phyinit.out_parser Parse state PHASE.F_LOAD_DMEM_1D(16885)DEBUG memtool.phyinit.out_parser Write DMEM 1D as bin size 0x67c to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.binDEBUG memtool.phyinit.out_parser Write DMEM 1D as txt size 0x5398 to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\dmem_1d.txtDEBUG memtool.phyinit.out_parser Parse state PHASE.G_EXEC_FW(17716)DEBUG memtool.phyinit.out_parser Parse state PHASE.PHASE.I_LOAD_PIE(17782)DEBUG memtool.phyinit.out_parser Write PIE as txt size 0x44ff to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.txtDEBUG memtool.phyinit.out_parser Write PIE as txt size 0x933a to file C:\Users\vboxuser\AppData\Local\Temp\mem_validation\pie.jsonDEBUG memtool.phyinit.out_parser Parse state PHASE.H_READ_MSG_BLOCK(18389)DEBUG memtool.phyinit.out_parser Parse retention register listDEBUG memtool.common.factories new instance -> {inst}{'app_state': 1435032830, 'num_records': 1, 'records': [{'state': 1, 'test_id': 200, 'data': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}], 'debug': '[0, 0, 0, 0, 0, 0, 0, 0]', 'err_capt_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0]', 'debug_regs': '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]'}DEBUG memtool.common.factories new instance -> {inst}DEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channelDEBUG memtool.comm.serial_channel Channel is aliveINFO memtool.comm.serial_channel Send reset to targetDEBUG memtool.comm.serial_channel Executing: RERROR libusbsio.hidapi.dev HID device 'b'\\\\?\\hid#vid_1fc9&pid_0146#6&dc7bbf3&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}'' opening failed.ERROR memtool.common.base_test Application load ended with exception: Download incomplete due to configuration error!DEBUG memtool.comm.serial_channel Executing: mw92F918,1 Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hi Jorge, 1. Could you please provide the data on the chain lengths and propagation delays of LpDDR signals in EVK? 2. Our CAD does not allow importing the EVK pcb file in the format it is posted on your site. Can you provide it in ASCII format? sfatyushkin_0-1750135408382.png Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, Your DDR connection is ok. There is no functional problem in swap CA/CB since dual channel device channels are independent in LPDDR4, just keep in mind that bit swapping within each slice/byte lane is OK. Byte swapping is NOT allowed. If you still having signal integrity tests failed, please look for layout issues and try lower operating frequencies. You could try to change the tunning with different settings and check if helps with your design: ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40 TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34) ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20) Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello @JorgeCas ! I am Alexander's colleague. Attached is the CPU and LPDDR connection diagram. Best regards, Serge Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Hello, Could you please share the connections of memory to i.MX device? Best regards. Re: i.MX8MP LPDDR4 CA Training Failed (without it stress test is ok for single freq point) Dear JorgeCas! Happy New Year! We made a new board and ran the memory at 1600 MHz. It doesn't run at higher speeds—we'll investigate this problem.. I compared the net lengths in the KIT in your picture with our calculations in EDA. 1. In the KIT, when calculating net lengths and delays, you didn't take the via lengths into account. 2. In the KIT, when calculating the CK_x_x signal path lengths, the additional sections to the resistors (R9, R10) were incorrectly added to calculated. Please comment on the KIT chain lengths highlighted in red. Best regards, Serge

LPSPI3 経由で FS26 を駆動するにはどうすればいいですか? 開発にはS32K3X4EVB-T172を使用しています。 LPSPI3 を使用して FS26 と通信できないことがわかったので、サンプル コードでこの状況を再現しました。 交換したい LPSPI3_PCS0 = 110 = PTB17 <> LPSPI0_PCS0 = 95 = PTB0 LPSPI3_SCK = 7 = PTD1 <> LPSPI3_SCK = 7 = PTD1 LPSPI3_SIN = 111 = PTD20 <> LPSPI0_SIN = 97 = PTC9 LPSPI3_SOUT = 8 = PTD0 <> LPSPI0_SOUT = 94 = PTB1 配線方法は以下の通りです。 LPSPI3_SCK = J37、番号1、LPSPI0_SCK = J2、番号21に接続 LPSPI3_SIN = J39、番号14、LPSPI0_SIN = J2、番号15に接続 LPSPI3_SOUT = J37、番号3、LPSPI0_SOUT = J2、番号18に接続 LPSPI3_PCS0 = J4、番号5、LPSPI0_PCS0 = J2、番号24に接続 20251219_140651.jpg 既知の障害点は、Sbc_fs26_InitDevice 内の Sbc_fs26_GetDeviceState が FS_STATES_INVALID を返すことです。 5.png ただし、Spi_SyncTransmit を使用すると、CSB が低く引き下げられることがわかります。これは正しいようです。 CSB CSB.jpg MOSI MOSI.jpg 設定を確認しましたが、どこに問題があるのかわかりません。添付ファイルは、LPSPI0 が LPSPI3 に変更されていることを除いて、サンプル コードとほぼ同じです。 1.png 2.png 3.png Re: How to drive FS26 via LPSPI3? 公式の例では、FS26 と通信するためにどの SPI を使用していますか? Re: How to drive FS26 via LPSPI3? LPSPI0の使用 LPSPI0を削除してから以下のドッキングを実行しました。 LPSPI0_PCS0 = 95 = PTB0 = J2 (上位24) LPSPI3_PCS0 = 110 = PTB17 = J4 (下位5) LPSPI0_SCK = 98 = PTC8 = J2 LPSPI3_SCK = 7 = PTD1 = J37 LPSPI3_SCK = 7 = PTD1 = J37 LPSPI0_SIN = 97 = PTC9 = J2 (上位15) LPSPI3_SIN = 111 = PTD20 = J39 (中間14) LPSPI0_SOUT = 94 = PTB1 = J2 (LPSPI3_SOUT = 8 = PTD0 = J37 に接続) ただし、FS26は通信できません。 Re: How to drive FS26 via LPSPI3? これはコード移植の問題ではありません。非常に大きなコードパッケージがあり、LPSPI3がFS26と通信できないという問題が発生しています。質問しやすいように、FS26のサンプルコードを使用し、FS26との通信をLPSPI0からLPSPI3に変更しました。しかし、LPSPI3がFS26と通信できないという同じ問題が依然として発生しています。Spi_SyncTransmitを呼び出すと、CSBとMOSIに対応する応答が表示されます。そのため、原因がわかりません。 Re: How to drive FS26 via LPSPI3? 使用 LPSPI0 LPSPI0_PCS0 = 95 = PTB0 LPSPI0_SCK = 98 = PTC8 LPSPI0_SIN = 97 = PTC9 LPSPI0_SOUT = 94 = PTB1 Re: How to drive FS26 via LPSPI3? クリスマス休暇期間中は、サポートの応答時間は通常より長くなる場合がありますのでご了承ください。ご理解のほどよろしくお願いいたします。 私が見た説明は、私が行っている RTD 上での SPI 通信転送であり、サポートを超える点があります。

RFID 検出エラーについて。 サポートチーム様。 RFID Discover 5.7.0.0をインストールしました。 RFID Discover をインストールして起動した後、添付画像に示すエラーが発生し、ソフトウェアを閉じるしかありませんでした。 これを解決する方法をご存知ですか? 環境： - Windows 11 ホーム（日本語） - Microsoft .NET Framework 4.0がインストールされている - NxpRdLib.dll は、次のフォルダにあります: Program Files(x86)/NXP Semiconductors/RFIDDiscover/V5.7.0.0/Bin - NxpRdLib.dll のバージョンは 17.0.0.2518 です Re: about RFID Discover error. バージョン 5.8 RFID Discover が利用可能です。 新しいバージョン 5.8 をインストールしてもう一度お試しください。 Re: about RFID Discover error. RFID Discover をバージョン 5.8 にアップデートした後でも、添付画像のようにエラーが表示されます。 他に提供すべき情報はありますか?

恩智浦 mpc5744p MCU 板的三维模型 & Devkit MotorGD 板 大家好， 我正在开发一个新的测试平台，包括恩智浦产品，如mpc5744p MCU和DevKit MotorGD板。 我要为我的测试平台买专业的 3D 照片我需要的是： 1. mpc5744p MCU 板 2 的 3D 文件。 我在恩智浦网站上搜索 了 DevKit MotorGD 看板 然后我在 .zip 里找到了这些但我无法使用 Easyeda 打开它们 。 1. LAY-29379_B.zip 2. LAY-29333_E.zip 请谁能帮我打开它们或者获取两块板的 3D 模型文件。 谢谢，祝您愉快！ Re: 3d Model of NXP mpc5744p MCU Board & Devkit MotorGD Board 你好 我在恩智浦网站上进行了搜索，找到了这些 .zip 文件但我无法使用 Easyeda 打开它们 。 1. LAY-29379_B.zip 2. LAY-29333_E.zip 这些是在 Candace: allegro 中设计的布局文件。 我不指望你能从布局设计中提取 3D 模型。 我找到了以下方法： EAGLE + Fusion 360 打开 .brd文件。 使用 Fusion 360 同步功能： 转到 Fusion 360 → 导入 EAGLE 设计。 它将生成一个包含元器件的完整 3D PCB 模型。 导出为 STEP (.step) 或 IGES 格式，用于机械整合。 我不指望你能从布局设计中提取 3D 模型。 通过社区无法共享 500MB 的 STEP 文件。 顺祝商祺！ Peter Re: 3d Model of NXP mpc5744p MCU Board & Devkit MotorGD Board 你好，petervlna、 非常感谢你的答复。 我们使用Eagle + Fusion 360 尝试了建议的解决方案，但不幸的是，我们遇到了文件无法打开的错误提示（如下图所示）。使用EasyEDA、Altium 和 KiCad 等其他 PCB 软件时也会出现同样的问题。 此时，我们迫切需要两块板的.STEP 格式的三维模型。如果您能直接提供这些文件，比如通过Google Drive、OneDrive、MEGA 等云存储服务或任何其他方便的平台，我们将不胜感激。 再次感谢您的支持。我们期待您的答复。 致以最崇高的敬意， Ahmed AhmedKamal_59_1-1765970973937.png Re: 3d Model of NXP mpc5744p MCU Board & Devkit MotorGD Board 你好 好的，在这种情况下，请向恩智浦网络支持提交一份报告。 您还需要与恩智浦签订有效的 NDA 协议，才能获得此类文件。 可以通过我们的支持门户共享 STEP 模型，因为它允许 2GB 的文件，而且我以前也共享过 STEP 文件。 无法在我们的官方系统之外共享内部文件。 顺祝商祺！ Peter Re: 3d Model of NXP mpc5744p MCU Board & Devkit MotorGD Board 您好 petervlna, 非常感谢您的建议，我们已立案，编号为 (Case: 00756530)。 我们希望能尽快拿到文件。 非常感谢。 致以最崇高的敬意， Ahmed AhmedKamal59_0-1766503944936.png

SAF sBoot CMU_FC チェック sBoot で CMU_FC チェックを構成するときにパラメータを設定する方法がわかりません。自分の理解に基づいていくつかの値を設定し、コードを生成しましたが、生成された LFREF 値と HFREF 値は設定した値に基づいてどのように導出されるのでしょうか?計算過程を見せていただけますか？ 私の意見では、上記で設定したパラメータは、RCCR.REF_CNT/HTCR.HFREF/LTCR.LFREF と比較する必要があります。FXOSC=40Mの場合、CMU_FC0チェックをどのように設定すればよいですか?RCCR.REF_CNT/HTCR.HFREF/LTCR.LFREF はいつ設定すればよいですか?値は何ですか? Re: SAF sBoot CMU_FC Checks こんにちは@ziwu 、 すべての計算はS32K3xx RM rev.11に記載されています。 セクション56.5.2 HFREFとLFREFのプログラミング。 よろしくお願いいたします。 ダニエル Re: SAF sBoot CMU_FC Checks 1.RM Rev.11 をチェックしましたが、まだ結果が得られません。バス クロックは何ですか? システム クロックですか? 2.EB tresos をチェックしたところ、「Mcu レジスタ値の最適化」を有効にすると RCCR が 0x50 に設定され、CMU_FC0/3/4 のすべての RCCR が 0x50 になっています。なぜ同じ値になっているのでしょうか?次の式では 0x50 を CAN で取得できません。0x50 を取得するにはどうすればいいですか? ziwu_0-1766105709787.png Re: SAF sBoot CMU_FC Checks こんにちは@ziwuさん 遅くなって申し訳ありません。現在不在のため、早く返信することができませんでした。 システムクロックは、RMにリストされているクロックオプションのいずれかに正確に設定する必要があります。例：表157.オプション A - 高性能モード (CORE_CLK @ 160 MHz)。 そして、バスクロック = レジスタインターフェースクロック = AIPS_SLOW_CLK danielmartynek_1-1766930897683.png danielmartynek_0-1766930828127.png 現在、SAF sBoost ドライバをテストできません。 ただし、CMU が有効になっている場合は、しきい値も MCAL MCU ドライバによって計算され、設定されます。 S32DS IDE と RTD 6.0.0 の例を次に示します。 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-MCAL-MCU-ClockMonitor-v1-0-S32DS36-RTD600/ta-p/2179976 よろしくお願いいたします。 ダニエル Re: SAF sBoot CMU_FC Checks 分かりました、ありがとうございます

[过滤器：smut] Sheetal_Chavan 的帖子正文匹配了 "*该死*"，板 "52693forum-board"。 [过滤器：smut] Sheetal_Chavan 的帖子正文匹配了 " *该死* "，板 "52693forum-board"。 帖子主题新的 MCAL API BLE_SendNbuXtal32MTrim 职位机构： 你好@ovidiu_usturoi、 使用 MCAL 1.0.8集成了新的 API BLE_SendNbuXtal32MTrim。我能用 BLE_SendNbuXtal32MTrim API 替换 PLATFORM_SetXtal32MhzTrim 吗？ 谢谢。 希塔尔-查万 @MichaelHuhn 正文"狗屎" 匹配的过滤模式"*shit*" 。 用户[id=198962,login=Sheetal_Chavan]发表的帖子有留言 uid 2259626。 链接到帖子：新的 MCAL API BLE_SendNbuXtal32MTrim

ls1043aqds 参考设计版本的技术文档 我正在使用 QSPI 下载和 IFC 总线调试基于 ls1043a 处理器的电路板。我在调试过程中遇到了一些问题。你能提供 ls1043aqds 开发板的示意图、参考手册和其他技术材料吗？ Re: Technical documentation for the reference design version of ls1043aqds 你好 对于 LS1043AQDS 参考设计，我可以为您提供以下资源： 1.LS1043AQDS 参考手册-本文档包含有关架构、总线协议、存储器映射和外设接口的详细信息，包括您正在使用的 QSPI 和 IFC 总线配置。 2。原理图-这些提供了电路级的实现细节，有助于调试您的板。 3.QorIQ LS1043A 参考设计材料-其中包括板设计文件、元器件数据表和实施指南。 您可以通过恩智浦网站的QorIQ处理器文档部分访问这些材料。具体而言，请查看 LS1043A 产品页面，那里有可供下载的参考设计材料。 如果您在 QSPI 下载或 IFC 总线实现方面遇到特定问题，我还建议您查看 LS1043A SoC 参考手册，该手册提供了有关这些接口的详细注册器级别信息。 问候 Re: Technical documentation for the reference design version of ls1043aqds 抱歉，我在恩智浦网站上找不到有关ls1043aqds开发板的任何信息。能否提供这些信息的下载链接 Re: Technical documentation for the reference design version of ls1043aqds 抱歉，我在恩智浦网站上找不到有关ls1043aqds开发板的任何信息。能否提供这些信息的下载链接

IMXRT1140-EVK 上の USB ホスト IMXRT1140-EVK に USB ホストが必要です。USB HOST CDC サンプルをインストールしましたが、USB OTG PWR には、コネクテッドデバイスに電力を供給するための 5V がないことに気付きました。何か設定が足りないのでしょうか、アドバイスをお願いします。 私のデバイスは、USB ホストにデータを送信する CDC ACM vcom デバイスです。 Re: USB Host on IMXRT1140-EVK @JACOBTHOMAS_007 この質問については、次の MIMXRT1040-EVKUM を参照してください。 J40(3-4): J48経由の5V_USB_OTG電源 J40(1-2): J45経由の5V_SYS電源 Sam_Gao_0-1765529901526.png Sam_Gao_1-1765529980947.png Re: USB Host on IMXRT1140-EVK 迅速な返信ありがとうございます。 ジャンパーを J40 (1-2) と (3-4) にコネクテッドした後、OTG からの出力電圧は 1.2V のみになります。このポートにコネクテッドされたデバイスを駆動するには、出力が 5V になる必要があると予想しました。 参考までに写真をご覧ください USB voltage.png   Re: USB Host on IMXRT1140-EVK こんにちは@Sam_Gao、このトピックについて何か更新はありますか?どういうわけか、USB VBUS ピンには 1.2V しか表示されません。 Re: USB Host on IMXRT1140-EVK @JACOBTHOMAS_007 「このポートにコネクテッドされたデバイスを駆動するには、出力が 5V である必要があると予想しました。」 --> USB ポートをマスターとして使用して、スレーブ デバイスに電力を供給したいと考えていましたか? MIMXRT1040-EVKUMの表11を次のように参照してください。 USBコネクタJ48を介した外部ソース（コネクタがホストモードで動作している場合）または電源スイッチU30を介した5V_SYS電源（コネクタがデバイスモードで動作している場合） Sam_Gao_0-1765876059106.png SO、USBポートをマスター/ホストとして使用する場合は、手順を順に確認してください。 1. 5V_SYSは動作可能です: SW6 + J45 + J40(1-2のみ😞J45 経由の 5V_SYS 電源。 2. ホスト モード (ID = GND) で動作させます。 Sam_Gao_1-1765877164735.png Re: USB Host on IMXRT1140-EVK サム・ガオ ありがとうございます。USB VBUS を +5V にできるようになりましたが、一方で USB デバイスを EVK otg ポートに接続しても、デバイスを検出できません。また何かが欠けているようです。 Re: USB Host on IMXRT1140-EVK @Sam_Gaoありがとう、うまくいきました!

S32DS IDE 是否可以安装 Eclipse Marketplace 我试图为 eclipse 安装 copilot 插件。 我以为 S32DS 是由 eclipse 继承而来的，那么这种操作应该是可行的。 但我发现根本没有日蚀市场。 所以我想知道：是否可以先安装 eclipse marketplace，然后再安装插件（包括 copilot 等）。 或者我们可以说，S32DS 的设计初衷就是不兼容大多数第三方插件？ 这个问题应该同时适用于 S32DS-S32PLATFORM 和 S32DS-ARM 第三方（高级）插件 Eclipse IDE 使用和设置 Re: Is is possible for S32DS IDE to install Eclipse Marketplace 你好@noel_0319 在 S32DS 中安装 GitHub Copilot 在技术上是可行的，因为 IDE 是基于 Eclipse 的。不过，由于该功能依赖于 Eclipse，我们不提供官方支持，也不能保证其正常运行。 BR、VaneB Re: Is is possible for S32DS IDE to install Eclipse Marketplace 没关系，我只是想确保恩智浦没有禁止第三方插件的官方限制，否则我的努力都是白费。

IMX8MP 是否有在单个板上使用多个 LPDDR4 模块的 PCB 参考设计？ IMX8MP 是否有在单个板上使用多个 LPDDR4 模块的 PCB 参考设计？ i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus 回复： Does the IMX8MP have a PCB reference design that uses multiple LPDDR4 modules on a single board? 多个 DDR 芯片并行的 PCB 布局示例 回复： Does the IMX8MP have a PCB reference design that uses multiple LPDDR4 modules on a single board? 我们所有的设计都在这里： FRDM i.MX 8M Plus 开发板 | 恩智浦半导体 i.MX 8M Plus 评估套件|恩智浦半导体 您可以参考

IMX8MP RGMII接続（PHYなし） こんにちは、 PHY を使用せずにスイッチへのイーサネット RGMII 接続を設定しようとしています。他の投稿に基づいて、デバイス ツリーを次のように構成しました。 &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; phy-mode = "rgmii"; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; pinctrl_fec: fecgrp { fsl,pins = , , , , , , , , , , , , , ; }; pinctrl_fec_phy: fecphygrp { fsl,pins = , ; }; ethtool では「Link detected: yes」と表示され、ifconfig では IP アドレスが割り当てられたことが示されます。しかし、ボードとの間で ping を実行することができません。このCASEでピンが正しく設定されているかCAN確認できますか?ありがとう。 i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus Re: IMX8MP RGMII Connection with No PHY ご返信ありがとうございます。私はすでにその文書を見て、ここまで進むことができました。しかし、物事をうまく進めるためには、まださらなる支援が必要です。 Re: IMX8MP RGMII Connection with No PHY 同封のファイルを参照してください。これはあなたのCASEに非常に役立ちます。 Re: IMX8MP RGMII Connection with No PHY RGMIIの場合、現在のBSPはこれをデフォルトでサポートしているので、それを参照することができます。 https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L390

Best DevOps Practices for Embedded Systems Development Hey everyone, I wanted to discuss the best practices for implementing DevOps in embedded systems development. We all know that embedded systems have unique challenges, but combining DevOps principles and leveraging the right DevOps solutions can significantly improve our workflows. Here are some practices I’ve found useful: Automated Builds and CI/CD Setting up automated build pipelines is crucial for embedded systems. With CI/CD, we can automate testing, flashing, and deployment to real devices, ensuring we detect errors early. Version Control for Firmware and Hardware Treat firmware like software – using Git or similar tools for version control, along with hardware abstraction layers (HALs), helps manage both software and hardware dependencies in sync. Continuous Integration with Hardware in the Loop (HIL) Integrating HIL testing into your CI pipeline ensures you are validating against real-world scenarios, not just simulated environments. This can help catch issues that only occur with actual hardware. Containerization for Embedded Software Using Docker or similar tools for software environment replication ensures consistency across development, testing, and deployment phases, even when working with embedded platforms. I'd love to hear your thoughts and any additional practices you’ve found effective. How are you integrating DevOps into your embedded development workflows? DSC Re: Best DevOps Practices for Embedded Systems Development We are trying to do just the things you are proposing. Do you have any concrete advice on how to do it?

MT53E768M32D4DT-046 AAT:E DDR 部分是否与 I.MX8QM 兼容 你好， ，我们准备将 DDR 部件号改为MT53E768M32D4DT-046 AAT:E，I.MX8QM 处理器是否与该部件兼容，请确认。 谢谢& ， Mallikarjuna。 Re: MT53E768M32D4DT-046 AAT:E DDR part compatible with I.MX8QM or not 你好 NEEDEOLCALL、 请确认美光 DDR 部件（MT53E768M32D2ZW-046 AAT:C）是否与 I.MX8QM 处理器兼容。 感谢& ， Mallikarjuna， [email protected]。 Re: MT53E768M32D4DT-046 AAT:E DDR part compatible with I.MX8QM or not 您好，感谢您的咨询！我们已经验证了 i.MX8QM 处理器（基于 NXP 官方兼容性指南和数据表）与美光 MT53E768M32D4DT-046 AAT:E DDR4 内存的兼容性。是的，该内存元器件与 i.MX8QM 完全兼容，无需任何硬件修改即可直接用于您的设计。以下是详细的分析和确认。 兼容性概述 i.MX8QM DDR 控制器规格： 支持 DDR4 内存，数据总线宽度：16 位或 32 位（x16/x32 组织）。 最大密度：每个芯片 8 Gb（1 GB），支持单级/双级配置，总容量高达 32 GB。 速度支持：DDR4-2400 MT/秒（CL 值 17-17-17），时序符合 JEDEC JESD79-4B 标准。 控制器：DDRSS（DDR 子系统），集成 PHY，支持 ODT（On-Die Termination）和 Bank Group 架构。 电源：1.2V VDDQ，0.6V VTT，兼容电源模式。 MT53E768M32D4DT-046 AAT:E 规格： 容量：8 Gb (1 GB) DDR4 同步动态随机存取存储器(SDRAM)，x32 组织（32 位数据宽度）。 速度DDR4-2400 MT/s (PC4-19200)，计时 CL=17-17-17。 代码包：FBGA（x32 配置），电压 1.2V，工作温度 -40°C 至 +95°C（工业级）。 其他：支持 3D 堆叠 动态随机存取存储器(DRAM)，低功耗 (IDD < 50 mA)。 兼容性确认： 总线宽度：i.MX8QM 支持 x32 DDR4，MT53E768M32D4DT-046 AAT: E 的 x32 组织无需桥接即可直接匹配。 密度和级数：支持 8 Gb 单芯片，支持单级配置，符合 i.MX8QM 的 8 Gb/芯片限制（恩智浦兼容性指南表 2-1 确认了美光 MT53E 系列）。 速度/定时：2400 MT/s 完全符合 i.MX8QM 的支持范围（最高 3200 MT/s），定时参数（tRCD=17 ns，tRP=17 ns）符合控制器的默认设置。 核实来源： NXP i.MX 8M/8QM 内存兼容性指南（web:0、web:2、web:3）：Micron MT53E 系列（如 MT53E768M32D4DT）明确列为经过验证的部件，支持 8 Gb x32 配置。 恩智浦社区帖子（web: 1，web: 5）：用户已成功使用类似的 MT53E768M32D4DT-046 WT: A 在 i.MX8QM 板上运行，通过了压力测试（使用 8GB 配置进行压力测试）。 数据表：i.MX8QM 参考手册（IMX8QMHDG 修订版 1，2024），第 7.3 节 DDR 控制器，支持 JESD79-4 DDR4 标准，兼容美光部件。 潜在的考虑因素 等级和容量：如果使用多芯片配置（如 2 x 8 Gb = 16 GB），请确保将级配置为单级/双级（i.MX8QM 最多支持 4 个级）。建议使用 TI DDR 配置工具进行定时验证。 电源/热管理：确保 VDDQ = 1.2V、VTT = 0.6V，并添加一个 10 µF 的去耦电容。x32 配置功耗约为 1.5 瓦/芯片；EVM 板验证显示没有散热问题。 软件配置：在 U-Boot 或 Linux 电路板支持包 中，使用 DDR 工具（恩智浦 DDR 工具）生成与 MT53E 系列兼容的寄存器设置（.h 文件）。 供货情况：该零件仍在生产（非 EOL），DigiKey 有充足的库存，单价约为 15-20 美元（1000 件量）。 建议采取的下一步措施 测试建议：将内存更换为 i.MX8QM EVK 板进行测试（恩智浦开发板支持 DDR4 x32）。如有需要，恩智浦可提供免费的 DDR 验证服务（community.nxp.com）。 替代选择：如果库存有限，可选择兼容替代品，如 Samsung K4A8G085WB-BCPB（8 Gb x32 DDR4-2400）。 如果您有特定的设计文件（如 DDR 时序设置）或需要恩智浦支持部门的联系信息，请与我分享，以便我提供进一步的帮助！ 致以最诚挚的问候，杰克 Re: MT53E768M32D4DT-046 AAT:E DDR part compatible with I.MX8QM or not 你好@mallibeerala是的，它是兼容的。 您可以查看 i.MX8QM 的 ddr 工具和兼容指南： i.MX 8/8X/8XLite - LPDDR4 和 DDR3L 内存兼容性指南 - NXP Community i.MX 8/8X 系列 DDR 工具版本-恩智浦社区 希望能对您有所帮助 祝您有美好的一天 顺祝商祺！ Rita Re: MT53E768M32D4DT-046 AAT:E DDR part compatible with I.MX8QM or not 你好， ，请提供"i.MX8QM 的 ddr 工具" 路径。在该工具中，我将直接检查"MT53E768M32D2ZW-046 AAT:C" DDR 是否兼容。 在兼容指南列表中没有该部件。 谢谢& ， Mallikarjuna。 Re: MT53E768M32D4DT-046 AAT:E DDR part compatible with I.MX8QM or not @mallibeerala工具在这里： i.MX 8/8X 系列 DDR 工具发布 如有任何问题，请随时联系我们

配置I2C的问题 用MCUXpresso Config Tools 25.06根据示例生成RT1061的工程里，我并不是选的i2c的示例，但是因需要用到i2c,所以在 _0-1764309587752.png 里做了配置，生成的代码里的引脚总是置0： _1-1764309630095.png 我对比了使用i2c的示例生成的工程里，这里应该是置1的，请问，是不是需要在MCUXpresso Config Tools的其他地方做配置，才能正确生成代码呢？请给个指示。谢谢 Re: 配置I2C的问题 Hi @ChenHua. Thank you for your question! This parameter corresponds to the Software Input On field. Gavin_Jia_0-1764318187719.png In the PinConfig tool, you need to configure the following locations if you want to enable: Gavin_Jia_1-1764318303100.png Best regards, Gavin

How to Reduce A-Core and DDR Frequency on i.MX8ULP I want to reduce both the A-core frequency and the DDR frequency on the i.MX8ULP. Could you please guide me on how to achieve this and which registers or configurations need to be modified? Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hello, You can take a look in the next application note (4.3 Use DVFS): Optimizing Power Consumption for i.MX 8ULP Best regards. Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hi @JorgeCas I have used DVFS and I want to reduce the A-core CPU frequency. Currently, the frequency is showing around 808 MHz, and I would like to lower it as much as possible. Below are the logs I am getting: root@imx8ulp-9x9-lpddr4-evk:~# echo 1 > /sys/devices/platform/imx8ulp-lpm/enable [ 467.490570] DDR enter low frequency mode root@imx8ulp-9x9-lpddr4-evk:~# mhz 808 MHz, 1.2392 nanosec clock Could you please guide me on how to reduce the A-core frequency, and which settings or configurations need to be changed? Thanks. Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hello, According to application note, you need to use imx8ulp-evk-nd.dtb device tree but as I can see in your log, you are using 9x9 board and we do not have a device tree to do the changes. You can use it as reference to modify your device tree and try again: https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts  Best regards. Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Thanks @JorgeCas  root@imx8ulp-9x9-lpddr4-evk:~# echo 1 > /sys/devices/platform/imx8ulp-lpm/enable root@imx8ulp-9x9-lpddr4-evk:~# mhz 655 MHz, 1.5267 nanosec clock From the reference, I updated my .dts file, and now I am able to get the A-core frequency down to 650 MHz. I would like to reduce the A-core frequency further, ideally to around 200 MHz. Could you please guide me on how to achieve this? Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hello, Unfortunately, we do not have documentation to reduce the frequency bellow 650 MHz for Cortex - A core. According to application note, is working with the minimum operating voltage of VDD_DIG1/2 (minimum operating frequency) and our engineer commented in your previous post that PLL will not provide a lower frequency. You could try to modify PLL registers manually. Best regards. Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hello, @JorgeCas  Thank you for the clarification. I understand that 650 MHz is the lowest documented frequency supported by the PLL for the Cortex-A core. To further reduce power consumption, I would like to explore manually modifying the PLL configuration. Could you please advise which PLL (registers or clock path) controls the Cortex-A clock on i.MX8ULP, and whether there are any recommended settings or constraints when attempting to lower the frequency below 650 MHz? Any guidance or reference documentation on safely modifying the PLL registers would be greatly appreciated. Best regards, Yash Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP Hello @JorgeCas, Just checking in on my previous question regarding lowering the Cortex-A core frequency below 650 MHz by modifying the PLL configuration on i.MX8ULP. I wanted to check if you had a chance to review it. Any guidance would be greatly appreciated. Thank you, Yash

使用比 MIMXRT1170-EVKB 更大的与非闪存 你好。我正在研究使用带有与非闪存的 RT1170 作为遥测存储器的可行性研究。评估板 MIMXRT1170-EVKB 上有具有 2Gb 存储空间的 MT29F2G08ABAGAH4 与非闪存。SDK 中有一个名为 evkbmimxrt1170_flash_component_nand_semc_cm7 的示例，演示了如何使用内存。这个例子非常棒，效果也非常好。 如数据表中的这张图片所示，现在我们的目标是在定制板上使用这款微控制器（特别是 MIMXRT1176CVM8A），其中 64Gb 的大型与非闪存 MT29F64G08AECABH1 分成 2 个芯片，每个芯片 32Gb。暂时采用异步模式。 2025-11-30 21_28_11-Data Sheet_ 32_64_128_256Gb Async_Sync NAND (M73A) - nand_memory_datasheet.pdf —.png 您能告诉我如何实现这一目标吗？必须如何修改 SDK 示例才能使用该内存？ 在此先表示感谢。向 Vojtech 致以最崇高的敬意。 Re: Using larger NAND flash than on MIMXRT1170-EVKB 你好@Kan_Li，感谢您的快速回复。 我们知道，如果不付出努力，就无法获得本机支持，但我们有一个简单的方法来解决这个问题。我们将通过 GPIO 引脚驱动 CE# 引脚，而不是 SEMC 驱动 CE# 引脚，只需将一个 CE# 引脚置低，执行 SEMC 操作，然后断开引脚。我们每次只选择一个模具。 对于 R/B# 引脚，我们将通过 AND 栅芯片（如 74AUP1G09GW）将它们连接起来。由于我们希望一次只使用一个模具，所以这样做会很顺利。每个芯片都可以像直接连接一样驱动引脚。 现在我需要的建议是如何正确设置SEMC控制器的示例，以便通过IPCMD和AXI正确地与该内存进行交互。谢谢。 问候 Vojtech Re: Using larger NAND flash than on MIMXRT1170-EVKB 你好@Kan_Li、 好吧，我明白你的意思了。让我换一种方式来表达我的支持请求。比方说，我只想使用带有一个 LUN 的 die 1，而第二个则完全没有连接，被遗忘了。芯片 1 的连接方式将与 DevKit 上的与非闪存相同，CE# 由 SEMC 通过与示例中相同的引脚驱动。因此，我基本上只是将 DevKit 的 2 Gb 与非闪存替换为我之前提到的同一个系列的 32 Gb 芯片的一半。 现在，请问我需要采取哪些步骤来重写这个例子才能正常使用这个新的与非闪存？ 谢谢。向 Vojtech 致以最崇高的敬意。 Re: Using larger NAND flash than on MIMXRT1170-EVKB 你好@VojtechBaranek、 是的，你说得对！对于您选择的芯片，我认为列地址位数（columnAddrBitNum）应使用 kSEMC_NandColum_13bit。 祝您愉快， Kan ------------------------------------------------------------------------------- 注： - 如果本帖回答了您的问题，请点击"标记正确" 按钮。谢谢！ - 我们会在最后一次发帖后的 7 周内跟踪主题，之后的回复将被忽略 如果您以后有相关问题，请打开一个新主题并参考已关闭的主题。 ------------------------------------------------------------------------------- Re: Using larger NAND flash than on MIMXRT1170-EVKB 你好@Kan_Li、 这对于你提到的字段来说是感知的。难道不应该同时扩展 columnAddrBitNum 吗？ 致以最崇高的敬意，Vojtech。 Re: Using larger NAND flash than on MIMXRT1170-EVKB 你好@VojtechBaranek、 如果是这样，我想你只需按如下方法更新内存大小即可： Kan_Li_1-1764745442686.png 祝您愉快， Kan ------------------------------------------------------------------------------- 注： - 如果本帖回答了您的问题，请点击"标记正确" 按钮。谢谢！ - 我们会在最后一次发帖后的 7 周内跟踪主题，之后的回复将被忽略 如果您以后有相关问题，请打开一个新主题并参考已关闭的主题。 -------------------------------------------------------------------------------

CBTL04083A 用于切换单端 1.8V GPIO/UART 大家好 我知道 CBTL04083A 是专为高速差分信号开关而设计的，而且有很多专门用于 GPIO/UART 开关的好产品。但是，我们目前需要使用 CBTL04083A 版本一个兼容差分信号和单端低速 1.8 V I/O（GPIO 和 UART）的 MUX 模块。差分 PCB 布局将在本模块之外处理。 据我所知，CBTL04083A 的开关基本上是场效应管，因此它应该可以切换单端信号。此外，1.8 V GPIO/UART 电平为 0-1.8V DC，属于设备的输入/共模范围。一个值得关注的问题是推荐的差分摆幅VID ≤ 1.6 V，因为 1.8 V 的 GPIO 可能会超过这个范围。我的假设是，VID 指南针对的是高速信号完整性，因此在这种低速使用情况下可能不是问题。 计划的 UART - CBTL04083A 连接：TX → P，RX → N为同一差分对，开关在一起。 请确认这种用法是否可用于可靠的通信，并分享任何最佳做法建议？ Re: CBTL04083A to switch singled-ended 1.8V GPIO/UART 您好__OTL__ 日安 你说得没错，一个简单的直观方法就是把它理解为一个场效应管，不断被激活和失活。 因此，只要是直流和低频信号，它都能通过： -信号的电压范围在设备的 VDD 和绝对最大额定值范围内。 - 共模电压和摆幅不违反电气特性。 对于 1.8 V 逻辑电压（0-1.8V)，这通常是安全的，因为该设备支持高达 3.3 V 的电源，而且绝对最大额定值高于 1.8 V。 VID 规格适用于高速差分线对，以确保信号完整性并将失真降至最低。对于低速 GPIO/UART 来说，这一点并不重要，因为..： - 对带宽的要求要低得多。 - 在这种速度下，场效应晶体管开关的行为几乎与短路一样。 因此，在这种情况下，超过 1.6 V 的差分摆幅不是功能问题。 同一差分对的 TX → P 和 RX → N 这在电气上是可以接受的，只是需要注意一些问题： 两条线路将一起切换，这对 UART TX/RX 来说是没有问题的。 确保未使用的差分路由不会引入耦合或噪声。 总之，对于可靠的 UART/GPIO 通信来说，计划中的使用是可以接受的；只是在设计布局时要注意避免任何噪声。 希望这些信息对您有所帮助，如果您还需要其他帮助，请告诉我。 祝你愉快，好运连连。