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How to Reduce A-Core and DDR Frequency on i.MX8ULP

I want to reduce both the A-core frequency and the DDR frequency on the i.MX8ULP.
Could you please guide me on how to achieve this and which registers or configurations need to be modified?

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hello,

You can take a look in the next application note (4.3 Use DVFS):

Optimizing Power Consumption for i.MX 8ULP

Best regards.

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hi @JorgeCas

I have used DVFS and I want to reduce the A-core CPU frequency. Currently, the frequency is showing around 808 MHz, and I would like to lower it as much as possible.
Below are the logs I am getting:

root@imx8ulp-9x9-lpddr4-evk:~# echo 1 > /sys/devices/platform/imx8ulp-lpm/enable
[ 467.490570] DDR enter low frequency mode 
root@imx8ulp-9x9-lpddr4-evk:~# mhz 
808 MHz, 1.2392 nanosec clock

Could you please guide me on how to reduce the A-core frequency, and which settings or configurations need to be changed?

Thanks.

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hello,

According to application note, you need to use imx8ulp-evk-nd.dtb device tree but as I can see in your log, you are using 9x9 board and we do not have a device tree to do the changes.

You can use it as reference to modify your device tree and try again:

https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx8ulp-evk-nd.dts

Best regards.

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Thanks @JorgeCas

root@imx8ulp-9x9-lpddr4-evk:~# echo 1 > /sys/devices/platform/imx8ulp-lpm/enable
root@imx8ulp-9x9-lpddr4-evk:~# mhz
655 MHz, 1.5267 nanosec clock

From the reference, I updated my .dts file, and now I am able to get the A-core frequency down to 650 MHz. I would like to reduce the A-core frequency further, ideally to around 200 MHz. Could you please guide me on how to achieve this?

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hello,

Unfortunately, we do not have documentation to reduce the frequency bellow 650 MHz for Cortex - A core.

According to application note, is working with the minimum operating voltage of VDD_DIG1/2 (minimum operating frequency) and our engineer commented in your previous post that PLL will not provide a lower frequency.

You could try to modify PLL registers manually.

Best regards.

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hello, @JorgeCas

Thank you for the clarification. I understand that 650 MHz is the lowest documented frequency supported by the PLL for the Cortex-A core.

To further reduce power consumption, I would like to explore manually modifying the PLL configuration. Could you please advise which PLL (registers or clock path) controls the Cortex-A clock on i.MX8ULP, and whether there are any recommended settings or constraints when attempting to lower the frequency below 650 MHz?

Any guidance or reference documentation on safely modifying the PLL registers would be greatly appreciated.

Best regards,
Yash

Re: How to Reduce A-Core and DDR Frequency on i.MX8ULP

Hello @JorgeCas,

Just checking in on my previous question regarding lowering the Cortex-A core frequency below 650 MHz by modifying the PLL configuration on i.MX8ULP. I wanted to check if you had a chance to review it. Any guidance would be greatly appreciated.

Thank you,
Yash