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TEA2017启动异常 我参照UM11613文件,设计PFC+LLC电路,计划输出58V/13A。(TEA2017外围电路参数目前均与UM11613设计文件相同) 谐振腔参数为Lr=22uH,Lm=150uH,Cr=220nF ,输出暂采用带中心抽头的异步整流方式 目前在TEA2017上电启动后,仅能工作几百us就会停止工作。使用Ringo查看MTP并未看到触发保护(TEA2017所有参数默认)。这种情况下我应该检查哪一部分的电路,使其能正常工作? 1753775905739.png 1753776103887.png image.png Re: TEA2017启动异常 亲爱的 Yi 感谢您提供的补充信息。请使用设计工具中的推荐元器件。此外,MOSFET 和请按照 Magnetic_Implementation sheet 中的建议创建相应的电感器和变压器。 我可能需要联系应用工程师,就您的问题寻求建议。他们总是要求提供以下信息。 请分享: 客户:? 最终客户:?(可以与客户相同) 最终应用: ? 国家: 中国中国 年产量:? 致以最崇高的敬意 约瑟夫 Re: TEA2017启动异常 在我的次级侧,只有一个 TL431 反馈电路,而且我没有驱动任何负载。 Re: TEA2017启动异常 我将 Cr 改为 147 nF,但结果仍和以前一样。将温度从 333 K 调到 233 K 后,它就停止工作了。 image.png 我使用您提供的 Excel 工具进行了计算,结果显示 fo=88千赫.我不明白为什么 TEA2017 在 233 K 时停止工作。 image.png image.png image.png 在项目 2.1 中,我参考了 UM11613 中的 LLC 驱动器设计,并使用晶体管进行关断,这与第 2.1 节中指定的设置不同。在这种情况下,我应该如何调整参数设置,还是可以忽略这种差异? image.png 我已经购买了 TEA2017/3Y,到货后将用于后续测试。 非常感谢你们的帮助。 Re: TEA2017启动异常 亲爱的 Yi 我认为,随着负载的增加,TEA2017 试图通过降低频率来应对负载。这是所有 LLC 控制器的正确行为。然而,随着频率的降低,它已达到增益曲线的峰值,进一步降低频率将无法增加增益=功率来应对负载的增加,反而会降低增益=功率。 JozefKozon_1-1753851047482.png 您需要对 LLC 进行设计,使增益曲线的增益峰值向左和向上移动,这样随着负载的增加=>频率的降低,增益峰值就不会达到。请将 Cr 从 220nF 减少到例如150nF。这将改变增益曲线,使其能够应对功率的增加。 您可以使用我在上一个答案中附上的 LLC 设计工具。输入所需的规格,将计算出您的 TEA2017 外部元器件。 JozefKozon_2-1753851393951.png JozefKozon_3-1753851442620.png 另外,请考虑使用改进后的 TEA2017AAT/3 代替 TEA2017AAT/2。请参见附件。 致以最崇高的敬意 约瑟夫 Re: TEA2017启动异常 我使用的是 TEA2017AAT/2,注意到在触发信号停止输出之前,谐振频率突然从 333K 下降到 233K。为什么会这样? ff7401c93a337aa7c47c4a51b3da276.jpg 15ae105bea832f9e872b985aecd787d.jpg Re: TEA2017启动异常 亲爱的 Yi 您使用的是哪个 TEA2017?我们建议使用最新的TEA2017AAT/3版本。 JozefKozon_0-1753784656545.png 请将 Cr 从 220nF 降至 150nF,并观察启动行为。 请使用随附的设计工具来计算推荐的元器件。 致以最崇高的敬意 约瑟夫
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バンドギャップ電圧測定 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> これは、マイクロコントローラに搭載されているバンドギャップ電圧の測定を示すSWの例です。 バンドギャップ電圧は、内部ATDチャネルにルーティングされます。ATDコンバータは入力電圧を測定し、フラッシュメモリにある変数に格納します。 SWサンプルプロジェクトは、MC9S12XEP100デバイス用のCodeWarrior v5.1で作成されています。 全般
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The Android Booting process Some questions arise when we think about the Android boot sequence. What is the Zygote, init.rc, what is the difference between the linux kernel and the android linux kernel?. This document is intended to explain how the booting process runs. Consider the following graph: Step 1: Power On and System Startup When we press the power button, the Boot ROM code starts executing from a pre-defined location which is hardwired in ROM. It loads the Bootloader into RAM and starts executing. Step 2: Bootloader The bootloader is a small program which runs before Android does. This is NOT part of the Android operating system. The bootloader is the place where manufacturer puts their locks and restrictions. The bootloader executes in two stages. In the first stage it detects external RAM and loads a program which helps in the second stage. In the second stage, the bootloader setups the network, memory, etc, which requires to run kernel. The bootloader is able to provide configuration parameters or inputs to the kernel for specific purposes. The bootloader can be found at: /bootable/bootloader/legacy/usbloader This legacy loader contains 2 important files: 1- Init.s :: Initializes stacks, zeros the BSS segments and  call_main() in main.c 2- Main.c :: Initializes hardware (clocks, board, keyboard, console) and creates linux tags. Step 3: Kernel The Android kernel starts in a similar way as the linux kernel.  As the kernel launches, is starts to setup cache, protected memory, scheduling and loads drivers. When the kernel finishes the system setup, it looks for “init” in the system files. What is the difference between the linux and android kernels?, here's a list of changes/addons that the Android Project made to the Linux kernel: Binder: It is an Android specific interprocess communication mechanism and remote method invocation system. ashmem:  "Android Shared Memory". It is a new shared memory allocator, similar to POSIX SHM but with a different behavior and sporting a simpler file-based API. pmem: "Process memory allocator": It is used to manage large (1-16+ MB) physically contigous regions of memory shared between userspace and kernel drivers. logger:  This is the kernel support for the logcat command. wakelocks: It is used for power management files. It holds the machine awake on a per-event basis until wakelock is released. oom handling: It kills processes as available memory becomes low. alarm manager: It lets user space tell the kernel when it would like to wake up. RAM_CONSOLE: Allows to save kernel printk messages to a buffer in RAM, so that after a kernel panic they can be viewed in the next kernel invocation. USB gadget driver for ADB yaffs2 flash filesystem Step 4: init process Init is the very first process, we can say it is a root process, or the grandfather of all processes. The init process has two responsibilities.      1- Mounts directories like /sys , /dev    or /proc      2- Runs init.rc script - The init process can be found at /init :: /system/core/init - Init.rc file can be found at :: /system/core/rootdir/ Android has specific format and rules for init.rc files. More information about this rules can be found in: What is inside the init.rc and what is it used for. At  this stage, you can finally see the Android logo in your screen. Step 5: Zygote and Dalvik In Java, we know that a separate Virtual Machine instance will popup in memory for separate per app, but in the case of Android, the VM should run as quick as possible for an app. But what happens if you have several apps thus launching several instances of the Dalvik (VM)?, it would consume an immense amount of memory. To overcome this problem, the Android OS has a system called “Zygote”.  The Zygote enables code sharing across the Dalvik VM, achieving a lower memory footprint and minimal startup time.  Zygote is a virtual machine process that starts at system boot. The Zygote preloads and initializes core library classes. The Zygote loading process: Load Zygote Init class: /frameworks/base/core/java/com/android/internal/os/ZygoteInit.java registerZygoteSocket() :: It registers a server socket for zygote command connections. preloadClasses() :: Is a simple text file that contains a list of classes that need to be preloaded, you can find the file at /framework/base preloadResources()  :: Everything that is included in the android.R file will be loaded with this method (themes and layouts). At this time, you can see the boot animation. Step 6: System service After the above steps are completed,  Zygote launches the system services.  The Zygote forks a new process to launch the system services. Core services: Starting power manager Creating the Activity Manager Starting telephony registry Starting package manager Set activity manager service as system process Starting context manager Starting system contact providers Starting battery service Starting alarm manager Starting sensor service Starting window manager Starting Bluetooth service Starting mount service Other services: Starting status bar service Starting hardware service Starting NetStat service Starting connectivity service Starting Notification Manager Starting DeviceStorageMonitor service Starting Location Manager Starting Search Service Starting Clipboard Service Starting checkin service Starting Wallpaper service Starting Audio Service Starting HeadsetObserver Starting AdbSettingsObserver Now we have finally completed the booting process (system service are up and running in memory). Need to analyze the Android Bootup? The logcat ::  Use adb to get the booting process events from the logcat. ‘adb logcat –d –b events | grep “boot” ‘adb logcat –d | grep preload’ More information about ADB can be found here: Using ADB with your Sabre Board Re: The Android Booting process Good Document, I get answers for some of my questions. Really appreciate for the simplicity and the way you expressed.SergioSolis Re: The Android Booting process Important to understand is the fact that "Android" alone is not entirely an Operating System, it is rather the User Space of Linux Kernel. Android is based on the Linux Operating System, the GNU Linux kernel. Boot Process is Architecture dependent i.e. X86 and ARM (e.g A8 Cortex) have differences, ARM requires a signed first stage loader so there is a two stage boot process as the article says but does not clearly say its for ARM, Android now runs on x86 as well. If you are interested reading upon the x86 boot process see my white paper: "https://sites.google.com/site/weqaar/Home/files/bootSector_code.pdf?attredirects=0&d=1" On ARM the boot process looks like: 1) X Loader (ARM specific) 2) Boot strapper (i.e. uBoot) - jumps to kernel entry point (head.s) 3) Kernel loads init (i.e. /sbin/init) 4) /sbin/init then reads /etc/inittab, then "si::sysinit:/etc/init.d/rcS" (systemV init) 5) rcS creates device files (i.e. using mtab, mounts important fs i.e. /sys), forks daemons or demons whatever 6) getty is then attached to virt terminals, bash is then executed on user login by getty Dalvik is a Register VM, a user space process for most of the part, JAVA eh. I forked an embedded Linux distro, that is not based on any other distro i.e. Debian, its a good starting point for anybody wanting to learn boot stuff (for ARM specially), runs in QEMU, here is the doc: "https://sites.google.com/site/weqaar/Home/files/DaaS-Embedded-Linux-v1.03.pdf?attredirects=0&d=1" I can make the sources with toolchain available if anybody wants, good stuff it is I can tell you that. Books I wold recommend: ISBN 10: 0-8493-4058-6 ISBN 10: 0-137-01783-9 The diagram shows daemons coming off the Kernel which is not entirely true, Kernel processes or Kernel Daemons e.g. kswapd are forked by the Kernel whereas Init forks user-space processes or daemons e.g. ssh Re: The Android Booting process This is really good document. Thanks for posting.
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Varification of EMC Compliance for MYD-Y6ULX-CHMI The MYD-Y6ULX-CHMI Display Panel is an ultra-low cost Human Machine Interface (HMI) solution based on 528MHz NXPi.MX6UL/6ULL ARM Cortext-A7 processor. It is a Linux-ready device with ported QT, can be used in various applications including POS, Intelligent access control and more others. The panel provides a well-designed hardware with various peripherals and rich software resources to help users accelerate their time to the market. The MYD-Y6ULX-CHMI consists of an MYD-Y6ULX-HMI Development Board and a 7-inch capacitive LCD mounting on its top. The LCD offers 800x480 pixels display resolution. The MYD-Y6ULX-HMI Development Board provides peripherals and interfaces including RS232, RS485, Ethernet, USB Host/Device, LCD, Camera, TF card slot and etc. Considering wireless communication and dial-up functions, MYIR offers an optional IO board MYB-Y6ULX-HMI-4GEXP for the MYD-Y6ULX-CHMI Display Panel. The IO Board features on board AP6212 module for WiFi/Bluetooth and a Mini-PCIe interface for USB based 4G LTE module. Moreover, the IO Board has extended one more Ethernet interface and Audio in/out ports to further enhance the functionality of the panel, thus making a complete solution for HMI applications. The MYD-Y6ULX-CHMI has passed the verification of EMC Compliance.           MYD-Y6ULX-CHMI Display Panel                            MYD-Y6ULX-CHMI Display Panel + MYB-Y6ULX-HMI-4GEXP The MYD-Y6ULX-CHMI Display Panel is an ultra-low cost Human Machine Interface (HMI) solution based on 528MHz NXPi.MX6UL/6ULL ARM Cortext-A7 processor. It is a Linux-ready device with ported QT, can be used in various applications including POS, Intelligent access control and more others. The panel provides a well-designed hardware with various peripherals and rich software resources to help users accelerate their time to the market. The MYD-Y6ULX-CHMI consists of an MYD-Y6ULX-HMI Development Board and a 7-inch capacitive LCD mounting on its top. The LCD offers 800x480 pixels display resolution. The MYD-Y6ULX-HMI Development Board provides peripherals and interfaces including RS232, RS485, Ethernet, USB Host/Device, LCD, Camera, TF card slot and etc. Considering wireless communication and dial-up functions, MYIR offers an optional IO board MYB-Y6ULX-HMI-4GEXP for the MYD-Y6ULX-CHMI Display Panel. The IO Board features on board AP6212 module for WiFi/Bluetooth and a Mini-PCIe interface for USB based 4G LTE module. Moreover, the IO Board has extended one more Ethernet interface and Audio in/out ports to further enhance the functionality of the panel, thus making a complete solution for HMI applications. The MYD-Y6ULX-CHMI has passed the verification of EMC Compliance.           MYD-Y6ULX-CHMI Display Panel                            MYD-Y6ULX-CHMI Display Panel + MYB-Y6ULX-HMI-4GEXP
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实践研讨会:利用恩智浦最新多媒体应用处理器 i.MX 8M Mini 快速推进您的产品开发 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 从 i.MX 8M Mini EVK 开始实践,我们将介绍开箱即用的支持,包括软件、工具、硬件设计指南和演示软件。参加者在完成本课程后应该能够自信地使用 i.MX 8M Mini 开始自己的设计。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 从 i.MX 8M Mini EVK 开始实践,我们将介绍开箱即用的支持,包括软件、工具、硬件设计指南和演示软件。参加者在完成本课程后应该能够自信地使用 i.MX 8M Mini 开始自己的设计。 i.MX 应用处理器
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基于模型的设计工具箱电机控制示例 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 该视频显示: - 采用 S32K144 rev2.0 的电机控制典型设置评估板; - 用于 BLDC 电机控制的 Simulink 模型; - 如何设置 Simulink 为 S32K144 rev2.0 生成 ANSI C 代码单片机; - 快速浏览基于模型的设计工具箱; - 快速浏览 FreeMASTER 数据可视化工具; - 使用 DevKit S32K144EVB 和 MotorGD 屏蔽运行的电机控制示例; (在 “我的视频” 中查看) 视频库 回复:基于模型的设计工具箱电机控制示例 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 非常感谢! 回复:基于模型的设计工具箱电机控制示例 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 谢谢分享,但是 C 代码在哪里?
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1.1 S32V overview The S32V234 is our 2nd generation vision processor family designed to support computation intensive applications for image processing and offers an ISP, powerful 3D GPU, dual APEX-2 vision accelerators, security and supports SafeAssure™. S32V234 is suited for ADAS, NCAP front camera, object detection and recognition, surround view, machine learning and sensor fusion applications. S32V234 is engineered for automotive-grade reliability, functional safety and security measures to support vehicle and industrial automation. S32V234 has a complete enablement platform supported by S32 Design Studio IDE for Vision which includes a compiler, debugger, Vision SDK, Linux BSP and graph tools. Video Link : 8296 The target applications for S32V234 are: Automotive Sensor Fusion Systems Automotive Vision Systems Front View Camera Intelligent Roadside Unit Smart  Rear-View Camera Surround View & Sense Park Assist System Surround View Park Assist System NEXT TOPIC
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LPCキー feature_SPIFI <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> LPC機能SPIFI 添付のドキュメントは、LPC MCUシリアルSPIFI機能の紹介とアプリケーションです トピック • SPIFIの紹介 • SPIFIパフォーマンス • SPIFIデバッグ • SPIFI ライブラリ • SPIFI フラッシュ コンテンツ保護の概要 日時:LPCキー feature_SPIFI <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 興味深い情報ですが、内部フラッシュとのパフォーマンスの比較もありますか。これはあなたのプレゼンテーションには欠けていると思います。 それについてコメントしていただけますか? ありがとうございます
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HMB-N1937 推出基于 Android 的互联设备 Brillio 操作系统 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Brillo 是基于Android的轻量级操作系统, 适用于小型联网设备,开放、可扩展且安全。 Brillo将Android平台扩展至您所有的联网设备, 使这些设备可以轻松安装并与其他设备和您的智能手机无缝协作。 它与谷歌'Weave'通信API配套提供,可以在Brillo设备之间轻松实现通信和交换,并在云中存储数据。 在本次课程中,我们将向您介绍Brillo以及恩智浦如何与谷歌合作,将Brillo扩展至i.MX 6UltraLite处理器和其他平台。 观看视频演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Brillo 是基于Android的轻量级操作系统, 适用于小型联网设备,开放、可扩展且安全。 Brillo将Android平台扩展至您所有的联网设备, 使这些设备可以轻松安装并与其他设备和您的智能手机无缝协作。 它与谷歌'Weave'通信API配套提供,可以在Brillo设备之间轻松实现通信和交换,并在云中存储数据。 在本次课程中,我们将向您介绍Brillo以及恩智浦如何与谷歌合作,将Brillo扩展至i.MX 6UltraLite处理器和其他平台。 观看视频演示 智能家居和智能建筑
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DES-N1846 - 关于 DDR4 你需要知道的一切 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 了解 DDR4 的基础知识以及如何在 QorIQ 设备上配置 DDR4 控制器。 观看视频演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 了解 DDR4 的基础知识以及如何在 QorIQ 设备上配置 DDR4 控制器。 观看视频演示 设计 | 软件与服务
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KDS での KSDK と Processor Expert のサポートを使用した新しい USB プロジェクトの作成 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> KSDKファンの皆さん、こんにちは。   ご存知かもしれませんが、KSDKはKinetisマイクロコントローラの包括的なソフトウェアサポートを提供し、アプリケーション開発を加速します。ハードウェアabstraccionレイヤーとペリフェラルドライバーを提供するだけでなく、Processor Expertにも対応できます。   以下は、KSDK と Processor Expert のサポートを使用して新しいプロジェクトを作成する方法の例です。   これは、KSDK ドライバーまたはプロセッサ エキスパート サポートを使用してアプリケーション コードを追加する準備ができている簡単な USB HID の例を示しています。   これがお役に立てば幸いです。   よろしくお願いします。   アイザック・アビラ 全般 Re:KDSでKSDKとProcessor Expertのサポートを使用して新しいUSBプロジェクトを作成する <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> この関数「USB_Class_HID_Send_Data()」はどのように機能しますか? この関数を使用したときに、Aなどの単語を送信し続けます。 AではなくAだけを送信する方法。 Re:KDSでKSDKとProcessor Expertのサポートを使用して新しいUSBプロジェクトを作成する <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 私はこのガイドが示しているものと似たようなことを達成しようとしていますが、あまり役に立たないほど十分に異なります。TWR-K21F120M を使用しており、OS なしで Processor Expert コンポーネントを使用して USB MSD を実装する必要があります。これを達成するために私に示せるリソースはありますか?
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APF-ACC-T0983 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> このセッションでは、KEAシリーズとKFAシリーズを含む、新しいKinetisマイクロコントローラの自動車製品ファミリの概要を説明します。Kinetisマイクロコントローラの自動車ファミリは、車載市場向けの32ビットARM® Cortex-M0®+/M4ベースのAEC Q100認定マイクロコントローラの、拡張性に優れたポートフォリオです。このファミリは、コスト重視のアプリケーション向けに最適化されており、非常に低い消費電力でピン数の少ないオプションを提供します。2.7-5.5V電源を備え、優れたEMC/ESD堅牢性に重点を置いたKinetisマイクロコントローラ・オート・シリーズ・デバイスは、ボディ・アプリケーション、インフォテインメント接続モジュール、パーキング・アシスタンス、セーフティ・コンパニオン・チップ、汎用センサ・ノードなど、幅広いアプリケーションに適しています。Kinetisマイクロコントローラのオート・ファミリのすべての製品は、同様のペリフェラルを共有しており、さまざまなサードパーティ製およびフリースケールのHW/SW開発ツールによってサポートされています。開発者は、Kinetisマイクロコントローラのオート・ファミリを使用して、設計を迅速に開始できます。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> このセッションでは、KEAシリーズとKFAシリーズを含む、新しいKinetisマイクロコントローラの自動車製品ファミリの概要を説明します。Kinetisマイクロコントローラの自動車ファミリは、車載市場向けの32ビットARM® Cortex-M0®+/M4ベースのAEC Q100認定マイクロコントローラの、拡張性に優れたポートフォリオです。このファミリは、コスト重視のアプリケーション向けに最適化されており、非常に低い消費電力でピン数の少ないオプションを提供します。2.7-5.5V電源を備え、優れたEMC/ESD堅牢性に重点を置いたKinetisマイクロコントローラ・オート・シリーズ・デバイスは、ボディ・アプリケーション、インフォテインメント接続モジュール、パーキング・アシスタンス、セーフティ・コンパニオン・チップ、汎用センサ・ノードなど、幅広いアプリケーションに適しています。Kinetisマイクロコントローラのオート・ファミリのすべての製品は、同様のペリフェラルを共有しており、さまざまなサードパーティ製およびフリースケールのHW/SW開発ツールによってサポートされています。開発者は、Kinetisマイクロコントローラのオート・ファミリを使用して、設計を迅速に開始できます。
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FTF-INS-F1134 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 备受期待的 i.MX 7 系列专为物联网应用、销售点产品和许多其他成本敏感的嵌入式应用而设计。本课程将揭示下一代 i.MX 系列的更多细节,重点关注安全性、处理能力和低功耗技术。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 备受期待的 i.MX 7 系列专为物联网应用、销售点产品和许多其他成本敏感的嵌入式应用而设计。本课程将揭示下一代 i.MX 系列的更多细节,重点关注安全性、处理能力和低功耗技术。
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Multilink Rev C の問題 - MCU V10.6 Update3 のインストール後および MCF V7.2 の CW 後に動作しない <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> MCU V10.6 Update3 以降、Multilink Rev C が動作しない Multilink Rev C が MCF V7.2 の CW で動作しない                                       A- 説明   この問題は、Mulitilink Universal Rev Cでのみ発生します。 MCU V10.6 Update 3 は Mulilink Universal Rev B で正常に動作しています。   デフォルトの MCU v10.6 では、S12Z ボード上の Multilink Universal Rev C は正常に動作しています。 MCU V10.6 Update 3 (+最新のパッチ/アップデート - 5月末) をインストールした後、デバッガを初めて起動すると、CodeWarrior は Multilink Universal インターフェイス用の新しいファームウェアが利用可能であることを検出します。 ファームウェアは自動的に更新されます。   ただし、新しいファームウェアには問題があります: Usbmlfsufbdmens.0930 場合によっては、オンボードでアプリケーションをデバッグできないことがあります。       B- ソリューション   MCU 10.6 update 3 には、ファームウェア Usbmlfsufbdmens.0930 が含まれています ただし、このファームウェアにはいくつかの問題があります。 P&Eは、9.30から9.35の間にS12関連の多くの問題に対処した。 最新バージョン(Usbmlfsufbdmens.0935)へのアップデートを推奨します。このデバッグモジュールでデバイスをターゲットにする場合。   最新バージョンは、P&EのWebサイトからダウンロードできます。                 http://www.pemicro.com/downloads/download_file.cfm?download_id=346   添付されているアップデートも見つかります。   この問題はCodeWarrior MCU V10.6.4で解決されました      新しい CodeWarrior for MCU v10.6.4 リリース     C- その他のケース – Classic IDE MCF V7.2   構成: Coldfire V7.2 の CW と ColdFire 54452 Ext FLASH のマルチリンク ユニバーサル Rev C。 アプリケーションをボードにロードしようとすると、「フラッシュIDの取得に失敗しました」というエラーが表示されます。 最後のP&Eファームウェアをインストールした後、問題も解決しました。   問題を回避するために、P&Eのフィードバックに従って、P&EのWebサイトからダウンロードできる最新のP&Eアップデート を常に インストールすることをお勧めします。                 http://www.pemicro.com/downloads/download_file.cfm?download_id=346 全般
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EUF-ACC-T1574 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> フリースケールは、Kinetisマイクロコントローラを使用して自動車開発を容易にします。車載用Kinetis EAシリーズ・マイクロコントローラは、シンプルなツール、広範な開発環境、および-40°Cから125°Cの温度範囲にわたる車載グレードの認定により、市場投入までの時間を短縮します。フリースケール・オートモーティブのポートフォリオ (S32、S12、MagniV、Kinetis EA) とエコシステム <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> フリースケールは、Kinetisマイクロコントローラを使用して自動車開発を容易にします。車載用Kinetis EAシリーズ・マイクロコントローラは、シンプルなツール、広範な開発環境、および-40°Cから125°Cの温度範囲にわたる車載グレードの認定により、市場投入までの時間を短縮します。フリースケール・オートモーティブのポートフォリオ (S32、S12、MagniV、Kinetis EA) とエコシステム
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Porting Micro-ROS on Frdm-MCXN947 1. Overview The MCXN947 chip is a highly integrated microcontroller featuring robust processing capabilities, extensive peripheral support, and advanced security features. It is suitable for a wide range of complex applications. The NXP FRDM-MCXN947 board is a low-cost design and evaluation board based on the MCXN947 device. NXP provides a comprehensive set of tools and software support for the MCXN947, including hardware evaluation boards, an integrated development environment (IDE), example applications, and drivers. Micro-ROS is an embedded version of ROS 2 specifically designed to operate on embedded systems, enabling real-time control and communication for robotics and embedded devices. It extends the powerful features of ROS 2 to resource-constrained embedded platforms like microcontrollers and embedded systems. The introduction of Micro-ROS facilitates tighter integration between embedded systems and the ROS 2 ecosystem, enabling advanced robotic automation and control. This document explores the process of porting Micro-ROS to the MCXN947 board.‌ Harry_Zhang_0-1733195688906.png This document explores the process of porting Micro-ROS to the MCXN947 board. Hardware Environment:     FRDM-MCXN947 Software Environment:     Ubuntu 22.04     IDE:MCUXpresso IDE v11.9.0     SDK:SDK Builder | MCUXpresso SDK Builder (nxp.com) 2. ROS 2 Architecture Before delving into the Micro-ROS porting process, let us briefly introduce the new ROS 2 architecture. This is necessary because Micro-ROS heavily leverages ROS 2's abstraction layer source code in its design and implementation. Compared to its predecessor ROS 1, ROS 2 employs a distinct communication mechanism, most notably adopting the DDS (Data Distribution Service) protocol for communication and node discovery. ROS 1, by contrast, relies on the XML-RPC protocol and requires the master node to launch before other nodes can join. ROS 1's limited support for embedded devices stems from the XML-RPC mechanism, which introduces significant software dependencies in these environments. To address this issue, projects like rosserial developed lightweight communication protocols tailored for MCU-to-PC master node communication. ROS 2, on the other hand, integrates the industry-proven DDS protocol, which has demonstrated its stability in domains like military, aerospace, and financial systems. It is important to note that DDS is a standard protocol with various implementations, such as Cyclone DDS (Eclipse), Fast DDS, and Micro XRCE-DDS (eProsima). To ensure that upper-layer ROS 2 code remains unaffected by different DDS implementations, ROS 2 defines a series of abstract layer interfaces, such as RCL (ROS Client Library) and RMW (ROS Middleware). These DDS implementations provide a uniform RMW interface. On top of RMW is the RCL, implemented in C, which supports various programming languages, including C++, Python, and Java. Thus, successfully porting ROS 2 to a real-time operating system (RTOS) hinges on the RTOS supporting a specific DDS implementation and its corresponding RMW interface. Only then can upper-layer RCL and ROS application code run without modification. ROS 2 comprises RCL (ROS Client Library), RMW (ROS Middleware Interface), and DDS (Data Distribution Service). Porting ROS 2 to a new platform essentially involves creating a compatible RMW-DDS combination, leaving the RCL layer unaltered. Micro-ROS provides such an RMW-DDS combination. Specifically, Micro-ROS employs Micro XRCE-DDS (a DDS standard designed for extremely resource-constrained environments) with a corresponding RMW implementation. This enables Micro-ROS to be compatible with ROS 2's architecture while efficiently running on resource-limited embedded devices. Thus, porting Micro-ROS to different hardware platforms fundamentally involves interfacing communication protocols like UART (Universal Asynchronous Receiver-Transmitter) and UDP (User Datagram Protocol) with the Micro-ROS RMW-DDS combination. This process ensures effective communication between Micro-ROS and other nodes or external systems while maintaining the lightweight and efficient characteristics suitable for embedded devices. Harry_Zhang_1-1733196001201.png From the above introduction, we can see that MicroROS transplantation mainly has two parts: Connect UART/UDP communication and clock to implement the 5 functions in default_transport.cpp. Folder DDS+RMW+RCL generates libmicroros.a static library. 3. Micro-ROS Static Library Toolchain and Environment Configuration 3.1 Micro-ROS Static Library Toolchain and Environment Configuration First, install ROS 2 on Ubuntu 22.04 LTS and run the following commands: sudo apt update&&sudo apt install locales sudo locale-gen en_US en_US.UTF-8 sudo update-locale LC_ALL=en_US.UTF-8 LANG=en_US.UTF-8 export LANG=en_US.UTF-8 sudo apt update && sudo apt install curl gnupg lsb-release sudo curl -sSL https://raw.githubusercontent.com/ros/rosdistro/master/ros.key -o /usr/share/keyrings/ros-archive-keyring.gpg (1) sudo apt update: Updates the system’s package list to fetch the latest package information. (2) sudo apt install locales: Installs the locales package, which provides tools for managing and configuring localization. (3) sudo locale-gen en_US en_US.UTF-8: Generates the localization settings for US English, including UTF-8 encoding. (4) sudo update-locale LC_ALL=en_US.UTF-8 LANG=en_US.UTF-8: Updates the system’s localization settings to use UTF-8 encoding for US English. (5) export LANG=en_US.UTF-8: Sets the current terminal’s language encoding to US English UTF-8. (6) sudo apt install curl gnupg lsb-release: Installs additional tools (curl for network requests, gnupg for encryption, lsb-release for distribution information). (7) sudo curl: Downloads the ROS public key for verifying package integrity. 3.2 Installing ROS on Ubuntu Set up and build the Micro-ROS development environment with the following commands: sudo apt update && sudo apt upgrade && sudo apt install ros-humble-desktop source /opt/ros/humble/setup.bash && echo “source /opt/ros/humble/setup.bash” >>~/.bashrc source /opt/ros/$ROS_DISTRO/setup.bash mkdir uros_ws && cd uros_ws git clone -b iron https://github.com/micro-ROS/micro_ros_setup.git src/micro_ros_setup rosdep update && rosdep install --from-paths src --ignore-src -y colcon build source install/local_setup.bash ros2 run micro_ros_setup create_firmware_ws.sh generate_lib (1) Update the software and install ROS (Robot Operating System) (2) Set and save the configuration of the ROS environment. (3) These two commands create a new directory uros_ws (workspace), and then switch to this directory. (4) Clone the project named micro_ros_setup from the GitHub repository and place it in the src directory of the workspace. (5) These two commands are used to install the dependencies required by the project. (6) This command uses the colcon build system to compile and install the project. Colcon is a general-purpose build tool suitable for multiple programming languages and platforms. (7) create_firmware_ws.sh: This is the name of the executable file to be run. It might be a script that creates a firmware workspace. The purpose of this command is to run the create_firmware_ws.sh script in the micro_ros_setup package and pass the parameter generate_lib to generate a firmware workspace containing the Micro-ROS library. This step requires downloading a large amount of source code from github. After failure, the next generation will prompt that the firmware already exists and you need to rm this folder. If the following picture appears, it proves that the code download is successful. Harry_Zhang_2-1733196354824.png 4. Generating the Micro-ROS Static Library If the toolchain and environment setup are successful, you should have five folders in your workspace: build, firmware, install, log, and src. Harry_Zhang_3-1733196629781.png The firmware folder contains the Micro-ROS workspace. 4.1 Configure the toolchain.cmake file according to the target processor Enter the fireware directory. The colcon.meta and toolchain.cmake inside are the configuration files we need to specify to generate the static library. Colcon.meta describes the configuration of our micro-ros, and toolchain.cmake describes the microcontroller platform. We can open MCUXpresso to find MCXN947 related configuration. and create toolchain.cmake. set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_CROSSCOMPILING 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) # SET HERE THE PATH TO YOUR C99 AND C++ COMPILERS set(PIX /opt/gcc-arm-none-eabi-10.3-2021.10/bin) set(CMAKE_C_COMPILER ${PIX}/arm-none-eabi-gcc) set(CMAKE_CXX_COMPILER ${PIX}/arm-none-eabi-g++) set(CMAKE_C_COMPILER_WORKS 1 CACHE INTERNAL "") set(CMAKE_CXX_COMPILER_WORKS 1 CACHE INTERNAL "") # SET HERE YOUR BUILDING FLAGS set(FLAGS "-O2 -ffunction-sections -fdata-sections -fno-exceptions -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard -nostdlib -mthumb --param max-inline-insns-single=500 -D'RCUTILS_LOG_MIN_SEVERITY=RCUTILS_LOG_MIN_SEVERITY_NONE'" CACHE STRING "" FORCE) set(CMAKE_C_FLAGS_INIT "-std=c11 ${FLAGS} -DCLOCK_MONOTONIC=0 -D'__attribute__(x)='" CACHE STRING "" FORCE) set(CMAKE_CXX_FLAGS_INIT "-std=c++11 ${FLAGS} -fno-rtti -DCLOCK_MONOTONIC=0 -D'__attribute__(x)='" CACHE STRING "" FORCE) set(__BIG_ENDIAN__ 0) The above is how cmake is written. Among them, "-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard": These options specify the architecture and floating point unit characteristics of the target processor. We can view the architecture and floating point unit characteristics of the MCXN947's target processor. Harry_Zhang_4-1733196734969.png We can open MCUXpresso IDE, open a MCXN947 project, and check mcpu=cortex-m33 -mfpu=fpv5-sp-d16 mfloat-abi=hard in All options in settings->MCU Linker. Therefore, the MCXN947 series is an M33 core. We need to change -mcpu=cortex-m7 to -mcpu=cortex-m33, and basically no other changes are needed. From this we can also see that a series of static libraries produced should be universal! 4.2 Configure the colcon.meta file according to Micro-ROS requirements The other file created sets the Micro-ROS library configurations. To set the transport layer type, here we want a custom transport layer, the configuration “-DUCLIENT_PROFILE_CUSTOM_TRANSPORT=ON” is set to “ON” and the configuration “-DRMW_UXRCE_TRANSPORT=custom” is set to “custom”. The other interesting settings are under the “rmw_microxrcedds” section. Here we can set the maximum number of nodes (1), publisher (5), subscribers (5), services (1) and clients (1) that should be supported, as well as the maximum message history (4) used for a reliable QoC mode. A more detailed description of all settings under this section, can be found in the eProsima Micro XRCE-DDS GitHub. An example configuration, the one I used, is shown below: touch colcon.meta { "names": { "tracetools": { "cmake-args": [ "-DTRACETOOLS_DISABLED=ON", "-DTRACETOOLS_STATUS_CHECKING_TOOL=OFF" ] }, "rosidl_typesupport": { "cmake-args": [ "-DROSIDL_TYPESUPPORT_SINGLE_TYPESUPPORT=ON" ] }, "rcl": { "cmake-args": [ "-DBUILD_TESTING=OFF", "-DRCL_COMMAND_LINE_ENABLED=OFF", "-DRCL_LOGGING_ENABLED=OFF" ] }, "rcutils": { "cmake-args": [ "-DENABLE_TESTING=OFF", "-DRCUTILS_NO_FILESYSTEM=ON", "-DRCUTILS_NO_THREAD_SUPPORT=ON", "-DRCUTILS_NO_64_ATOMIC=ON", "-DRCUTILS_AVOID_DYNAMIC_ALLOCATION=ON" ] }, "microxrcedds_client": { "cmake-args": [ "-DUCLIENT_PIC=OFF", "-DUCLIENT_PROFILE_UDP=OFF", "-DUCLIENT_PROFILE_TCP=OFF", "-DUCLIENT_PROFILE_DISCOVERY=OFF", "-DUCLIENT_PROFILE_SERIAL=OFF", "-UCLIENT_PROFILE_STREAM_FRAMING=ON", "-DUCLIENT_PROFILE_CUSTOM_TRANSPORT=ON", "-DUCLIENT_PROFILE_SHARED_MEMORY=ON", "-DUCLIENT_SHARED_MEMORY_MAX_ENTITIES=20" ] }, "rmw_microxrcedds": { "cmake-args": [ "-DRMW_UXRCE_MAX_NODES=5", "-DRMW_UXRCE_MAX_PUBLISHERS=6", "-DRMW_UXRCE_MAX_SUBSCRIPTIONS=4", "-DRMW_UXRCE_MAX_SERVICES=6", "-DRMW_UXRCE_MAX_CLIENTS=1", "-DRMW_UXRCE_MAX_HISTORY=4", "-DRMW_UXRCE_TRANSPORT=custom" ] } } } 4.3 Building the Micro-ROS Static Library Run the following commands: source install/local_setup.bash ros2 run micro_ros_setup build_firmware.sh $(pwd)/firmware/toolchain.cmake $(pwd)/firmware/colcon.meta If the static library is successfully generated, you will see libmicroros.a in the firmware/build file. Harry_Zhang_5-1733197118503.png 5. Integrating and Testing the Static Library Locally 5.1 Adding the Generated Micro-ros Static Library to the Local Project Harry_Zhang_6-1733197148946.png (1) Create a folder named bsp_include. Harry_Zhang_7-1733197224655.png (2) Add all files from the include directory into your project under bsp_include. (3) Add all paths in the include file to the include path. Harry_Zhang_8-1733197237901.png (4) Add the generated libmicroros.a static library to the project, for example, add it to bsp_include. Harry_Zhang_9-1733197313200.png (5) Add the libmicrorots.a static library and name path to Libraries(-l) and Library search path(-L). 5.2  Implementing the Serial Communication Interface Functions To port Micro-ROS to an MCU, you must provide transport layer functionalities for reading and writing through the communication interface. The required transport functions are defined as follows: rmw_ret_t rmw_uros_set_custom_transport( bool framing, void * args, open_custom_func open_cb, close_custom_func close_cb, write_custom_func write_cb, read_custom_func read_cb); ​ Through this structure, we can see that the communication interface function group mainly includes open, close, write, and read. open: This function is responsible for initializing (opening) peripheral devices used by the transport layer. This function is empty if the peripheral is initialized elsewhere and before the Micro-ROS function is called. close: This function is responsible for deinitializing (turning off) peripherals used by the transport layer. Because there is no need to deinitialize the function. This function is also empty. write: This function is responsible for writing data (bytes) on the peripheral device. The number of bytes to be written and the bytes themselves are given as parameters "len" and "buf" respectively. read: This function is responsible for reading data (bytes) from the peripheral device. The number of bytes to read is specified in the function parameter "len" and bytes should be returned via the function parameter "buf". bool transport_close(struct uxrCustomTransport * transport) { return true; } bool transport_open(struct uxrCustomTransport * transport) { return true; } size_t transport_write(struct uxrCustomTransport* transport, const uint8_t * buf, size_t len, uint8_t * err) { LPUART_WriteBlocking(DEMO_LPUART, buf, len); return len; } size_t transport_read(struct uxrCustomTransport* transport, uint8_t* buf, size_t len, int timeout, uint8_t* err) { LPUART_ReadBlocking(DEMO_LPUART, buf, len); return len; } Additionally, you need to implement a function to provide the system’s clock time. This clock does not have to provide real-time or world time, but rather elapsed time since startup or similar. For example: int clock_gettime(clock_t unused, struct timespec *tp) { (void)unused; IRTC_GetDatetime(RTC, &datetimeGet); tp->tv_sec = datetimeGet.second; tp->tv_nsec = (long)(datetimeGet.second) * 1000000; return 0; } 5.3 Testing To run Micro-ROS in practice, the setup includes two components: 1. A client running on the MCU. 2. An agent running on the host PC. Basic Micro-ROS Client (MCU) Below are the minimal steps and code needed to create and run a Micro-ROS client. These instructions are based on the Micro-ROS documentation for node creation. //Required global variables rcl_allocator_t allocator; rclc_support_t support; rcl_node_t node; rclc_executor_t executor; rmw_ret_t error; //Set Communication functions rmw_uros_set_custom_transport( true, NULL, rtt_transport_open, rtt_transport_close, rtt_transport_write, rtt_transport_read ); //Set Allocation functions (Optional) rcl_allocator_t allocator = rcutils_get_zero_initialized_allocator(); allocator.allocate = rtt_allocate; allocator.deallocate = rtt_deallocate; allocator.reallocate = rtt_reallocate; allocator.zero_allocate = rtt_zero_allocate; (void)!rcutils_set_default_allocator(&allocator); //Get allocator allocator = rcl_get_default_allocator(); //Create init_options error = rclc_support_init(&support, 0, NULL, &allocator); //Create node error = rclc_node_init_default(&node, "uROS_Terminal", "", &support); //Create executor error = rclc_executor_init(&executor, &support.context, 1, &allocator); //Call the executor periodically e.g. in the while(1) loop or a thread: while(1) { error = rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)); } ​ Setting up the Micro-ROS Agent (PC) The agent establishes an interface between the Micro-ROS client on the MCU and ROS 2 on the host PC. To set up the agent: # Go to the Micro-ROS workspace folder cd microros_ws # Source ROS 2 source /opt/ros/humble/setup.bash # Source local packages source install/local_setup.bash # Create Agent ros2 run micro_ros_setup create_agent_ws.sh # Build Agent ros2 run micro_ros_setup build_agent.sh # Possible ROS Update sudo rosdep init rosdep update  After successfully building the Micro ROS agent, the following bash command starts/runs the agent: # Go to the Micro-ROS workspace folder cd microros_ws # Source ROS 2 source /opt/ros/humble/setup.bash # Source local packages source install/local_setup.bash # Run Agent (serial connection) ros2 run micro_ros_agent micro_ros_agent serial --dev /dev/ttyACM0 Of these bash commands, the last one is the one that actually starts the Micro-ROS agent. It takes several parameters, the first is the type of connection to use, in this case a serial connection. Then there are two parameters that only apply to serial connections: "--dev/ttyACM0", which sets the serial interface to be used (to list all serial interfaces in linux, you can use the following bash command: "dmesg | grep tty".) After starting the Micro-ROS agent, the MCU can connect to the host PC via the serial interface and reset to establish a new connection. If the following Micro-ROS agent terminal output: Harry_Zhang_10-1733198156377.png This proves the success of transplanting Micro-Ros On Frdm-mcxm947.
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示例 S32K146-Set_whole_FlexRAM-as_RAM v0_0 S32DS.ARM.2.2 ******************************************************************************** * 文件:main.c * 所有者:David Tosenovjan * 版本:0.0 * 日期:2021年3月12日 * 分类:一般商业信息 ******************************************************************************** * 详细说明: * 示例代码将整个 4kB FlexRAM 区域配置为 SRAM 使用。 *默认情况下或批量擦除后,S32K1设备只有地址范围 * 0x1400_0000-0x1400_0DFF (3.5kB) 可供 SRAM 使用。 * 要启用剩余的 0.5kB,需要执行程序分区命令 *(使用示例中所示的设置),但只能使用空白的新 * 设备(或之前已批量擦除)。设置地址范围 * 0x1400_0000-0x1400_0FFF 用于 SRAM。 * ---------------------------------------------------------------------------------------------- *测试硬件:S32K146EVB-Q144 * 微控制器:PS32K146UAVLQ 0N73V QAC1735D * Fsys: 默认 * 调试器:Lauterbach Trace32、OpenSDA * 目标:Debug_RAM * 终端:无 * EVB连接:默认 ********************************************************************************
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i.MX6DQ 寄存器编程辅助工具 重要提示:如果您有任何疑问或想要报告有关 DDR 工具或支持文档的任何问题,请在i.MX 社区中创建支持工单。请注意,任何私人消息或直接邮件不会被监控,也不会收到回复。 这些是与MX6DQ SoC中MMDC DDR3和LPDDR2初始化相关的寄存器的详细编程辅助工具。最后一张表格格式化寄存器设置以便与ARM RealView ICE一起使用。它还可以与DDR压力测试的Windows可执行文件一起使用。此编程辅助工具用于NXP内部的电路板。 i.MX6 双核 i.MX6 四核
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Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Board: Custom S32G399A based module, derived from S32G-VNP-RDB3. PFE_MAC1 connected via RGMII (PE_02–PE_13) to an NXP SJA1110A switch port 2, configured as the DSA CPU port (in-tree sja1105 driver, kernel 6.x BSP43.0). Topology: - PFE_MAC0: SGMII via SerDes1 lane1, Mode 1 - PFE_MAC1: RGMII to SJA1110A port 2 (DSA CPU port) — the port in question - PFE_MAC2: SGMII via SerDes0 lane1 The S32G MACs are configured as follows: +---------+--------------+------------------+ |                    | LANE 0               | LANE 1                        | +---------+--------------+------------------+ | SERDES0    | GMAC (SGMII) | PFE_MAC2 (SGMII)  | | SERDES1      | NOT USED        | PFE_MAC0 (SGMII) | +---------+--------------+------------------+ Full U-Boot hwconfig: hwconfig=pcie0:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=both;pcie1:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=0 pfeng_mode=enable,sgmii,rgmii,sgmii DTS for port@2 (switch side): port@2 { reg = <2>; label = "OBC-1"; ethernet = <&pfe_netif1>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; fixed-link { speed = <1000>; full-duplex; }; }; DTS for pfe_netif1 (MAC side): &pfe_netif1 { phy-mode = "rgmii"; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; PFE_MAC1 (pfe1) link state — confirmed up and correctly configured at the Linux/driver level: dmesg at boot: [ 5.264108] pfeng 46000000.pfe: netif name: pfe1 [ 5.274127] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 5.279692] pfeng 46000000.pfe: netif(pfe1) mode: std [ 5.284853] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 6.012884] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 6.019438] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 6.026270] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 6.032374] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 6.040545] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb [ 6.060939] pfeng 46000000.pfe pfe1 (uninitialized): Registered PTP HW clock successfully on EMAC1 [ 6.070441] pfeng 46000000.pfe pfe1: registered [ 6.207482] pfeng 46000000.pfe pfe1: configuring for fixed/rgmii link mode [ 6.214306] pfeng 46000000.pfe pfe1: Set TX clock to 125000000Hz [ 6.220158] pfeng 46000000.pfe pfe1: Link is Up - 1Gbps/Full - flow control off [ 5.257995] pfeng 46000000.pfe: EMAC0 interface mode: 4 [ 5.290707] pfeng 46000000.pfe: EMAC1 interface mode: 9 [ 5.323320] pfeng 46000000.pfe: EMAC2 interface mode: 4 [ 5.354571] pfeng 46000000.pfe: Interface selected: EMAC0: 0x4 EMAC1: 0x9 EMAC2: 0x4 [ 5.382609] pfeng 46000000.pfe: TX clock on EMAC0 for interface sgmii installed [ 5.390050] pfeng 46000000.pfe: RX clock on EMAC0 for interface sgmii installed [ 5.404998] pfeng 46000000.pfe: TX clock on EMAC1 for interface rgmii installed [ 5.419918] pfeng 46000000.pfe: Defer enabling of RX clock on EMAC1 for interface rgmii (ret: -5) [ 5.434235] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed [ 5.448374] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [ 5.667058] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 [ 5.998447] pfeng 46000000.pfe pfe0 (uninitialized): Registered PTP HW clock successfully on EMAC0 [ 6.060939] pfeng 46000000.pfe pfe1 (uninitialized): Registered PTP HW clock successfully on EMAC1 [ 6.130296] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2 [ 6.215040] pfeng 46000000.pfe: RX clock on EMAC1 for interface rgmii installed Live DTB confirms the kernel matches the source DTS: # cat /proc/device-tree/soc/pfe@46000000/ethernet@11/phy-mode rgmii ip a output: 6: pfe1: mtu 1536 qdisc mq state UP group default qlen 1000 link/ether 00:04:9f:be:ef:01 brd ff:ff:ff:ff:ff:ff inet6 fe80::204:9fff:febe:ef01/64 scope link All SJA1110 DSA slave ports correctly enumerated. This confirms the sja1105 DSA driver bound successfully to pfe1 as the CPU port/DSA master and parsed the static config without error. Clock tree: both TX and RX RGMII clocks enabled and attached to the correct consumer: # cat /sys/kernel/debug/clk/clk_summary | grep pfe1 pfe1_tx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_tx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_tx_rgmii 1 1 0 125000000 0 0 50000 Y ethernet@11 tx_rgmii pfe1_rx_rgmii 1 1 0 125000000 0 0 50000 Y ethernet@11 rx_rgmii pfe1_tx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id So pfe1 is UP, LOWER_UP, correctly bound to the SJA1110 as DSA master, running in RGMII mode with both clocks enabled — this rules out pfe1 being down, unbound, or misconfigured at the Linux/driver level. The open question is specifically whether frames actually cross the physical RGMII pins between PFE_MAC1 and SJA1110 port 2. Issue: No traffic appears to cross the RGMII bus between PFE_MAC1 and SJA1110 port 2 in either direction, despite everything on both sides of that bus being independently up: Test 1 — S32G -> switch direction Setup: ip addr add 192.168.1.100/24 dev EPS-100bt1-9 ethtool -S pfe1 | grep '^ p02_' > before tcpdump -i pfe1 -e -nn -c 20 > capture.txt & arping -c 10 -I EPS-100bt1-9 192.168.1.6 ethtool -S pfe1 | grep '^ p02_' > after # arping -c 10 -I EPS-100bt1-9 192.168.1.6 ARPING 192.168.1.6 from 192.168.1.100 EPS-100bt1-9 Sent 10 probes (10 broadcast(s)) Received 0 response(s) $ cat capture.txt tcpdump: verbose output suppressed, use -v[v]... for full protocol decode listening on pfe1, link-type NULL (BSD loopback), snapshot length 262144 bytes 18:08:36.352535 AF Unknown (4294967295), length 64: 0x0000: ffff 0004 9fbe ef01 dadb 0c09 0806 0001 ................ 0x0010: 0800 0604 0001 0004 9fbe ef01 c0a8 0164 ...............d 0x0020: ffff ffff ffff c0a8 0106 0000 0000 0000 ................ 0x0030: 0000 0000 0000 0000 0000 0000 ............ [... 9 more identical ARP frames, all correctly DSA-tagged (dadb 0c09) and well-formed, plus one unrelated IPv6 background frame interleaved ...] # diff before after --- before +++ after @@ -1,4 +1,4 @@ - p02_: 1 + p02_: 0 p02_n_runt: 0 p02_n_soferr: 0 p02_n_alignerr: 0 # grep n_rxfrm before after before: p02_n_rxfrm: 0 after: p02_n_rxfrm: 0 Test 2 — switch -> S32G direction Setup Partner board is a separate SJA1105 switch based board. # ping -c 10 -I t1-6 192.168.1.100 (run on a separate SJA1105/1110-family switch board connected to our port 9 / 100BASE-T1 / EPS-100bt1-9) # diff before after (ethtool -S EPS-100bt1-9) - n_rxfrm: 0 + n_rxfrm: 9 <- port 9 physically received 9 frames from the wire # diff before after - p02_n_txfrm: 0 + p02_n_txfrm: 9 <- switch fabric forwarded all 9 toward the CPU port # tcpdump -i pfe1 -e -nn -c 20 (same window) listening on pfe1, link-type NULL (BSD loopback), snapshot length 262144 bytes [-- nothing captured --] Port 9 received 9 real frames; the fabric forwarded all 9 toward port 2 — but nothing arrived at pfe1. So the SJA1110's own fabric counters show all 9 frames successfully forwarded from port 9 to port 2's egress. But tcpdump -i pfe1 -e -nn on the S32G during this exact test shows NOTHING received. So the DSA/software layer on the S32G side believes it's sending (case 1). The switch's internal fabric believes it's sending toward the CPU port (case 2). Neither side has any confirmation that the other actually received anything across the physical RGMII bus. Every layer adjacent to this bus works individually; the bus itself has no confirmed successful crossing in either direction. What's been ruled out so far: - pfeng_mode / hwconfig (xpcs_mode) — confirmed correct; EMAC1 mode is RGMII (0x9), not SGMII (it was previously misconfigured as SGMII due to xpcs_mode=both on SerDes1 forcing PFE_MAC1's XPCS into SGMII; corrected to xpcs_mode=0 since PFE_MAC0 alone only needs XPCS0) - PFE_MAC1 TX/RX clock enablement — confirmed enabled at the correct rate (125MHz) in clk_summary - DSA tagging and CPU port binding — confirmed working (port netdevs exist, frames get tagged with the correct destination port in the DSA header) - SJA1110 internal fabric/forwarding — confirmed working between two other ports (9 and 2) using real external traffic - BASE-T1 link partner — confirmed passing real frames into the switch (port 9 n_rxfrm increments from genuine wire traffic) What hasn't been ruled out / open questions: - Whether 1000 Mbps RGMII with zero internal delay on both MAC and switch sides (rx/tx-internal-delay-ps=0, plain "rgmii" not "rgmii-id") is compatible without delay added by board trace length — have not yet tried forcing the link down to 100 Mbps as a timing-margin test 1. Is rx/tx-internal-delay-ps=0 on both ends at 1000 Mbps RGMII expected to work, or does this combination typically require delay compensation unless the PCB explicitly accounts for it? 2. Am I missing any other configuration? Happy to share full register dumps, if required. Appreciate any pointers before we probe the PE_02-13 bus with a logic analyzer (limited probe access due to board layout, so it is not so convenient currently. Thanks. Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi @Joey_z @db16122 I am attaching the relevant sections of the schematics here. The connection flow is as follows: We use PE_02 to PE_13 on the S32G3 chip shown in s32g3_pfe_mac1_connections.png for the PFE_MAC1. They go to a board to board connector (shown in Board_to_board_connector.png) that routes these signals to  a different board that has the switch. The switch connections are shown in SJA1110_A.png and SJA1110_B.png. So the connection is PE_xx pins -> board connectors -> switch (SJA1110) Please let me know if you have any questions. I have also raised a support ticket ( #00990408) with the same details.  Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi,pcentauri92 Thank you for your reply. Please provide me with the schematic diagrams related to your ETH, particularly the ones for PFE_MCA1 and SJA1110 sections. You can create an internal support system case. In the information description, @Joey, then provide your schematic diagram information. Refer to this website: https://support.nxp.com BR Joey Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi @Joey_z , Thank you for the response. The module in question here is a custom design that uses the S32G399A chip along with the NXP SJA1110A ethernet switch. We based this design on the S32G-VNP-RDB3 development platform but we made quite a few changes from the base design. The PFE_MAC1 using RGMII is one of those changes.  I am also attaching the dts file override where we change the PFE_MAC1 mode and pinmux here. PFE_MAC1 mode configuration: /* pfe_mdio1 is already disabled in the base config in s32gxxxa-rdb.dtsi */ &pfe_mdio1 { /* occupied by GMAC0 */ status = "disabled"; }; /* * pfe_netif1 = PFE_MAC1 — management port to Switch-A port 2. * Overrides the base "sgmii" stub in s32gxxxa-rdb.dtsi. * Plain "rgmii" (no -id/-txid) since both MAC and switch add zero delay. * No phy-handle: the link partner is the SJA1110A switch, described as a * fixed-link on switch port@2. MDIO is not needed for link management here. */ &pfe_netif1 { phy-mode = "rgmii"; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; PFE_MAC1 pinmux: /* * PFE_MAC1 RGMII pinmux — management port to Switch-A. * * All RX pad SSS values confirmed from S32G3 IOMUX spreadsheet. * TX path: output pads only, no IMCR needed. * RX path: input pads + IMCR registers to route pads into PFE_MAC1. * * Note: PE_07 (TXD3) uses FUNC3, not FUNC2. Similarly PE_08 (RX_CLK) output uses FUNC3; its IMCR (CR#859) uses FUNC2. */ pfe1rgmii_pins: pfe1rgmii_pins { /* TX outputs: PE_02=TX_CLK, PE_03=TX_EN, PE_04=TXD0, PE_05=TXD1, PE_06=TXD2 PE_07 (TXD3) */ pfe1rgmii_grp0 { pinmux = , /* PE_02: PFE_MAC1_TX_CLK */ , /* PE_03: PFE_MAC1_TX_EN */ , /* PE_04: PFE_MAC1_TXD0 */ , /* PE_05: PFE_MAC1_TXD1 */ , /* PE_06: PFE_MAC1_TXD2 */ ; /* PE_07: PFE_MAC1_TXD3 */ output-enable; slew-rate = ; }; /* RX inputs — pads set to FUNC0 (input mode); routing into PFE_MAC1 is handled by the IMCR entries in pfe1rgmii_grp2 below. NXP input mux pattern: pad=FUNC0 + IMCR=FUNC2 */ pfe1rgmii_grp1 { pinmux = , /* PE_08: input */ , /* PE_09: input */ , /* PE_10: input */ , /* PE_11: input */ , /* PE_12: input */ ; /* PE_13: input */ input-enable; slew-rate = ; }; /* IMCR input mux — selects which pad drives each PFE_MAC1 RX signal. CR#866 routes PE_02 (TX_CLK pad) back into PFE_MAC1_TX_CLK_I; required even for RGMII TX because the MAC samples its own TX_CLK internally. All entries at FUNC2 per S32G3 IOMUX spreadsheet. */ pfe1rgmii_grp2 { pinmux = , /* CR#866: PFE_MAC1_TX_CLK_I ← PE_02 */ , /* CR#859: PFE_MAC1_RX_CLK_I ← PE_08 */ , /* CR#865: PFE_MAC1_RXDV_I ← PE_09 */ , /* CR#861: PFE_MAC1_RXD_I[0] ← PE_10 */ , /* CR#862: PFE_MAC1_RXD_I[1] ← PE_11 */ , /* CR#863: PFE_MAC1_RXD_I[2] ← PE_12 */ ; /* CR#864: PFE_MAC1_RXD_I[3] ← PE_13 */ }; }; Please let me know if you need any other information.    Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction any schematics sharing from hardware side for RGMII bus between PFE_MAC1 and SJA1110 port 2 ? Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi,pcentauri92 Thank you for your detail information According to my understanding, there seems to be a problem with the communication when using PFE_MAC1 RGMAII and Port 2 of SJA1110A on your development board. Is that correct? The default configuration of S32G-VNP-RDB3 is that PFE_MAC0/1 operates in SGMII mode and is connected to SJA1110. On your development board, why did you consider using RGMII mode? It is recommended to modify the corresponding software configuration. BR Joey
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需要 S32K342 FOTA 引导加载程序架构指南(基于 UART 的更新) 您好,NXP团队, 我们正在为 S32K342 开发定制的固件空中升级 (FOTA) 解决方案,希望获得有关推荐的闪存架构和启动流程的指导。 MCU详情 设备:S32K342 PFlash:2 MB 银行 0:1 MB 银行 1:1 MB DFlash:128 KB 当前状态 我们使用UART作为固件更新接口。 目前为止,我们已成功做到: 通过 UART 接收固件(.bin 文件)。 将完整的二进制文件存储到闪存中 确认接收到的图像已正确存储。 我们剩下的挑战是实现引导加载程序架构和应用程序切换机制。 我们希望就以下问题获得澄清: 1. 推荐的FOTA Flash布局 对于 S32K342 双镜像 FOTA 实现,推荐的内存布局是什么? 具体来说,我们想知道以下方面的推荐地点: 引导加载程序 应用插槽 A 应用插槽 B 元数据/启动标志 版本信息 CRC 回滚信息 提供一份包含地址的内存映射示例将非常有帮助。 2. 推荐的启动流程 请问有人能解释一下NXP推荐的完整启动顺序吗? 例如: 重置 引导加载程序启动 检查启动标志 选择活动应用程序 验证图像(CRC/签名) 跳转到应用程序 我们希望能得到流程图或对整个流程的解释。 3. 从引导加载程序跳转到应用程序 对于 S32K342,标准的 Cortex-M7 跳转序列是否足够? 例如: 从应用程序基地址读取 MSP 从基数 + 4 读取 Reset_Handler 设置 MSP 更新 VTOR 跳转到 Reset_Handler 在转移控制权之前,是否有任何 S32K342 特有的要求或初始化步骤? 4. 双应用图像 如果应用 A 和应用 B 位于不同的闪存地址: 每个应用程序都应该有自己的链接脚本吗? 或者,NXP 是否有推荐的构建双槽应用的方法? 5. 闪存库的使用 由于 S32K342 有两个 1 MB 的 PFlash 存储区: 推荐的方法是否是: 从 Bank 0 执行引导加载程序 将新固件编程到 Bank 1 中。 验证成功后切换执行 两个 PFlash 存储体之间是否存在读写限制或擦除/编程限制? 6. 元数据存储 理想的存储地点在哪里? 活动图像标志 图像有效性 Firmware version CRC 回滚状态 这些物品应该存放在: 保留 PFlash DFlash 另一个专用的区域? 7. 基于UART的FOTA 由于我们的更新接口是 UART,我们想知道推荐的工作流程。 以下流程是否正确? 个人电脑 │ UART │ 引导加载程序接收 .bin 文件 │ 将固件存储到非活动闪存插槽中 │ 验证CRC │ 更新启动元数据 │ RESET MCU │ 引导加载程序选择新映像 │ 跳转至应用程序 或者恩智浦是否推荐其他方法? 8. AB_SWAP 与自定义引导加载程序 对于 S32K342 的生产 FOTA 而言,HSE AB_SWAP 是否是强制性的? 或者,具有双应用程序插槽的完全自定义引导加载程序也是一种受支持且常用的架构吗? 如果您有任何专门介绍 S32K342 FOTA、UART 固件更新或双映像引导加载程序的应用笔记、参考项目、引导加载程序示例或文档,我们将非常感谢您提供这些参考资料。 感谢您的支持。 S32K3 S32DS-ARM Re: S32K342 FOTA Bootloader Architecture Guidance Required (UART-Based Update) 你好@bavinkumar_02 1.对于 S32K342,AB_SWAP 只有一种可能的设置。参见“3.5.3.2HSE固件参考手册中提供了“AB_SWAP”模式下闪存布局的图示,该手册可从“文档”->“安全文件”下载: https://www.nxp.com/products/S32K3 就您的情况而言,最方便、最常见的布局是: lukaszadrapa_0-1782731189993.png 必须安装 AB_SWAP 版本的 HSE 固件(交换是 HSE 的一项功能,没有 HSE 固件就无法执行此操作)。固件已安装到两个分区,并且如图所示,它占用了两个分区中最后的 176KB。 因为整个数据块都被交换了,所以两个数据块中必须有完全相同的引导加载程序副本。其余部分分配给申请。 代码始终从活动块运行,因此引导加载程序和所有应用程序都是针对活动块中的地址编译的。 当引导加载程序更新应用程序时,它会将应用程序编程为被动阻塞,因此在闪存编程期间不会出现边读边写的问题。应用程序编程完成后,即可触发 HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK HSE 服务。下次RESET后,分区将被交换,引导加载程序将像往常一样跳转到应用程序(跳转到当前活动块中的新应用程序)。 2. 流程取决于应用程序。在现代汽车应用中,简单的基于 CRC 的验证已不再被认为足够。软件的完整性和真实性通常通过安全启动机制来保证。在 S32K3 设备上,这是由硬件网络安全引擎 (HSE) 处理的,它会执行加密验证(例如)。基于签名)在启动过程中自主进行。预计量产汽车系统将利用这些硬件支持的网络安全功能,而不是仅仅依赖 CRC 验证。 我们提供安全启动应用笔记,其中包括演示项目。可从以下网址下载: https://www.nxp.com/products/S32K3 应用笔记请点击此处查看: 文档 -> 安全文件 -> 安全启动应用笔记 v0.1.1.0(AN744511) 相关演示项目可在此处下载: 设计资源 -> 软件 -> 安全文件 -> SecureBootAppNoteDemo (SW745310) 您可以在 HSE 演示示例中找到其他安全启动示例: https://www.nxp.com/webapp/Download?colCode=S32K3_HSE_DemoExamples 三种模式——高级安全启动、基本安全启动和 SHE 安全启动——都有相应的示例。建议启用高级安全启动。 请参阅所有项目中包含的 Readme.md 文件。 3. 是的,这是标准的跳转序列。强烈建议在跳转之前取消初始化引导加载程序初始化的所有资源。 4. 如上所述,代码始终从活动分区执行,因此应用程序始终使用相同的链接器文件。 5. 前面已经讨论过了。 6.这取决于用户。您可以将数据存储在应用程序映像后面,或者存储在数据闪存中。 7. 对于生产汽车用例而言,从数据传输的角度来看,所提出的流程总体上是正确的,但正如前面提到的,我不建议依赖 CRC 作为主要的验证机制。 在汽车应用中,接收到的图像通常会受到加密保护——例如,图像可能会被加密,并且其真实性/完整性会通过数字签名(而不仅仅是 CRC)来验证。 此外,在使用 HSE AB_SWAP 机制时,引导加载程序在 RESET 后不会简单地通过软件元数据选择新映像。新映像被编程到被动分区并成功验证后,应用程序/引导加载程序应调用 HSE 服务 HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK。这将激活被动块,因此RESET后设备将从新激活的分区启动。 8. HSE AB_SWAP 并非严格强制要求,但对于 S32K342 上的量产汽车 FOTA 解决方案,强烈建议使用。 如果没有 HSE 就实施 FOTA,那就意味着您没有利用 S32K3 平台的一个关键优势。这些设备的主要优点是内置支持 HSE 处理的 A/B 交换(分区重映射)。如果没有它,引导加载程序就必须手动管理一切。 具体而言,不包括 HSE AB_SWAP: 你需要自己实现一种机制来选择 A/B 图像。 您需要仔细管理地址空间,并将每个应用程序链接到不同的固定位置。 图像之间的切换不会由硬件自动处理,而完全由您的软件处理。 除了 HSE AB 交换功能之外,没有其他硬件支持的重映射机制可用。 此外,您还将失去与 AB_SWAP 集成的安全启动的简洁性和稳健性。借助 HSE,图像激活、验证和分区之间的切换以更加可控和高效的方式进行处理,符合汽车网络安全要求。 总之,虽然不考虑 HSE 也能做到这一点,但这会大大增加复杂性,并消除该平台的关键优势。 您可以查看“S32K3XX HSE 和 OTA 高级培训 [TR744101]”,该培训文档可从以下链接下载:文档 -> 安全文件: https://www.nxp.com/products/S32K3 问候, 卢卡斯
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