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S32K144 JTAG S32K144信息安全开发,JTAG口如何禁用,禁用后如何恢复? S32K144 Information Security Development: How to Disable the JTAG Port and How to Restore It After Disabling? Re: S32K144 JTAG 谢谢! 现在我可以锁定 JTAG,也可以通过在程序中添加解锁代码来解锁。 我还想问,是否有可能使用 J-Link 等工具直接输入后门密钥来解锁。 Re: S32K144 JTAG 你好@MUXU 禁用 JTAG 接口。您必须在启动代码中操作 Flash 部分。 /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF /* 8 bytes backdoor comparison key */ .long 0xFFFFFFFF /* */ .long 0xFFFFFFFF /* 4 bytes program flash protection bytes */ .long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */ 一旦 MCU 被锁定,可通过 解锁 1.批量擦除(仅在 FSEC[MEEN] 启用时可行) 2. 后门钥匙 更多信息请参见第 36.4.1 节(闪存配置字段说明)和第 36.4.4.1.4 节。(特别是闪存网络安全寄存器 (FSEC))S32K1xx 系列参考手册,修订版 14。 BR、VaneB
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S32K324 seperate core code Hey there, I am investigating how to enable and use the dual-core functionality on the S32K324. There are two questions I can't get my head around: How do I unlock the two cores to act independently of each other? As far as I understand, they start in the lockstep configuration by default, and the DCMROF19[LOCKSTEP_EN] bit tells me if they are in lockstep or decoupled. But that bit is read-only, so where is the point in the configuration where I can decouple? How do the cores know which code flash area to read code from? They need to execute separate functions, so they need different main routines that reside in different code flash areas. Do I have to jump with one core to the specified code area I want to execute code from, or does each core have a specific code start address? thanks in advance Re: S32K324 seperate core code Hello there, this is immensely useful. I am implementing a bootloader and want to enable multicore-support. With this method, it is possible to start an application on Core 1, from Core 0. However, I want the bootloader to be able to "boot" its own application. Is it possible for Core0 to relocate its own vector table and jump to a different application? I assume that one cannot simply write the new VTOR address to MC_ME->PRTN0_CORE0_ADDR and jump to the application at runtime? Regards, Matthew Re: S32K324 seperate core code I know, but I wonder if this is the preffered solution, or is it also configurable somewhere, so later it could be overwritten by accident by some generated code. Re: S32K324 seperate core code You can do the register access @lukaszadrapa described inside the solution. Lets say you have your main inside the M0 core while M1 is still inactive. Tell M1 where it`s own main function runs by calling: voind main_on_core_0() { // some normal code here MC_ME->PRTN0_CORE1_ADDR = (uint32)(&main_function_of_core_1); } Then tell Core 1 to start via the registers access: MC_ME->PRTN0_CORE1_PCONF = MC_ME_PRTN0_CORE1_PCONF_CCE_MASK; MC_ME->PRTN0_CORE1_PUPD = MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK; MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY( 0x5AF0); MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(~0x5AF0); Re: S32K324 seperate core code Hello, Which part of the software shall enable core1?  I'm working on S32k322 and it seems like the only place in the RTD, where these registers are used EnableCore1 routine in startup_cm7.s . However, this part of code is excluded when both MULTIPLE_CORE && MULTIPLE_IMAGE are defined.  How to start M7_1 core then if both cores are supposed to run different applications? Is therea any RTD function which can be called from M7_0 to start second core? Perhaps there is some MCAL config needed  in S32DS which should be used to run 2nd core? Best Regards, Slawomir Re: S32K324 seperate core code Hey @lukaszadrapa  Thanks! That really helped me! Re: S32K324 seperate core code Hi @FelixR  If you have S32K324, it’s already in decoupled mode. This device is considered as dual core. If you have S32K344 then it is in lock step mode by default and it can be configured to work in decoupled mode, so it will become S32K324 in fact. The configuration can be changed by programming of corresponding DCF record in UTEST flash. But as I said, this is not necessary in case of S32K324. When you create new project for S32K324 in S32 Design Studio, two projects are created. One for each core. Each project has own linker file, own startup files etc. It is possible to define which cores will start automatically after reset in Boot Configuration Word in IVT (see “32.5.1 Boot configuration word” in the S32K3 reference manual). Addresses of entry point are defined in IVT. Each core has specific address. A core which is not started in this way can be started by software like this: MC_ME->PRTN0_CORE1_ADDR = (uint32_t)(vtor); //vtor is an address of vector table MC_ME->PRTN0_CORE1_PCONF = MC_ME_PRTN0_CORE1_PCONF_CCE_MASK; MC_ME->PRTN0_CORE1_PUPD = MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK; MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY( 0x5AF0); MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(~0x5AF0); Regards, Lukas
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Software reset error when adapting TJA1120 driver to linux 5.15, error code -110 I'm having problems with software reset when adapting TJA1120 driver (from Linux 6.6) to Linux 5.15 with error code -110, I'm not sure about the cause as well as I don't know how to fix this problem. I refer to this post NXP_C45_TJA11XX Driver Soft Reset Issue, made changes to nxp_c45_soft_reset, but it has no effect, the code is as follows. static int nxp_c45_soft_reset(struct phy_device *phydev) { int ret; ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, DEVICE_CONTROL_RESET); if (ret) return ret; usleep_range(2000, 2050); return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, ret, !(ret & DEVICE_CONTROL_RESET), 20000, 240000, true); }: Error. [ 6.188117] sunxi-mdio 4500048.mdio0. sunxi_mdio_probe() BEGIN [ 6.265731] sunxi-mdio 4500048.mdio0. phy id: 0x001bb031, adr: 0x1b, device: 4500048.mdio0-mii:1b, DRIVER: NXP C45 TJA1120 [ 6.278218] sunxi-mdio 4500048.mdio0. sunxi_mdio_probe() SUCCESS [ 47.166283] NXP C45 TJA1120 4500048.mdio0-mii:1b:. nxp_c45_soft_reset failed: -110
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TJA1120 ドライバを Linux 5.15 に適合させるときにソフトウェア リセット エラーが発生しました (エラー コード -110)。 TJA1120ドライバ(Linux 6.6用)をLinux 5.15に適用する際に、エラーコード-110のソフトウェアリセット問題が発生しました。原因と解決方法がわかりません。 こちらの投稿「NXP_C45_TJA11XX ドライバのソフトリセット問題」を参考に、nxp_c45_soft_reset を修正しましたが、うまくいきませんでした。コードは以下の通りです。 static int nxp_c45_soft_reset(struct phy_device *phydev) { int ret; ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, DEVICE_CONTROL_RESET); if (ret) return ret; usleep_range(2000, 2050); return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, ret, !(ret & DEVICE_CONTROL_RESET), 20000, 240000, true); }: エラーメッセージ: [6.188117] sunxi-mdio 4500048.mdio0:sunxi_mdio_probe() 開始 [6.265731] sunxi-mdio 4500048.mdio0:PHY ID: 0x001bb031、アドレス: 0x1b、デバイス: 4500048.mdio0-mii:1b、ドライバー: NXP C45 TJA1120 [6.278218] sunxi-mdio 4500048.mdio0:sunxi_mdio_probe() 成功 [ 47.166283] NXP C45 TJA1120 4500048.mdio0-mii:1b:nxp_c45_soft_reset 失敗: -110 Re: TJA1120驱动适配linux5.15时出现软件复位错误,错误码-110 こんにちは、 私の知る限り、tja1120 は 5.15 ではサポートされていません。それで、最新の BSP からドライバをバックポートしましたか?動作していますか? よろしくお願いします! よろしくお願いいたします。 Re: TJA1120驱动适配linux5.15时出现软件复位错误,错误码-110 こんにちは@miipoさん、 私がサポートできるのはデバイスの観点からのみです。 エラー コードが phy_write_mmd によって生成されたのか、それとも phy_read_mmd_poll_timeout によって生成されたのかをCAN区別できますか? usleep_range の時間を増やしてみたことはありますか? よろしくお願いいたします。 パベル
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i.MX8MM Kernel crashes on cpuidle Hi, We have a custom i.MX8MM board that crashes after running for some time. This issue occurs with both Linux kernel version 6.1.55 (Yocto 4.2) and Linux kernel version 5.15.71 (Yocto 4.0). The system's default CPU governor is ondemand. We've tested changing the CPU governor to performance, and the system no longer crashes. Do you have any suggestions on how to determine if this is a hardware issue or a kernel issue? And how to solve this issue? Here's the relevant log: [32832.280148] audit: type=1327 audit(1751365801.520:22): proctitle=2F7573722F7362696E2F63726F6E64002D6E [36432.304306] audit: type=1006 audit(1751369401.584:23): pid=3094 uid=0 subj=kernel old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=15 res=1 [36432.317968] audit: type=1300 audit(1751369401.584:23): arch=c00000b7 syscall=64 success=yes exit=1 a0=3 a1=ffffd19f6b10 a2=1 a3=ffffa11e9020 items=0 ppid=265 pid=3094 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=15 comm="crond" exe="/usr/sbin/crond" subj=kernel key=(null) [36432.344959] audit: type=1327 audit(1751369401.584:23): proctitle=2F7573722F7362696E2F63726F6E64002D6E [37877.552323] rcu: INFO: rcu_preempt self-detected stall on CPU [37877.558090] rcu: 2-...!: (1 ticks this GP) idle=d95/0/0x3 softirq=199976/199976 fqs=0 [37877.566100] (t=5958 jiffies g=1820793 q=55) [37877.570369] rcu: rcu_preempt kthread timer wakeup didn't happen for 5957 jiffies! g1820793 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 [37877.581933] rcu: Possible timer handling issue on cpu=0 timer-softirq=157944 [37877.589067] rcu: rcu_preempt kthread starved for 5958 jiffies! g1820793 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=0 [37877.599676] rcu: Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior. [37877.608805] rcu: RCU grace-period kthread stack dump: [37877.613854] task:rcu_preempt state:I stack: 0 pid: 13 ppid: 2 flags:0x00000008 [37877.622211] Call trace: [37877.624655] __switch_to+0x104/0x15c [37877.628241] __schedule+0x2b8/0x710 [37877.631733] schedule+0x88/0x100 [37877.634962] schedule_timeout+0x80/0xf0 [37877.638801] rcu_gp_fqs_loop+0x118/0x2e0 [37877.642726] rcu_gp_kthread+0x104/0x11c [37877.646564] kthread+0x150/0x160 [37877.649795] ret_from_fork+0x10/0x20 [37877.653373] rcu: Stack dump where RCU GP kthread last ran: [37877.658855] Task dump for CPU 0: [37877.662081] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x00000008 [37877.671999] Call trace: [37877.674443] __switch_to+0x104/0x15c [37877.678021] cpuidle_enter_state+0x25c/0x2f0 [37877.682296] cpuidle_enter+0x38/0x50 [37877.685873] do_idle+0x210/0x2a0 [37877.689103] cpu_startup_entry+0x24/0x80 [37877.693027] rest_init+0xe4/0xf4 [37877.696256] arch_call_rest_init+0x10/0x1c [37877.700356] start_kernel+0x610/0x650 [37877.704020] __primary_switched+0xbc/0xc4 [37877.708037] Task dump for CPU 0: [37877.711264] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x00000008 [37877.721181] Call trace: [37877.723625] __switch_to+0x104/0x15c [37877.727203] cpuidle_enter_state+0x25c/0x2f0 [37877.731475] cpuidle_enter+0x38/0x50 [37877.735052] do_idle+0x210/0x2a0 [37877.738281] cpu_startup_entry+0x24/0x80 [37877.742205] rest_init+0xe4/0xf4 [37877.745433] arch_call_rest_init+0x10/0x1c [37877.749531] start_kernel+0x610/0x650 [37877.753194] __primary_switched+0xbc/0xc4 [37877.757206] Task dump for CPU 2: [37877.760431] task:swapper/2 state:R running task stack: 0 pid: 0 ppid: 1 flags:0x00000008 [37877.770349] Call trace: [37877.772792] dump_backtrace+0x0/0x19c [37877.776457] show_stack+0x18/0x70 [37877.779775] sched_show_task+0x154/0x180 [37877.783701] dump_cpu_task+0x44/0x58 [37877.787280] rcu_dump_cpu_stacks+0xe8/0x12c i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, After our tests, we found that the PMIC was causing this issue. Thank you for your support. Re: i.MX8MM Kernel crashes on cpuidle if just one board has this issue, as I mentioned before, you can do the AB test to confirm if this issue is related to the chip, since other boards are fine Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, Thanks for your information. But we don't plan to change the kernel configuration just for one faulty device. We're going to have the distributor help us analyze the problem. Re: i.MX8MM Kernel crashes on cpuidle For optimized performance on the i.MX, you can try to set the stpes as below: CONFIG_ARM_PSCI_CPUIDLE=n in the defconfig files, to avoid cpu enter idle state,  and CONFIG_ARM_PSCI_CPUIDLE is depends on the CONFIG_CPU_FREQ, if couldn't set CONFIG_CPU_FREQ=n, also suggest set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y to the CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y, I think this should be the same as you use "echo performance" command in the user space Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, All of your boards get the same result when you use the command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? => Yes. # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1200000 1600000 What is the frequency when you use ondemand and performance? => The frequency is the same for both ondemand and performance mode. # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq 1600000 Re: i.MX8MM Kernel crashes on cpuidle if all of your boards have the same SW and HW, only one board has issue, you can do the AB test, to check if the chip issue, all of your boards get the same result when you use the command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? and what is the frequency when you use ondemand and performance? I mean when you set ondemand or performance, use the command to check "cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq", are the ondemad and performance share the same cpu frequency?  Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, Thanks for your information. Our kernel has only been modified for peripheral hardware; we haven't made any changes to the CPU frequency or other CPU-related settings. Many of our devices can boot and run normally. Currently, only one device will crash after running for a day. Here is the scaling_available_frequencies result: # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1200000 1600000 Re: i.MX8MM Kernel crashes on cpuidle what do you change in the kernel? the imx8mm default frequency is 1.2Ghz, so you couldn't boot up the board as default, right? what do you get "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? the uboot set the init clock under /arch/arm/mach-imx/imx8m/clock_imx8mm.c for the kernel, set the available cpu frequency in the dtsi file and the cpufreq driver is https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/cpufreq/imx-cpufreq-dt.c if your bsp is the similar as nxp, it seems the system crash under 1.2G, you can refer to the chapter 2.5.3 CPU Frequency Scaling (CPUFREQ) of enclosed file Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, System crashed while CPU governor is ondemand mode. Here is the scaling_available_governors result: # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors conservative ondemand userspace powersave performance schedutil Re: i.MX8MM Kernel crashes on cpuidle  The system's default CPU governor is ondemand. We've tested changing the CPU governor to performance, and the system no longer crashes. > is it your typo?when do you get the system crash? with ondemand or with performance? do you mind giving me the result with command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors" ? Re: i.MX8MM Kernel crashes on cpuidle Hi @adv-johnchang  We are working with a custom i.MX8M Plus DDR4 board that includes 32 MB QSPI NOR flash. Our objective is to boot U-Boot, Linux kernel, device tree, and initramfs (rootfs.img) entirely from QSPI flash, without using SD/eMMC. We are able to successfully boot up to U-Boot (flash.bin) from QSPI flash. -----Flash Layout and Image Sizes---------------- QSPI flash size: 32 MB flash.bin (U-Boot + SPL) ~2.4 MB Image.gz (Kernel) ~15 MB imx8mp-evk.dtb ~85 KB rootfs.img ~12.6 MB ----QSPI Offset Layout---------- flash.bin @ 0x00000000 Image.gz @ 0x0024D000 imx8mp-evk.dtb @ 0x010A6B00 rootfs.img @ 0x010BB800 U-Boot Environment Setup After booting into U-Boot from QSPI, we configure the following environment variables to load the kernel, device tree, and initramfs from flash: sf probe 0 setenv loadaddr 0x40480000 // kernel setenv fdt_addr 0x43000000 //dtb setenv initrd_addr 0x43800000 //rootfs (minimal initramfs) setenv kernel_comp_addr_r 0x50000000 setenv kernel_comp_size 0x04000000 Reading Images from QSPI Flash sf read ${loadaddr} 0x0024D000 0x00E59A6F sf read ${fdt_addr} 0x010A6B00 0x00014BBA sf read ${initrd_addr} 0x010BB800 0x00C04DB0 Boot Command setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} rdinit=/dev booti ${loadaddr} ${initrd_addr} ${fdt_addr} Issue Observed The kernel starts executing but hangs at “Starting kernel …”. Please refer to the attached kernel boot log (kernel_bootlog1). When using the following boot arguments: setenv bootargs setenv bootargs "console=ttymxc1,115200 earlycon root=/dev/ram0 rw rdinit=/sbin/init loglevel=8" The kernel progresses further but hangs midway during boot. Please refer to the attached kernel boot log (kernel_bootlog2). Attached the kernel DTS and kernel defconfig for reference. Kindly let us know if any modifications are required. Also getting same error like you Unable to handle kernel paging request at virtual address. can you please give any suggistions to resolve it and successful kernel boot.  Questions: 1. Are there any recommended changes required in the kernel DTS for booting initramfs entirely from QSPI on a custom i.MX8M Plus DDR4 board? 2. Are there any additional boot arguments recommended by NXP for initramfs-based boot on i.MX8MP from QSPI flash? 3. What could be the possible reason for the kernel not booting correctly? We followed the same procedure that works successfully on the i.MX8MP LPDDR4  EVK, where the kernel and root filesystem boot properly from QSPI flash. The only differences in our setup are the flash.bin and device tree, which were modified according to the DDR configuration of our custom board. thank you.
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i.MX8MM Kernel crashes on cpuidle Hi, We have a custom i.MX8MM board that crashes after running for some time. This issue occurs with both Linux kernel version 6.1.55 (Yocto 4.2) and Linux kernel version 5.15.71 (Yocto 4.0). The system's default CPU governor is ondemand. We've tested changing the CPU governor to performance, and the system no longer crashes. Do you have any suggestions on how to determine if this is a hardware issue or a kernel issue? And how to solve this issue? Here's the relevant log: [32832.280148] audit: type=1327 audit(1751365801.520:22): proctitle=2F7573722F7362696E2F63726F6E64002D6E [36432.304306] audit: type=1006 audit(1751369401.584:23): pid=3094 uid=0 subj=kernel old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=15 res=1 [36432.317968] audit: type=1300 audit(1751369401.584:23): arch=c00000b7 syscall=64 success=yes exit=1 a0=3 a1=ffffd19f6b10 a2=1 a3=ffffa11e9020 items=0 ppid=265 pid=3094 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=15 comm="crond" exe="/usr/sbin/crond" subj=kernel key=(null) [36432.344959] audit: type=1327 audit(1751369401.584:23): proctitle=2F7573722F7362696E2F63726F6E64002D6E [37877.552323] rcu: INFO: rcu_preempt self-detected stall on CPU [37877.558090] rcu: 2-...!: (1 ticks this GP) idle=d95/0/0x3 softirq=199976/199976 fqs=0 [37877.566100] (t=5958 jiffies g=1820793 q=55) [37877.570369] rcu: rcu_preempt kthread timer wakeup didn't happen for 5957 jiffies! g1820793 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 [37877.581933] rcu: Possible timer handling issue on cpu=0 timer-softirq=157944 [37877.589067] rcu: rcu_preempt kthread starved for 5958 jiffies! g1820793 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=0 [37877.599676] rcu: Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior. [37877.608805] rcu: RCU grace-period kthread stack dump: [37877.613854] task:rcu_preempt state:I stack: 0 pid: 13 ppid: 2 flags:0x00000008 [37877.622211] Call trace: [37877.624655] __switch_to+0x104/0x15c [37877.628241] __schedule+0x2b8/0x710 [37877.631733] schedule+0x88/0x100 [37877.634962] schedule_timeout+0x80/0xf0 [37877.638801] rcu_gp_fqs_loop+0x118/0x2e0 [37877.642726] rcu_gp_kthread+0x104/0x11c [37877.646564] kthread+0x150/0x160 [37877.649795] ret_from_fork+0x10/0x20 [37877.653373] rcu: Stack dump where RCU GP kthread last ran: [37877.658855] Task dump for CPU 0: [37877.662081] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x00000008 [37877.671999] Call trace: [37877.674443] __switch_to+0x104/0x15c [37877.678021] cpuidle_enter_state+0x25c/0x2f0 [37877.682296] cpuidle_enter+0x38/0x50 [37877.685873] do_idle+0x210/0x2a0 [37877.689103] cpu_startup_entry+0x24/0x80 [37877.693027] rest_init+0xe4/0xf4 [37877.696256] arch_call_rest_init+0x10/0x1c [37877.700356] start_kernel+0x610/0x650 [37877.704020] __primary_switched+0xbc/0xc4 [37877.708037] Task dump for CPU 0: [37877.711264] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x00000008 [37877.721181] Call trace: [37877.723625] __switch_to+0x104/0x15c [37877.727203] cpuidle_enter_state+0x25c/0x2f0 [37877.731475] cpuidle_enter+0x38/0x50 [37877.735052] do_idle+0x210/0x2a0 [37877.738281] cpu_startup_entry+0x24/0x80 [37877.742205] rest_init+0xe4/0xf4 [37877.745433] arch_call_rest_init+0x10/0x1c [37877.749531] start_kernel+0x610/0x650 [37877.753194] __primary_switched+0xbc/0xc4 [37877.757206] Task dump for CPU 2: [37877.760431] task:swapper/2 state:R running task stack: 0 pid: 0 ppid: 1 flags:0x00000008 [37877.770349] Call trace: [37877.772792] dump_backtrace+0x0/0x19c [37877.776457] show_stack+0x18/0x70 [37877.779775] sched_show_task+0x154/0x180 [37877.783701] dump_cpu_task+0x44/0x58 [37877.787280] rcu_dump_cpu_stacks+0xe8/0x12c i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, After our tests, we found that the PMIC was causing this issue. Thank you for your support. Re: i.MX8MM Kernel crashes on cpuidle if just one board has this issue, as I mentioned before, you can do the AB test to confirm if this issue is related to the chip, since other boards are fine Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, Thanks for your information. But we don't plan to change the kernel configuration just for one faulty device. We're going to have the distributor help us analyze the problem. Re: i.MX8MM Kernel crashes on cpuidle For optimized performance on the i.MX, you can try to set the stpes as below: CONFIG_ARM_PSCI_CPUIDLE=n in the defconfig files, to avoid cpu enter idle state,  and CONFIG_ARM_PSCI_CPUIDLE is depends on the CONFIG_CPU_FREQ, if couldn't set CONFIG_CPU_FREQ=n, also suggest set CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y to the CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y, I think this should be the same as you use "echo performance" command in the user space Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, All of your boards get the same result when you use the command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? => Yes. # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1200000 1600000 What is the frequency when you use ondemand and performance? => The frequency is the same for both ondemand and performance mode. # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq 1600000 Re: i.MX8MM Kernel crashes on cpuidle if all of your boards have the same SW and HW, only one board has issue, you can do the AB test, to check if the chip issue, all of your boards get the same result when you use the command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? and what is the frequency when you use ondemand and performance? I mean when you set ondemand or performance, use the command to check "cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq", are the ondemad and performance share the same cpu frequency?  Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, Thanks for your information. Our kernel has only been modified for peripheral hardware; we haven't made any changes to the CPU frequency or other CPU-related settings. Many of our devices can boot and run normally. Currently, only one device will crash after running for a day. Here is the scaling_available_frequencies result: # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1200000 1600000 Re: i.MX8MM Kernel crashes on cpuidle what do you change in the kernel? the imx8mm default frequency is 1.2Ghz, so you couldn't boot up the board as default, right? what do you get "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies"? the uboot set the init clock under /arch/arm/mach-imx/imx8m/clock_imx8mm.c for the kernel, set the available cpu frequency in the dtsi file and the cpufreq driver is https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/cpufreq/imx-cpufreq-dt.c if your bsp is the similar as nxp, it seems the system crash under 1.2G, you can refer to the chapter 2.5.3 CPU Frequency Scaling (CPUFREQ) of enclosed file Re: i.MX8MM Kernel crashes on cpuidle Hi joanxie, System crashed while CPU governor is ondemand mode. Here is the scaling_available_governors result: # cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors conservative ondemand userspace powersave performance schedutil Re: i.MX8MM Kernel crashes on cpuidle  The system's default CPU governor is ondemand. We've tested changing the CPU governor to performance, and the system no longer crashes. > is it your typo?when do you get the system crash? with ondemand or with performance? do you mind giving me the result with command "cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors" ?
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DCP Hashing Cache Alignment Issues + Potential HAL Bugs Hello!  My coworker and I encountered some weird behavior when attempting to implement accelerated CRC-32 using the MIMXRT1062's Data Co-Processor.  We believe that we've localized the issue to a bug related to how the DCP driver handles cache alignment, but we are still a little confused by what we saw. The issue originally manifested as, we would get CRC failures in our production application under specific conditions when it attempted to CRC a large block of memory.  The CRC hashing always worked fine under unit tests, but if we reproduce a specific sequence of operations we can trigger it to fail reliably in our application.  Currently I'm unsure if it was failing with an error code or if it was returning the wrong CRC value, because the way it occurred made it hard to debug.  We will continue looking into that this week. Thankfully, my coworker managed to find a band-aid solution to the problem: attaching an alignas(32) declaration to our dcp_hash_ctx_t instance (which is stored in DTCM).  With this in place, CRCs worked reliably and we could no longer reproduce the problem. To understand the issue better, we took a look inside the HAL's DCP driver and tried to understand what was going on with the alignment stuff in there.  What we found was... issues.  Many issues.  I will list out what we found in order of least to most serious. Inefficient DCP_FindCacheLine() Implementation This function is designed to look forward from an address to find the next cache line.  It works, but it's terribly inefficient, especially for a function called EVERY time a DCP_HASH function is used -- it uses a loop to do what should be a constant-time operation.  I wrote a new version for you which uses multiplication & division operations to accomplish the same result.  (bitwise operations could also be used but are less clear, and these are multiplies/divides by powers of 2 so the compiler will optimize into bitwise ops). /** * @brief Advances \c dcpWorkExt forward until a cache line boundary is reached. * @return Cache-aligned pointer between 0 and FSL_FEATURE_L1DCACHE_LINESIZE_BYTE-1 bytes ahead of \c dcpWorkExt */ static inline uint32_t *DCP_FindCacheLine(uint8_t *dcpWorkExt) { // Use integer division to divide the address down to the cache line size, which // rounds to the cache line before the given address. // So that we always go one cache line back even if the given address is on a cache line, // subtract 1. ptrdiff_t prevCacheLine = ((ptrdiff_t)(dcpWorkExt - 1)) / FSL_FEATURE_L1DCACHE_LINESIZE_BYTE; // Now we just have to multiply up again to get an address (adding 1 to go forward by 1 cache line) return (uint32_t *)((prevCacheLine + 1) * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE); } By all means, please take this one and replace the current implementation with it! Incorrect assertion in DCP_HASH_Init() The code in DCP_HASH_Init() contains the following assertion: BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size);  However, this is incorrect for the case where DCACHE is enabled, as the FindCacheLine function could potentially advance the context pointer by up to 31 bytes.  Honestly, we all got kinda lucky that dcp_hash_ctx_t (256 bytes) is >32 bytes larger than dcp_hash_ctx_internal_t (188 bytes); if that wasn't the case then you could potentially get out-of-bounds writes depending on how far it has to advance to find a cache line -- not a Heisenbug I want to deal with! To fix the issue, I believe that this assertion should be used instead: #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U) BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= (sizeof(dcp_hash_ctx_internal_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1), dcp_hash_ctx_t_size_too_small); #else BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size_too_small); #endif  Incorrect cache alignment method in DCP_HASH functions The most serious issue we found affects the DCP_HASH_Init(), DCP_HASH_Update(), and DCP_HASH_Finish() functions.  All of those functions contain the following code which seems to want to align the dcp_hash_ctx_internal_t: /* Align structure on DCACHE line*/ #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U) ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)((uint8_t *)ctx + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE); #else ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)ctx; #endif Unfortunately this just... doesn't work.  At all.  It just increments the passed pointer by 1 cache line size, rather than actually doing anything to align it.  So, for all this time, the hash functions have not actually been working with cache aligned buffers unless the dcp_hash_ctx_t structure itself is cache aligned.  This seems to partially explain why my coworker's fix worked, as it means that the structure wasn't actually aligned until we did so manually. We believe that the correct code would likely be: /* Align structure on DCACHE line*/ #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U) ctxInternal = (dcp_hash_ctx_internal_t *)DCP_FindCacheLine((uint8_t *)ctx); #else ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)ctx; #endif Questions Remaining While we seem to have worked around the issue in the short term, I feel like we still need more information before we can consider this closed.  CRCs using the DCP will be a key part of our application, and it would be very difficult to de-couple them this later if we discover that CRCs are not being done reliably.  So, we need to be absolutely sure that the issue we saw is fixed by these changes before we can move forward (which is difficult because we can't reproduce the problem in tests). So, I have two questions which I'd really appreciate answered: Could someone confirm whether the three things we posted are actually issues in the DCP HAL driver and, if they are, that they will be fixed in a future release? Could someone comment on whether the issue we saw (failed CRC operations) could actually be caused by the effect of these bugs (internal hash context is not aligned)?  I wasn't able to find any obvious reason *why* those two things would be connected, despite comments and another forum post which indicate that they are.  It's especially puzzling because the DCP context is located in DTCM and therefore shouldn't need explicit cache management (right?).  Does the DCP just assume things are cache aligned without stating that anywhere? Thanks for reading through all this and and I hope that you can help us with these questions!  Thank you so much! i.MXRT 106x Re: DCP Hashing Cache Alignment Issues + Potential HAL Bugs Hello, as of SDK 25.06.00 the DCP HASH functionality is still broken - totally unusable in a loop of incremental calls to DCP_HASH_Update, while one single call works fine (but we can't use it this way). Also tried the suggested patches, but nope. How is it possible that after two years no fix is available yet? Any plan to fix it soon? Thank you and best regards, Stefano Re: DCP Hashing Cache Alignment Issues + Potential HAL Bugs Hi Diego, Thanks for getting back to us, I know it's a lot to go through!  Unfortunately, after further testing, we weren't able to reliably reproduce the issue.  And once we merged in the fixes in this post, we have not seen it happen again.  I know that isn't proof positive that they work, but I do think that these changes ought to be made in the driver. Anyway, thanks for passing on these fixes! Jamie Re: DCP Hashing Cache Alignment Issues + Potential HAL Bugs Hi @MultipleMonomials  I am sorry for not reaching you out sooner. This issue requieres further investigation from our end. So, I still can not provide an answer to your questions at this moment. I am glad to know that you are reporting code improvements to prevent  part of this issue for happening.   May I ask for more details to replicate this issue? How can we modify the DCP demo from the SDK to get this replicated with our evk? Asking this just to  facilitate the diagnosis of the error and report this to the error team.  All the best,  Diego
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S32K3 TCPIP RTM 1.0.1HF1 ですかS32K3 RTD RTM2.0.0 ベースまたは S32K3 RTD RTM2.0.1 ベース S32K3_T_BOX_LWIP_for_S32K3.zipを使用してS32K3-T-BOXをテストしました。S32K3 RTD RTM2.0.0とFreeRTOS2.0.0をインストールしましたが、TCPIP RTM 1.0.1HF1をインストールできません(S32K3 RTD RTM2.0.1 をインストールするように求められます。 ただし、NXP WEB でサポートされるコードは S32K3 RTD RTM2.0.0 に依存します。 nxp ウェブ上で TCPIP RTM 1.0.1 without HF1 が見つかりません。TCPIP RTM 1.0.1HF1 しかありません。 S32K3 RTD RTM2.0.1 または HF1 なしの TCPIP RTM 1.0.1 に基づくコードを提供できますか? Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 こんにちは@xMaryAES 、 サポートチケットを通じてサポート CASE を入力してください。 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 こんにちは@Julián_AragónM 、 HF1 なしの TCP/IP RTM 1.0.1 も共有していただけますか。または、どこで見つけられるか教えていただけますか。 S32K3-T-BOX ありがとうございます。よろしくお願いします。 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 こんにちは@Julián_AragónM 、 S32K3 RTD RTM2.0.0 と互換性のある HF1 なしの TCP/IP RTM 1.0.1 を共有していただけますか? よろしくお願いいたします。 T1AES Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 hf1 なしの S32K3 TCPIP RTM 1.0.1 を送っていただけますか?ありがとう。 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 こんにちは@SCoder41さん、 Flexera での可視性についてはわかりませんが、HF1 なしの TCP/IP RTM 1.0.1 の UpdateSite を記載したプライベート メッセージを送信しました。 よろしくお願いします、 ジュリアン
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s32kがopenOCDをサポートしている場合 こんにちは皆さん S32K シリーズ (S32K144 や S32K344 など) が openOCD をサポートしているかどうかを知りたいです。サポートされている場合、これらの S32K の cfg ファイルはどこで見つかりますか? Re: if s32k support openOCD 私のボードの s32k144 では、 「s32k.cfg」を使用できるでしょうか? 私のopenocdのバージョンは「Open On-Chip Debugger 0.12.0+dev-snapshot (2025-07-16-14:15)」です Re: if s32k support openOCD こんにちは@rtzeropti OpenOCD Web サイトには、S32K デバイスの公式サポートに関する情報はありません。 サポートを求めるには、OpenOCD コミュニティが最適です。 BR ヴェインB Re: if s32k support openOCD 私も同じ質問があります。CMSIS-DAP デバッガーをどのようにサポートすればよいのでしょうか?
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2 mpr121 sensors in one arduino -> serial communication I am trying to connect 2(0x5A, 0x5B)addresses. In the code and  datasheet,  it says just connecting addr pin to (default, 3.3v) allows communication. Arduino recognizes other sensors, however, it cannot read the two touch sensor at one time. just tells me i=0 ~ 11 how can I make the i=12~23 run? and how can I differentiate 2 sensors in code? Is it possible to communicate mpr121 sensor to mpr121 sensor ?  I really want to know how to connect two sensors in one arduino. I also tried i2c scanner to check the wiring and weird thing is that serial monitor only tells me just one sensor. here's my code should i add some define in the first to differentiate? or  change loop  for{ } please enlighten me asap X( ------------------------------------------------------------------------------------------------------------------------------------ #include "SoftwareSerial.h" //#define defaultPatch 15 //악기 초기화 버튼 설정 악기번호 SoftwareSerial mySerial(2, 3); //SW시리얼핀 정의 D3이 MIDI신호 전송용, D2는 미사용 byte note = 0; //The MIDI연주될 note(음계) byte resetMIDI = 4; // VS1053 Reset용 핀 byte ledPin = 13; //MIDI 트래픽 표시용 LED #include #include "Adafruit_MPR121.h" #ifndef _BV #define _BV(bit) (1 << (bit)) #endif Adafruit_MPR121 cap = Adafruit_MPR121(); #define MPR121addr 0x5A #define MPR121addr 0x5B uint16_t lasttouched = 0; uint16_t currtouched = 0; #include int btn[]={60, 62, 64, 65, 67,69, 71, 72, 74, 76, 77, 79, 81, 83, 84, 86, 88, 89, 91, 93, 95, 96, 98, 100}; byte byteData; void setup() { Serial.begin(9600); mySerial.begin(9600); /* while (!Serial) { // needed to keep leonardo/micro from starting too fast! delay(10); } */ Serial.println("Adafruit MPR121 Capacitive Touch sensor test"); // Default address is 0x5A, if tied to 3.3V its 0x5B // If tied to SDA its 0x5C and if SCL then 0x5D if (!cap.begin(0x5A)) { Serial.println("MPR121-A not found, check wiring?"); while (1); } Serial.println("MPR121-A found!"); // if (!cap.begin(0x5B)) { Serial.println("MPR121-B not found, check wiring?"); while (1); } Serial.println("MPR121-B found!"); //Reset the VS1053 pinMode(resetMIDI, OUTPUT); digitalWrite(resetMIDI, LOW); delay(100); digitalWrite(resetMIDI, HIGH); delay(100); } void loop() { currtouched = cap.touched(); for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched & _BV(i)) && !(lasttouched & _BV(i)) ) { Serial.print(i); Serial.println(" touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } } for (uint8_t i=12; i<24; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched & _BV(i)) && !(lasttouched & _BV(i)) ) { Serial.print(i); Serial.println(" touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } } //*************** MIDI LOOPBACK ******************// if(Serial.available() > 0) { byteData = Serial.read(); mySerial.write( byteData); } lasttouched = currtouched; return; } //Send a MIDI note-on message. Like pressing a piano key //channel ranges from 0-15 void noteOn(byte channel, byte note, byte attack_velocity) { talkMIDI( (0x90 | channel), note, attack_velocity); } //Send a MIDI note-off message. Like releasing a piano key void noteOff(byte channel, byte note, byte release_velocity) { talkMIDI( (0x80 | channel), note, release_velocity); } //Plays a MIDI note. Doesn't check to see that cmd is greater than 127, or that data values are less than 127 void talkMIDI(byte cmd, byte data1, byte data2) { digitalWrite(ledPin, HIGH); mySerial.write(cmd ); mySerial.write(data1 ); //Some commands only have one data byte. All cmds less than 0xBn have 2 data bytes //(sort of: http://253.ccarh.org/handout/midiprotocol/) if( (cmd & 0xF0) <= 0xB0) mySerial.write(data2 ); digitalWrite(ledPin, LOW); } Touch Sensors Re: 2 mpr121 sensors in one arduino -> serial communication I only have 1 MPR121, so  I couldn't try the code, but I think it should be change like below : for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched & _BV(i)) && !(lasttouched & _BV(i)) ) { Serial.print(i); Serial.println(" touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } } for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched2 & _BV(i)) && !(lasttouched2 & _BV(i)) ) { //when sensor is touched do something Serial.print(i+12); Serial.println(" touched"); noteOn(0, btn[i],100); } } MPR121 have 12 input, _BV(bit)' bit parameter should always between 0-12, then use currtouched2 choose different ADDR. Lib's line-230: https://github.com/adafruit/Adafruit_MPR121/blob/master/Adafruit_MPR121.cpp Re: 2 mpr121 sensors in one arduino -> serial communication I have connected two MPR121 boards to my Arduino Uno at addresses 0x5C and 0x5A. The boards are recognized correctly. However, I would like to understand how I can set both boards in AUTOCONFIG mode and how I can adjust the TOUCH and RELEASE thresholds for each sensor on both boards. At the moment I use the .CPP file to make these settings but it seems to work only on the 0x5a address board. Thank you! Re: 2 mpr121 sensors in one arduino -> serial communication Hi Jin, Glad to hear you managed to connect all four MPR121 sensors on the same I2C bus. I am not sure about your current question, I assume it can be done easily in your sw depending on the address of the sensor you are currently communicating with.   Best regards, Tomas Re: 2 mpr121 sensors in one arduino -> serial communication Mr. Vacerka  Thank you so much!! I was relieved by the possibility of connection. For your kind reply, I succeeded in connecting all 4 mpr121 sensors!! One last problem I am facing is that "expand the number of touch buttons up to 24." Every touch sensor gives me value of  0 to 11. How can I make it to 0-11, 12-23, 24-35, 36-47 ? -----------------------------------------------------------------------------------------------------------------------------------------------------  #include "SoftwareSerial.h" //#define defaultPatch 15 //악기 초기화 버튼 설정 악기번호 SoftwareSerial mySerial(2, 3); //SW시리얼핀 정의 D3이 MIDI신호 전송용, D2는 미사용 byte note = 0; //The MIDI연주될 note(음계) byte resetMIDI = 4; // VS1053 Reset용 핀 byte ledPin = 13; //MIDI 트래픽 표시용 LED #include #include "Adafruit_MPR121.h" #ifndef _BV #define _BV(bit) (1 << (bit)) #endif // You can have up to 4 on one i2c bus but one is enough for testing! Adafruit_MPR121 cap = Adafruit_MPR121(); Adafruit_MPR121 cap2 = Adafruit_MPR121(); Adafruit_MPR121 cap3 = Adafruit_MPR121(); Adafruit_MPR121 cap4 = Adafruit_MPR121(); // Keeps track of the last pins touched // so we know when buttons are 'released' uint16_t lasttouched = 0; uint16_t currtouched = 0; uint16_t lasttouched2 = 0; uint16_t currtouched2 = 0; uint16_t lasttouched3 = 0; uint16_t currtouched3 = 0; uint16_t lasttouched4 = 0; uint16_t currtouched4 = 0; int btn[]={21, 23, 24, 26, 28, 29, 31, 33, 35, 36, 38, 40, 41, 43, 45, 47, 48, 50, 52, 53, 55, 57, 59, 60, 62, 64, 65, 67,69, 71, 72, 74, 76, 77, 79, 81, 83, 84, 86, 88, 89, 91, 93, 95, 96, 98, 100, 101}; byte byteData; void setup() { Serial.begin(9600); mySerial.begin(9600); while (!Serial) { // needed to keep leonardo/micro from starting too fast! delay(10); } Serial.println("Adafruit MPR121 Capacitive Touch sensor test"); // Default address is 0x5A, if tied to 3.3V its 0x5B // If tied to SDA its 0x5C and if SCL then 0x5D if (!cap.begin(0x5A)) { Serial.println("MPR121-A not found, check wiring?"); while (1); } Serial.println("MPR121-A found!"); // if (!cap2.begin(0x5B)) { Serial.println("MPR121-B not found, check wiring?"); while (1); } Serial.println("MPR121-B found!"); // if (!cap3.begin(0x5C)) { Serial.println("MPR121-C not found, check wiring?"); while (1); } Serial.println("MPR121-C found!"); // if (!cap4.begin(0x5D)) { Serial.println("MPR121-D not found, check wiring?"); while (1); } Serial.println("MPR121-D found!"); //Reset the VS1053 pinMode(resetMIDI, OUTPUT); digitalWrite(resetMIDI, LOW); delay(100); digitalWrite(resetMIDI, HIGH); delay(100); // this is inside the loop so you can plug boards hot // if you do not need hot plugin you may put it in setup() cap.begin(0x5A); cap2.begin(0x5B); cap3.begin(0x5C); cap4.begin(0x5D); } void loop() { // Get the currently touched pads currtouched = cap.touched(); currtouched2 = cap2.touched(); currtouched3 = cap3.touched(); currtouched4 = cap4.touched(); for (uint8_t i=0; i<48; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched & _BV(i)) && !(lasttouched & _BV(i)) ) { Serial.print(i); Serial.println(" touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } //2/////////////////////////////////////////////////// if ((currtouched2 & _BV(i)) && !(lasttouched2 & _BV(i)) ) { //when sensor is touched do something Serial.print(i); Serial.println(" touched"); noteOn(0, btn[i],100); } //3/////////////////////////////////////////////////// if ((currtouched3 & _BV(i)) && !(lasttouched3 & _BV(i)) ) { //when sensor is touched do something Serial.print(i); Serial.println(" touched"); noteOn(0, btn[i],100); } //4/////////////////////////////////////////////////// if ((currtouched4 & _BV(i)) && !(lasttouched4 & _BV(i)) ) { //when sensor is touched do something Serial.print(i); Serial.println(" touched"); noteOn(0, btn[i],100); } } // reset our state lasttouched = currtouched; lasttouched2 = currtouched2; lasttouched3 = currtouched3; lasttouched4 = currtouched4; return; //*************** MIDI LOOPBACK ******************// if(Serial.available() > 0) { byteData = Serial.read(); mySerial.write( byteData); } } //Send a MIDI note-on message. Like pressing a piano key //channel ranges from 0-15 void noteOn(byte channel, byte note, byte attack_velocity) { talkMIDI( (0x90 | channel), note, attack_velocity); } //Send a MIDI note-off message. Like releasing a piano key void noteOff(byte channel, byte note, byte release_velocity) { talkMIDI( (0x80 | channel), note, release_velocity); } //Plays a MIDI note. Doesn't check to see that cmd is greater than 127, or that data values are less than 127 void talkMIDI(byte cmd, byte data1, byte data2) { digitalWrite(ledPin, HIGH); mySerial.write(cmd ); mySerial.write(data1 ); //Some commands only have one data byte. All cmds less than 0xBn have 2 data bytes //(sort of: http://253.ccarh.org/handout/midiprotocol/) if( (cmd & 0xF0) <= 0xB0) mySerial.write(data2 ); digitalWrite(ledPin, LOW); }   Re: 2 mpr121 sensors in one arduino -> serial communication Hi Jin, Yes, it is possible to communicate with two MPR121 sensors on the same I2C bus in order expand the number of touch buttons up to 24. Actually you can assign four I2C addresses to the MPR121 depending on the connection of the ADDR pin:   For instance, one MPR121 slave will have the 7-bit I2C address of 0x5A when ADDR=VDD (which translates to 0xB4 for a write and 0xB5 for a read) and the other one 0x5B when ADDR=GND (which translates to 0xB6 for a write and 0xB7 for a read). I hope it helps! Best regards, Tomas
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S32G A53 QNX 上的 PFE 故障     您好,恩智浦专家 我们有一个自定义板要在上面运行 QNX 和 PFE 驱动程序。但我们遇到了以下问题,希望 PFE 专家帮助分析一下。     软件信息: PFE QNX 驱动程序版本:1.8.0 PFE FW 版本: 1.11.0 QNX SDP 版本: 7.1.0 QNX S32G399A 的 电路板支持包 版本:bsp_nxp-s32G-rdb3_br-710_be-710_be-710_svn996606_jbn10   硬件信息: 我们和恩智浦 S32G399ARDB3 EVN 板之间的硬件区别在于,DDR 已更改为 2GB,而且我们已经在 Linux 中对其进行了调整,而且 pfe 以太网驱动程序是正常的。 变化如下:           1。images/s32g399a-rdb.版本 文件中的更改,   2。src\ hardware\ startup\ 板\ s32g\ s32g399a-rdb\ s32g_init_raminfo.c 中的变化文件:     3.其他无关紧要的变化,与 PFE 驱动程序无关。       我的测试命令是: # slog2info -c # slog2info -w& # io-pkt-v6-hc-p tcpip pkt_typed_mem=pfe_ddr-d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/boot/devnp-boot/boot=/proc/boot/devnp-boot-2.so class_fw=/proc/boot/devnp-boot/boot=/proc/boot/devnp-boot=/   但是,运行后出现了错误信息。日志在此。 -------------------Appendix------------------     注意:在 SCMI 代理 RESET 命令期间发现已启用的时钟列表: 注意:linflex_lin 注意: usdhc_core board_smp_num_cpu: 8 个内核 MMU:16 位 ASID 40 位 PA TCR_EL1=b5183519 ARM GIC-500 r1p1,已检测到 arch v3.0 board_smp_num_cpu: 8 个内核 board_smp_num_cpu: 8 个内核 无 SPI 内部信息。为 32 -> 575 向量添加默认条目,OK cpu0: MPIDR=80000000 cpu0:MIDR=410fd034 Cortex-A53 r0p4 cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu0:CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu0:L1 缓存 32K linesz=64 set/way=256/2 cpu0:L1 缓存 32K linesz=64 set/way=128/4 cpu0:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_num_cpu: 8 个内核   A53 核心时钟:1000MHz DDR 时钟:800MHz SERDES 时钟:2000MHz LINFLEXD 时钟:125 兆赫 GMAC TS 时钟:48 兆赫 SPI 时钟:48MHz QSPI 时钟:800MHz SDHC 时钟:800MHz   加载 IFS...解压...完成 board_smp_start: cpu_cluster_id:0, cpu_id:1 注意:S32 TF-A:s32_pwr_domain_on:启动内核 1 (0) 跑步 cpu1: MPIDR=80000001 cpu1:MIDR=410fd034 Cortex-A53 r0p4 cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu1:L1 高速缓存 32K linesz=64 set/way=256/2 cpu1:L1 缓存 32K linesz=64 set/way=128/4 cpu1:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:0, cpu_id: 2 NOTTCE: S32 T TA: s323pw_pdomrin_on: bootingnup cor 2u 0) 宁 cpu2: MPIDR=80000002 cpu2:MIDR=410fd034 Cortex-A53 r0p4 cpu2: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu2: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu2:L1 缓存 32K linesz=64 set/way=256/2 cpu2:L1 缓存 32K linesz=64 set/way=128/4 cpu2:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:0, cpu_id:3 ngTice:SS32TT-A:: 32_pwr_rodain_on:启动核心 (30n) cpu3: MPIDR=80000003 cpu3:MIDR=410fd034 Cortex-A53 r0p4 cpu3: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu3: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu3:L1 缓存 32K linesz=64 set/way=256/2 cpu3:L1 缓存 32K linesz=64 set/way=128/4 cpu3:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:1, cpu_id:0 注意:S32 TF-A:s32_pwr_domain_on:启动核心 4 (0) 注意:S32 TF-A:s32_pwr_domain_on_finish:CPU 4 正在运行 cpu4: MPIDR=80000100 cpu4:MIDR=410fd034 Cortex-A53 r0p4 cpu4: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu4: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu4:L1 缓存 32K linesz=64 set/way=256/2 cpu4:L1 Dcache 32K linesz=64 set/way=128/4 cpu4:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:1, cpu_id:1 注意:S32 TF-A:s32_pwr_domain_on:启动内核 5 (0) cpu 5 运行 cpu5: MPIDR=80000101 cpu5:MIDR=410fd034 Cortex-A53 r0p4 cpu5: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu5: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu5:L1 高速缓存 32K linesz=64 set/way=256/2 cpu5:L1 缓存 32K linesz=64 set/way=128/4 cpu5:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:1, cpu_id: 2 注意:S32 TF-A:s32_pwr_domain_on:启动内核 6 (0) 宁 cpu6: MPIDR=80000102 cpu6:MIDR=410fd034 Cortex-A53 r0p4 cpu6: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu6: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu6:L1 高速缓存 32K linesz=64 set/way=256/2 cpu6:L1 缓存 32K linesz=64 set/way=128/4 cpu6:L2 统一 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id:1, cpu_id:3 注意:S32 TF-A:s32_pwr_domain_on:启动核心 7 (0) 7 运行 cpu7: MPIDR=80000103 cpu7:MIDR=410fd034 Cortex-A53 r0p4 cpu7: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu7: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu7:L1 高速缓存 32K linesz=64 set/way=256/2 cpu7:L1 缓存 32K linesz=64 set/way=128/4 cpu7:L2 统一 1024K linesz=64 set/way=1024/16   系统页面位于 phys:00000000a0010000 user:ffffff8040315000 kern:ffffff8040311000 在 vffffff8060097300 处开始下一个程序 时钟周期样本: 0 62957977 1 62957977 2 62957978 3 62957977 4 62957977 5 62957977 6 62957977 7 62957977 所有时钟周期偏移在公差范围内 欢迎使用 QNX Neutrino 7.1.0 版在恩智浦 S32G399A RDB 板上!! 启动看门狗... 启动串行驱动程序 ... 启动网络驱动程序 (/dev/socket)... 启动 SPI 驱动程序 (/dev/spi0,1,2,3,4,5)... 启动 I2C 0/1/2/3/4 驱动程序 (/dev/i2c0,1,2,3,4)... 启动 USDHC0 存储卡驱动程序... Path=Starting CAN driver... 0 - imx target=0 lun=0 Direct-Access(0) - SDMMC: AAM20E Rev: 1.0 数量 数量 数量 # slog2info -c   进程 4117 (slog2info) 已退出,状态=0。 ghccu# slog2info -w& [1] 12309 random.4 low 0 -----UNSYNC----- 随机.4 高 0 -----UNSYNC----- Jan 01 00:00:00.022 控制台.3 0 -----ONLINE----- console.3 out 0 -----UNSYNC----- Jan 01 00:00:00.027 随机.4 0 -----ONLINE----- random.4 default 0 -----UNSYNC----- Jan 01 00:00:00.028 random.4..0 0 -----ONLINE----- random.4..0 slog 0 -----UNSYNC----- Jan 01 00:00:00.050 devc_serlinflexd.7 0 -----ONLINE----- devc_serlinflexd.7 slog 0 -----UNSYNC----- Jan 01 00:00:00.055 spi_master.8 0 -----ONLINE----- spi_master.8 normal 0 -----UNSYNC----- Jan 01 00:00:00.059 spi_master.9 0 -----ONLINE----- spi_master.9 normal 0 -----UNSYNC----- Jan 01 00:00:00.063 spi_master.10 0 -----ONLINE----- spi_master.10 normal 0 -----UNSYNC----- Jan 01 00:00:00.067 spi_master.11 0 -----ONLINE----- spi_master.11 normal 0 -----UNSYNC----- Jan 01 00:00:00.088 devb_sdmmc_mx8x.17 0 -----ONLINE----- devb_sdmmc_mx8x.17 slog 0 -----UNSYNC----- Jan 01 00:00:04.268 qconn.20 0 -----ONLINE----- qconn.20 slog 0 -----UNSYNC----- 数量 数量 数量 # io-pkt-v6-hc-p tcpip pkt_typed_mem=pfe_ddr-d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/boot/devnp-boot/boot=/proc/boot/devnp-boot-2.so class_fw=/proc/boot/devnp-boot/boot=/proc/boot/devnp-boot=/ # Jan 01 00:00:14.060 iopkt.16408 0 -----ONLINE----- Jan 01 00:00:14.060 iopkt.16408 main_buffer* 0 detect_armv8ce_hw:支持 armv8ce! Jan 01 00:00:14.061 iopkt.16408 main_buffer 0 tcpip 启动 Jan 01 00:00:14.062 iopkt.16408 main_buffer 0 smmu 支持已禁用 Jan 01 00:00:14.063 iopkt.16408 main_buffer 0 正在初始化 IPsec... Jan 01 00:00:14.063 iopkt.16408 main_buffer 0 done   Jan 01 00:00:14.064 iopkt.16408 main_buffer 0 IPsec:已初始化的网络安全关联处理。   Jan 01 00:00:14.067 iopkt.16408 main_buffer 0 /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw,util_fw=/proc/boot/s32g_pfe_util.fw Jan 01 00:00:14.068 io_pkt_v6_hc.16408 0 -----ONLINE----- Jan 01 00:00:14.068 io_pkt_v6_hc.16408 slog* 0 INF[src/pfe_drv.c:1346]:版本信息 驱动程序版本: 1.8.0 驱动程序提交哈希值:57b6eefdb35cbff7a43ecfbdca3334760b1d0553 pfe_cfg_multi_instance_support: 0 pfe_cfg_local_if:6 pfe_cfg_master_if:6 pfe_cfg_sc_hif:1 pfe_cfg_hif_ring_length: 256 pfe_cfg_pfe0_promisc: 1 pfe_cfg_pfe1_promisc: 1 pfe_cfg_pfe2_promisc: 1     Jan 01 00:00:14.068 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1353]:--- 安全 IRQ 已启用。不允许使用 InterrupAttach() 或 InterrupAttach_r()。   Jan 01 00:00:14.068 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_fw.c:94]:读取 45724 字节   Jan 01 00:00:14.068 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_fw.c:100]:加载的固件文件:/proc/启动/s32g_pfe_class.fw   Jan 01 00:00:14.068 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_fw.c:94]:读取 23352 字节   Jan 01 00:00:14.069 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_fw.c:100]:加载的固件文件:/proc/启动/s32g_pfe_util.fw   Jan 01 00:00:14.069 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1449]:未找到 pfe0/EMAC0 的 MII 模式配置。使用 SGMII。   Jan 01 00:00:14.069 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1449]:未找到 pfe1/EMAC1 的 MII 模式配置。使用 SGMII。   Jan 01 00:00:14.069 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1449]:未找到 pfe2/EMAC2 的 MII 模式配置。使用 SGMII。   Jan 01 00:00:14.069 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1467]:发出 PFE 外设 RESET...   Jan 01 00:00:14.179 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1468]:PFE RESET 正常。   Jan 01 00:00:14.179 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2826]:PFE CBUS p0x46000000 已映射 @ v0x1e2a574000(0x1000000 字节)   Jan 01 00:00:14.179 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2831]:硬件版本 0x101   Jan 01 00:00:14.179 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_hw_feature.c:95]:硅 S32G3   Jan 01 00:00:14.179 io_pkt_v6_hc.16408 slog 0 WRN[hw/s32g/pfe_platform_master.c:2843]:禁用故障停机模式   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2093]:PFE_ERRORS:已创建奇偶校验实例   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2108]:PFE_ERRORS:已创建看门狗实例   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2124]:pfe_errors: 已创建总线错误实例   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2137]:PFE_ERRORS:已创建 FW 故障停止实例   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2150]:PFE_ERRORS:已创建主机故障停止实例   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2163]:PFE_ERRORS:创建的停止实例失败   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:2176]:PFE_ERRORS:ECC Err 实例已创建   Jan 01 00:00:14.254 io_pkt_v6_hc.16408 slog 0 INF[hw/s32g/pfe_platform_master.c:1097]:BMU1 缓冲区基数: p0xc0000000   Jan 01 00:00:14.255 io_pkt_v6_hc.16408 slog 0 ERR[src/oal_mm_qnx.c:98]: (DRIVER) event 1 - Driver runtime error: mmap64() failed: 1   Jan 01 00:00:14.255 io_pkt_v6_hc.16408 slog 0 ERR[src/oal_mm_qnx.c:171]: (DRIVER) event 1 - Driver runtime error:无法获取内存块   Jan 01 00:00:14.255 io_pkt_v6_hc.16408 slog 0 ERR[hw/s32g/pfe_platform_master.c:1125]:(DRIVER) 事件 1 - 驱动程序运行时出错:无法获取 BMU2 池内存   Jan 01 00:00:14.256 io_pkt_v6_hc.16408 slog 0 ERR[src/pfe_drv.c:1529]:(DRIVER) 事件 1 - 驱动程序运行时出错:无法初始化平台   Jan 01 00:00:14.257 iopkt.16408 main_buffer 0 无法启动 /proc/boot/devnp-pfe-2.so:没有这样的设备   Jan 01 00:00:14.257 io_pkt_v6_hc.16408 slog 0 INF[src/pfe_drv.c:1302]:PFE 输入失败,PFE 驱动程序终止     数量 数量 数量 数量 数量 数量     Re: PFE on S32G A53 QNX ERROR 你好,@桑德尔伍德 我对迟复感到非常抱歉。 不确定问题是否已经解决? 请问您的 uboot 是否设置了环境变量 skip_scmi_reset_agent? 如果没有,请尝试设置如下内容:"setenv skip_scmi_reset_agent '1'" BR 切宁   Re: PFE on S32G A53 QNX ERROR 你好,@桑德尔伍德 感谢您的回复。 1.我建议查看 PFE 驱动程序版本代码包中包含的 " PFE_QNX_DRV_IntegrationManual.pdf ",并确保每个步骤(构建、运行驱动程序)都是正确的。 2.如果 DTB 文件在 Linux 中运行良好,那么 QNX 中的原始文件也应替换为该文件。 你能不能再试一次,并告诉我测试结果。 BR 切宁 Re: PFE on S32G A53 QNX ERROR 你好,@桑德尔伍德 感谢您的回复。 是的,我现在明白了。 我们会进行调查,有结果后再回复您。 BR 切宁 Re: PFE on S32G A53 QNX ERROR 1.pfe DDR 的位置不能使用 NXP 手册中提供的示例,必须更改为空闲位置,以防止与预留内存重叠。 2. 我还没做任何动态更改。我的运行命令是:io-pkt-v6-hc-p tcpip pkt_typed_mem=pfe_ddr-d /proc/boot/devnp-pfe-2.so pfe0_link=1000-1-3,pfe0_mac=025556000050,class_fw=/proc/boot/s32g_pfe_class. class.so pfe0_link=1000-1-3,pfe0_mac=025556000050,class_fw=/proc/boot/fw,util_fw=/proc/boot/ s32g_pfe_util.fw 我我没有做任何动态更改,也没有修改 uboot 的环境变量。Linux 和 QNX 使用相同的 uboot 映像。所以,我的理解是,QNX 上 Serdes 的配置应该与 Linux 相同,对吗? Re: PFE on S32G A53 QNX ERROR 你好,@桑德尔伍德 很高兴 ddr 问题得到了解决,您能告诉我们原因吗? 对于所提到的 ping 问题,您是否提到了下面的驱动程序限制: BR 切宁 Re: PFE on S32G A53 QNX ERROR 你好, 我们已经解决了 ddr 错误,但在 ping 时可能会出现新问题。 我们板中的 pfe0 通过 MAC-TO-MAC(SGMII 模式)直接连接到外部交换机。在 Linux 环境中,该链接是正常的,可以与外部环境正常通信,如 ping 正常。但用当前的 QNX 取代 Linux 后,Ping 问题就会出现。 在 Linux 中,我们更改了设备树并将 pfe0 配置为修复 sgmii 模式。我怀疑与此有关,但不知道如何在 QNX 中进行配置。 日志请见附件。 Re: PFE on S32G A53 QNX ERROR 160 是十六进制 0xa0,看来 pfe_ddr 是正常的 # pidin sys=asinfo Header size=0x00000108, Total Size=0x00001050, #Cpu=8, Type=257 Section:asinfo offset:0x00000b90 size:0x00000200 elsize:0x00000020 0000) 000000000000-0000ffffffffff o:ffff a:0010 p:100 c:0 n:/memory 0020) 000000000000-00000000ffffffff o:0000 a:0010 p:100 c:0 n:/memory/below4G 0040) 0000000080000000-00000000ffffff o:0020 a:0017 p:100 c:0 n:/memory/below4G/ram 0060) 0000000880000000-00000008dffffffff o:0000 a:0017 p:100 c:0 n:/memory/ram 0080) 00000000ff800000-00000000ff83afff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/atf 00a0) 0000000080000000-0000000083ffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/pfe_ddr 00c0) 0000000050800000-000000005080ffff o:0000 a:0003 p:100 c:0 n:/memory/gicd 00e0) 0000000050900000-00000000509fffff o:0000 a:0003 p:100 c:0 n:/memory/gicr 0100) 0000000088000080-0000000088007fff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/fdt 0120) 00000000800d10a8-00000000815fa8b3 o:0000 a:0005 p:100 c:0 n:/memory/imagefs 0140) 0000000080080fa0-00000000800d10a7 o:0000 a:0007 p:100 c:0 n:/memory/startup 0160) 00000000800d10a8-00000000815fa8b3 o:0000 a:0007 p:100 c:0 n:/memory/bootram 0180) 00000000a0000000-00000000a0007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01a0) 00000000a0014000-00000000ff7fffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01c0) 00000000ff83b000-00000000ffffffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01e0) 0000000880000000-00000008dd5e2fff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram Re: PFE on S32G A53 QNX ERROR 你好,@陈 感谢您的回复。返回代码请参见日志。 BR 檀木 Re: PFE on S32G A53 QNX ERROR 你好,@桑德尔伍德 谢谢你的帖子。 似乎内存映射不正确,请问是否有日志显示 as_add_containing() 调用成功? BR 切宁
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How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? I'm trying to use the newest Android SDK library to set my dynamic URL based on AES key, but I'm unable to do it. nxpnfcandroidlib-release-protected.aar This is my code override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x01) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) ntag424DNA.setPICCConfiguration(true) Log.i("MainActivity", "✅ PICC Configuration updated to enable SDM globally.") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeSDMFileSettings(ntag424DNA, 0x01) if (reader.isConnected) { reader.close() } } catch (e: Exception) { e.printStackTrace() } } } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_ABSOLUTE_URI, "https://domain.com?uid=04BB38D2AA1191&ctr=0001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa".toByteArray( Charset.forName("US-ASCII") ), ByteArray(0), ByteArray(0) ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Encrypted, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x0E.toByte() // Change access = always ) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated $fileNumber") } private fun changeSDMFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { val fileSettings = ntag424DNA.getFileSettings(fileNumber); fileSettings.isSDMEnabled = true; fileSettings.isUIDMirroringEnabled = true; fileSettings.piccDataOffset = intTo2ByteArray(51) fileSettings.sdmMacOffset = intTo2ByteArray(51) fileSettings.sdmMacInputOffset = intTo2ByteArray(51) fileSettings.sdmReadCounterOffset = intTo2ByteArray(51) fileSettings.uidOffset = intTo2ByteArray(51) fileSettings.sdmAccessRights = byteArrayOf(0x00, 0x00) Log.i("MainActivity", "Prepare for saving SDM changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated: SUN CMAC enabled on $fileNumber") } private fun intTo2ByteArray(value: Int): ByteArray { return byteArrayOf( ((value shr 😎 and 0xFF).toByte(), (value and 0xFF).toByte() ) } I know that the offset number doesn't match the position in the URL but whatever I'm changing, I'm still getting this error. It looks like, for some reason, these settings can not be saved by this method. ntag424DNA.changeFileSettings(fileNumber, fileSettings) This is the error message com.nxp.nfclib.exceptions.UsageException: Invalid Parameters! {Invalid Value for PICC Offset} Code examples Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? The issue was due to the wrong offset value. It seems ntag reserved 21 default index. Now we are trying to change factory 128 aes key and changekey() function didnt work for us @ukcas  Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? hey there, I am following this thread to set up JSON data, but it is not working for me. This is my first time working with hardware, which is making things much more challenging. I am using the NXP Android library and the sample Android application from here: https://www.nxp.com/design/design-center/software/rfid-developer-resources/taplinx-software-development-kit-sdk:TAPLINX Below is my code inside Sample_Application_Android/src/main/java/com/nxp/sampletaplinx/WriteActivity.java public static byte[] intTo2ByteArray(int value) { return new byte[] { (byte) (value & 0xFF), // LSB (byte) ((value >> 8) & 0xFF), // middle byte (byte) ((value >> 16) & 0xFF) // MSB }; } private void tag424DNACardLogic(INTAG424DNA ntag424DNA) { byte[] KEY_AES128_DEFAULT = new byte[] { (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, }; byte[] NTAG424DNA_APP_NAME = {(byte) 0xD2, (byte) 0x76, 0x00, 0x00, (byte) 0x85, 0x01, 0x01}; byte[] data ={ 0x73, 0x75, 0x73, 0x68, 0x69, 0x6C }; mStringBuilder.append("\n\n"); int timeOut = 2000; try { ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME); KeyData aesKeyData = new KeyData(); Key keyDefault = new SecretKeySpec(KEY_AES128_DEFAULT, "AES"); aesKeyData.setKey(keyDefault); ntag424DNA.authenticateEV2First(0, aesKeyData, null); mStringBuilder.append(getString(R.string.Authentication_status_true)); mStringBuilder.append("\n\n"); ntag424DNA.setPICCConfiguration(true); String jsonTemplate = "{\"uuid\":\"00000000000000\",\"counter\":\"000000\",\"cmac\":\"0000000000000000\",\"domain1\":" + 1 + ",\"domain2\":" + 1 + "}"; byte[] jsonBytes = jsonTemplate.getBytes("UTF-8"); NTAG424DNAFileSettings fs = new NTAG424DNAFileSettings( CommunicationMode.Plain, // or MAC/ENC depending on your security (byte) 0x0E, // Read access: Key 0 (byte) 0x0E, // Write access: Key 0 (byte) 0x0E, // Read/Write: Key 0 (byte) 0x00 // Change access: Free ); byte[] type = "U".getBytes("US-ASCII"); fs.setSDMEnabled(true); fs.setUIDMirroringEnabled(true); fs.setSDMReadCounterEnabled(true); byte[] bytes = new byte[] { (byte)0xE0, (byte)0x00, (byte)0x00 }; fs.setSdmAccessRights(bytes); byte[] uuidOffset = intTo2ByteArray(8); fs.setUidOffset(uuidOffset); byte[] readCounterOffset = intTo2ByteArray(35); fs.setSdmReadCounterOffset(readCounterOffset); byte[] macOffset = intTo2ByteArray(51); fs.setSdmMacInputOffset(uuidOffset); fs.setSdmMacOffset(macOffset); ntag424DNA.changeFileSettings(FILE_NUMBER, fs); // Create NDEF record NdefRecordWrapper record = new NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, type, new byte[0], // empty ID jsonBytes // payload (your JSON) ); // Wrap record into NDEF message NdefMessageWrapper msg = new NdefMessageWrapper(record); ntag424DNA.writeNDEF(msg); NxpLogUtils.save(); } catch (Exception e) { writeFailedMessage(); mStringBuilder.append(e.getMessage()); Log.i("MainActivity", "URI NDEF message written successful $msg " + e.getMessage() ); showMessage(mStringBuilder.toString(), PRINT); NxpLogUtils.save(); } }  would be great help if someone can assist me with this Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? Thanks for the help! You are right that my offset has the wrong values. This is what I have changed and now I can save settings.  override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x02) if (reader.isConnected) { reader.close() } } catch (e: Exception) { Log.e("MainActivity", e.localizedMessage ?: "No Error Message"); e.printStackTrace() } } } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Plain, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x00.toByte() // Change access = always ) fileSettings.isSDMEnabled = true fileSettings.isUIDMirroringEnabled = true fileSettings.isSDMReadCounterEnabled = true fileSettings.sdmAccessRights = byteArrayOf(0xfe.toByte(), 0xe1.toByte()) fileSettings.uidOffset = byteArrayOf(0x1A, 0x00, 0x00) fileSettings.sdmReadCounterOffset = byteArrayOf(0x2d, 0x00, 0x00) fileSettings.sdmMacOffset = byteArrayOf(0x39, 0x00, 0x00) fileSettings.sdmMacInputOffset = byteArrayOf(0x39, 0x00, 0x00) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("MainActivity", "🔐 File settings updated $fileNumber") } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val payload = byteArrayOf(0x04) + "noexample.xxxx?uid=00000000000000&ctr=000000&cmac=0000000000000000".toByteArray() val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, "U".toByteArray(StandardCharsets.US_ASCII), ByteArray(0), payload ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? Dear Rocky2, Please check document refered by jimmyvhan and datasheet.  Your offsets are overlapping, which is not permitted as per datasheet. Considering your desired URL. You have too less space for NFCCounter, which is 3 bytes. So below settings are suiting corrected URL. https://domain.com?uid=04BB38D2AA1191&ctr=000001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa  You shall use these parameters for SDM Configuration. You decide on Input data for CMAC calculation as well. We used UIDOffset as starting point for this example. fileSettings.sdmMacOffset = intTo2ByteArray(53) fileSettings.sdmMacInputOffset = intTo2ByteArray(22) fileSettings.sdmReadCounterOffset = intTo2ByteArray(41) fileSettings.uidOffset = intTo2ByteArray(22)  Best regards, TapLinx team Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? This document could be useful for you. NTAG 424 DNA and NTAG 424 DNA TagTamper features and hints
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NTAG424 DNA で CMAC、UID、COUNTER、RAND を有効にするにはどうすればいいですか? 最新の Android SDKs ライブラリを使用して、AES キーに基づいて動的 URL を設定しようとしていますが、できません。 nxpnfcandroidlib-release-protected.aar これは私のコードです override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x01) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) ntag424DNA.setPICCConfiguration(true) Log.i("MainActivity", "✅ PICC Configuration updated to enable SDM globally.") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeSDMFileSettings(ntag424DNA, 0x01) if (reader.isConnected) { reader.close() } } catch (e: Exception) { e.printStackTrace() } } } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_ABSOLUTE_URI, "https://domain.com?uid=04BB38D2AA1191&ctr=0001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa".toByteArray( Charset.forName("US-ASCII") ), ByteArray(0), ByteArray(0) ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Encrypted, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x0E.toByte() // Change access = always ) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated $fileNumber") } private fun changeSDMFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { val fileSettings = ntag424DNA.getFileSettings(fileNumber); fileSettings.isSDMEnabled = true; fileSettings.isUIDMirroringEnabled = true; fileSettings.piccDataOffset = intTo2ByteArray(51) fileSettings.sdmMacOffset = intTo2ByteArray(51) fileSettings.sdmMacInputOffset = intTo2ByteArray(51) fileSettings.sdmReadCounterOffset = intTo2ByteArray(51) fileSettings.uidOffset = intTo2ByteArray(51) fileSettings.sdmAccessRights = byteArrayOf(0x00, 0x00) Log.i("MainActivity", "Prepare for saving SDM changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated: SUN CMAC enabled on $fileNumber") } private fun intTo2ByteArray(value: Int): ByteArray { return byteArrayOf( ((value shr 😎 and 0xFF).toByte(), (value and 0xFF).toByte() ) } オフセット番号が URL 内のポジショニングと一致しないことはわかっていますが、何を変更してもこのエラーが発生します。何らかの理由で、この方法ではこれらの設定を保存できないようです。 ntag424DNA.changeFileSettings(fileNumber, fileSettings) これはエラーメッセージです com.nxp.nfclib.exceptions.UsageException: Invalid Parameters! {Invalid Value for PICC Offset} コード・サンプル Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この問題はオフセット値が間違っているために発生しました。ntag は 21 のデフォルト インデックスを予約しているようです。今、ファクトリー128 AESキーを変更しようとしていますが、changekey()関数は機能しませんでした。 @ukcas Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? ちょっと、そこ、 このThreadに従って JSON データを設定していますが、うまくいきません。ハードウェアを扱うのは初めてなので、非常に困難になっています。私は、NXP Android ライブラリと、ここからのサンプル Android アプリケーションを使用しています: https://www.nxp.com/design/design-center/software/rfid-developer-resources/taplinx-software-development-kit-sdk:TAPLINX 以下はSample_Application_Android/src/main/java/com/nxp/sampletaplinx/WriteActivity.java内のコードです。 public static byte[] intTo2ByteArray(int value) { return new byte[] { (byte) (value & 0xFF), // LSB (byte) ((value >> 8) & 0xFF), // middle byte (byte) ((value >> 16) & 0xFF) // MSB }; } private void tag424DNACardLogic(INTAG424DNA ntag424DNA) { byte[] KEY_AES128_DEFAULT = new byte[] { (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, }; byte[] NTAG424DNA_APP_NAME = {(byte) 0xD2, (byte) 0x76, 0x00, 0x00, (byte) 0x85, 0x01, 0x01}; byte[] data ={ 0x73, 0x75, 0x73, 0x68, 0x69, 0x6C }; mStringBuilder.append("\n\n"); int timeOut = 2000; try { ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME); KeyData aesKeyData = new KeyData(); Key keyDefault = new SecretKeySpec(KEY_AES128_DEFAULT, "AES"); aesKeyData.setKey(keyDefault); ntag424DNA.authenticateEV2First(0, aesKeyData, null); mStringBuilder.append(getString(R.string.Authentication_status_true)); mStringBuilder.append("\n\n"); ntag424DNA.setPICCConfiguration(true); String jsonTemplate = "{\"uuid\":\"00000000000000\",\"counter\":\"000000\",\"cmac\":\"0000000000000000\",\"domain1\":" + 1 + ",\"domain2\":" + 1 + "}"; byte[] jsonBytes = jsonTemplate.getBytes("UTF-8"); NTAG424DNAFileSettings fs = new NTAG424DNAFileSettings( CommunicationMode.Plain, // or MAC/ENC depending on your security (byte) 0x0E, // Read access: Key 0 (byte) 0x0E, // Write access: Key 0 (byte) 0x0E, // Read/Write: Key 0 (byte) 0x00 // Change access: Free ); byte[] type = "U".getBytes("US-ASCII"); fs.setSDMEnabled(true); fs.setUIDMirroringEnabled(true); fs.setSDMReadCounterEnabled(true); byte[] bytes = new byte[] { (byte)0xE0, (byte)0x00, (byte)0x00 }; fs.setSdmAccessRights(bytes); byte[] uuidOffset = intTo2ByteArray(8); fs.setUidOffset(uuidOffset); byte[] readCounterOffset = intTo2ByteArray(35); fs.setSdmReadCounterOffset(readCounterOffset); byte[] macOffset = intTo2ByteArray(51); fs.setSdmMacInputOffset(uuidOffset); fs.setSdmMacOffset(macOffset); ntag424DNA.changeFileSettings(FILE_NUMBER, fs); // Create NDEF record NdefRecordWrapper record = new NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, type, new byte[0], // empty ID jsonBytes // payload (your JSON) ); // Wrap record into NDEF message NdefMessageWrapper msg = new NdefMessageWrapper(record); ntag424DNA.writeNDEF(msg); NxpLogUtils.save(); } catch (Exception e) { writeFailedMessage(); mStringBuilder.append(e.getMessage()); Log.i("MainActivity", "URI NDEF message written successful $msg " + e.getMessage() ); showMessage(mStringBuilder.toString(), PRINT); NxpLogUtils.save(); } } 誰かがこれを手伝ってCANととても助かります Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 助けてくれてありがとう!私のオフセットの値が間違っているというのはその通りです。変更した内容はこれで、設定を保存CANようになりました。 override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x02) if (reader.isConnected) { reader.close() } } catch (e: Exception) { Log.e("MainActivity", e.localizedMessage ?: "No Error Message"); e.printStackTrace() } } } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Plain, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x00.toByte() // Change access = always ) fileSettings.isSDMEnabled = true fileSettings.isUIDMirroringEnabled = true fileSettings.isSDMReadCounterEnabled = true fileSettings.sdmAccessRights = byteArrayOf(0xfe.toByte(), 0xe1.toByte()) fileSettings.uidOffset = byteArrayOf(0x1A, 0x00, 0x00) fileSettings.sdmReadCounterOffset = byteArrayOf(0x2d, 0x00, 0x00) fileSettings.sdmMacOffset = byteArrayOf(0x39, 0x00, 0x00) fileSettings.sdmMacInputOffset = byteArrayOf(0x39, 0x00, 0x00) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("MainActivity", "🔐 File settings updated $fileNumber") } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val payload = byteArrayOf(0x04) + "noexample.xxxx?uid=00000000000000&ctr=000000&cmac=0000000000000000".toByteArray() val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, "U".toByteArray(StandardCharsets.US_ASCII), ByteArray(0), payload ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 親愛なるロッキー2様 jimmyvhan が参照しているドキュメントとデータシートを確認してください。 オフセットが重複していますが、これはデータシートでは許可されていません。 ご希望のURLを検討中です。NFCCounter のスペースが 3 バイトと少なすぎます。SO、以下の設定は修正された URL に適しています。 https://domain.com?uid=04BB38D2AA1191&ctr=000001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa SDM 構成にはこれらのパラメータを使用する必要があります。CMAC 計算のための入力データも決定します。この例では、UIDOffset を出発点として使用しました。 fileSettings.sdmMacOffset = intTo2ByteArray(53) fileSettings.sdmMacInputOffset = intTo2ByteArray(22) fileSettings.sdmReadCounterOffset = intTo2ByteArray(41) fileSettings.uidOffset = intTo2ByteArray(22) よろしくお願いします、 TapLinxチーム Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この文書はあなたにとって役に立つかもしれません。 NTAG 424 DNAとNTAG 424 DNA TagTamperの機能とヒント
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NTAG424 DNA で CMAC、UID、COUNTER、RAND を有効にするにはどうすればいいですか? 最新の Android SDKs ライブラリを使用して、AES キーに基づいて動的 URL を設定しようとしていますが、できません。 nxpnfcandroidlib-release-protected.aar これは私のコードです override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x01) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) ntag424DNA.setPICCConfiguration(true) Log.i("MainActivity", "✅ PICC Configuration updated to enable SDM globally.") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeSDMFileSettings(ntag424DNA, 0x01) if (reader.isConnected) { reader.close() } } catch (e: Exception) { e.printStackTrace() } } } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_ABSOLUTE_URI, "https://domain.com?uid=04BB38D2AA1191&ctr=0001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa".toByteArray( Charset.forName("US-ASCII") ), ByteArray(0), ByteArray(0) ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Encrypted, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x0E.toByte() // Change access = always ) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated $fileNumber") } private fun changeSDMFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { val fileSettings = ntag424DNA.getFileSettings(fileNumber); fileSettings.isSDMEnabled = true; fileSettings.isUIDMirroringEnabled = true; fileSettings.piccDataOffset = intTo2ByteArray(51) fileSettings.sdmMacOffset = intTo2ByteArray(51) fileSettings.sdmMacInputOffset = intTo2ByteArray(51) fileSettings.sdmReadCounterOffset = intTo2ByteArray(51) fileSettings.uidOffset = intTo2ByteArray(51) fileSettings.sdmAccessRights = byteArrayOf(0x00, 0x00) Log.i("MainActivity", "Prepare for saving SDM changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated: SUN CMAC enabled on $fileNumber") } private fun intTo2ByteArray(value: Int): ByteArray { return byteArrayOf( ((value shr 😎 and 0xFF).toByte(), (value and 0xFF).toByte() ) } オフセット番号が URL 内のポジショニングと一致しないことはわかっていますが、何を変更してもこのエラーが発生します。何らかの理由で、この方法ではこれらの設定を保存できないようです。 ntag424DNA.changeFileSettings(fileNumber, fileSettings) これはエラーメッセージです com.nxp.nfclib.exceptions.UsageException: Invalid Parameters! {Invalid Value for PICC Offset} コード・サンプル Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この問題はオフセット値が間違っているために発生しました。ntag は 21 のデフォルト インデックスを予約しているようです。今、ファクトリー128 AESキーを変更しようとしていますが、changekey()関数は機能しませんでした。 @ukcas Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? ちょっと、そこ、 このThreadに従って JSON データを設定していますが、うまくいきません。ハードウェアを扱うのは初めてなので、非常に困難になっています。私は、NXP Android ライブラリと、ここからのサンプル Android アプリケーションを使用しています: https://www.nxp.com/design/design-center/software/rfid-developer-resources/taplinx-software-development-kit-sdk:TAPLINX 以下はSample_Application_Android/src/main/java/com/nxp/sampletaplinx/WriteActivity.java内のコードです。 public static byte[] intTo2ByteArray(int value) { return new byte[] { (byte) (value & 0xFF), // LSB (byte) ((value >> 8) & 0xFF), // middle byte (byte) ((value >> 16) & 0xFF) // MSB }; } private void tag424DNACardLogic(INTAG424DNA ntag424DNA) { byte[] KEY_AES128_DEFAULT = new byte[] { (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, }; byte[] NTAG424DNA_APP_NAME = {(byte) 0xD2, (byte) 0x76, 0x00, 0x00, (byte) 0x85, 0x01, 0x01}; byte[] data ={ 0x73, 0x75, 0x73, 0x68, 0x69, 0x6C }; mStringBuilder.append("\n\n"); int timeOut = 2000; try { ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME); KeyData aesKeyData = new KeyData(); Key keyDefault = new SecretKeySpec(KEY_AES128_DEFAULT, "AES"); aesKeyData.setKey(keyDefault); ntag424DNA.authenticateEV2First(0, aesKeyData, null); mStringBuilder.append(getString(R.string.Authentication_status_true)); mStringBuilder.append("\n\n"); ntag424DNA.setPICCConfiguration(true); String jsonTemplate = "{\"uuid\":\"00000000000000\",\"counter\":\"000000\",\"cmac\":\"0000000000000000\",\"domain1\":" + 1 + ",\"domain2\":" + 1 + "}"; byte[] jsonBytes = jsonTemplate.getBytes("UTF-8"); NTAG424DNAFileSettings fs = new NTAG424DNAFileSettings( CommunicationMode.Plain, // or MAC/ENC depending on your security (byte) 0x0E, // Read access: Key 0 (byte) 0x0E, // Write access: Key 0 (byte) 0x0E, // Read/Write: Key 0 (byte) 0x00 // Change access: Free ); byte[] type = "U".getBytes("US-ASCII"); fs.setSDMEnabled(true); fs.setUIDMirroringEnabled(true); fs.setSDMReadCounterEnabled(true); byte[] bytes = new byte[] { (byte)0xE0, (byte)0x00, (byte)0x00 }; fs.setSdmAccessRights(bytes); byte[] uuidOffset = intTo2ByteArray(8); fs.setUidOffset(uuidOffset); byte[] readCounterOffset = intTo2ByteArray(35); fs.setSdmReadCounterOffset(readCounterOffset); byte[] macOffset = intTo2ByteArray(51); fs.setSdmMacInputOffset(uuidOffset); fs.setSdmMacOffset(macOffset); ntag424DNA.changeFileSettings(FILE_NUMBER, fs); // Create NDEF record NdefRecordWrapper record = new NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, type, new byte[0], // empty ID jsonBytes // payload (your JSON) ); // Wrap record into NDEF message NdefMessageWrapper msg = new NdefMessageWrapper(record); ntag424DNA.writeNDEF(msg); NxpLogUtils.save(); } catch (Exception e) { writeFailedMessage(); mStringBuilder.append(e.getMessage()); Log.i("MainActivity", "URI NDEF message written successful $msg " + e.getMessage() ); showMessage(mStringBuilder.toString(), PRINT); NxpLogUtils.save(); } } 誰かがこれを手伝ってCANととても助かります Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 助けてくれてありがとう!私のオフセットの値が間違っているというのはその通りです。変更した内容はこれで、設定を保存CANようになりました。 override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x02) if (reader.isConnected) { reader.close() } } catch (e: Exception) { Log.e("MainActivity", e.localizedMessage ?: "No Error Message"); e.printStackTrace() } } } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Plain, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x00.toByte() // Change access = always ) fileSettings.isSDMEnabled = true fileSettings.isUIDMirroringEnabled = true fileSettings.isSDMReadCounterEnabled = true fileSettings.sdmAccessRights = byteArrayOf(0xfe.toByte(), 0xe1.toByte()) fileSettings.uidOffset = byteArrayOf(0x1A, 0x00, 0x00) fileSettings.sdmReadCounterOffset = byteArrayOf(0x2d, 0x00, 0x00) fileSettings.sdmMacOffset = byteArrayOf(0x39, 0x00, 0x00) fileSettings.sdmMacInputOffset = byteArrayOf(0x39, 0x00, 0x00) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("MainActivity", "🔐 File settings updated $fileNumber") } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val payload = byteArrayOf(0x04) + "noexample.xxxx?uid=00000000000000&ctr=000000&cmac=0000000000000000".toByteArray() val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, "U".toByteArray(StandardCharsets.US_ASCII), ByteArray(0), payload ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 親愛なるロッキー2様 jimmyvhan が参照しているドキュメントとデータシートを確認してください。 オフセットが重複していますが、これはデータシートでは許可されていません。 ご希望のURLを検討中です。NFCCounter のスペースが 3 バイトと少なすぎます。SO、以下の設定は修正された URL に適しています。 https://domain.com?uid=04BB38D2AA1191&ctr=000001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa SDM 構成にはこれらのパラメータを使用する必要があります。CMAC 計算のための入力データも決定します。この例では、UIDOffset を出発点として使用しました。 fileSettings.sdmMacOffset = intTo2ByteArray(53) fileSettings.sdmMacInputOffset = intTo2ByteArray(22) fileSettings.sdmReadCounterOffset = intTo2ByteArray(41) fileSettings.uidOffset = intTo2ByteArray(22) よろしくお願いします、 TapLinxチーム Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この文書はあなたにとって役に立つかもしれません。 NTAG 424 DNAとNTAG 424 DNA TagTamperの機能とヒント
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PFE on S32G A53 QNX ERROR     Hi,NXP experts We have a custom board that we want to run QNX and PFE drivers on. But we have encountered the following problem and would like to ask PFE experts to help analyze it.     software information: PFE QNX driver version: 1.8.0 PFE FW version: 1.11.0 QNX SDP version: 7.1.0 BSP version of QNX S32G399A: BSP_nxp-s32g-rdb3_br-710_be-710_SVN996606_JBN10   hardware information: The difference in hardware between us and the NXP S32G399ARDB3 EVN board is that DDR has been changed to 2GB, and we have already adapted it in Linux, and the pfe Ethernet driver is normal. The changes are as follows:           1. Changes in images/s32g399a-rdb.build file,   2. Changes in src\hardware\startup\boards\s32g\s32g399a-rdb\s32g_init_raminfo.c file:     3. Other insignificant changes, unrelated to the PFE driver.       My test commands are: # slog2info -c   # slog2info -w & # io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw   However, after running, the error message appears.Log is here. -------------------Appendix------------------     NOTICE:  The list of clocks found enabled during the SCMI agent reset command: NOTICE:         linflex_lin NOTICE:         usdhc_core board_smp_num_cpu: 8 cores MMU: 16-bit ASID 40-bit PA TCR_EL1=b5183519 ARM GIC-500 r1p1, arch v3.0 detected board_smp_num_cpu: 8 cores board_smp_num_cpu: 8 cores No SPI intrinfo. Add default entry for 32 -> 575 vectors, Ok cpu0: MPIDR=80000000 cpu0: MIDR=410fd034 Cortex-A53 r0p4 cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu0: L1 Icache 32K linesz=64 set/way=256/2 cpu0: L1 Dcache 32K linesz=64 set/way=128/4 cpu0: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_num_cpu: 8 cores   A53 CORE CLOCK : 1000MHz DDR CLOCK      : 800MHz SERDES CLOCK   : 2000MHz LINFLEXD CLOCK : 125MHz GMAC TS CLOCK  : 48MHz SPI CLOCK      : 48MHz QSPI CLOCK     : 800MHz SDHC CLOCK     : 800MHz   Loading IFS...decompressing...done board_smp_start: cpu_cluster_id: 0, cpu_id: 1 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 1 (0)  running cpu1: MPIDR=80000001 cpu1: MIDR=410fd034 Cortex-A53 r0p4 cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu1: L1 Icache 32K linesz=64 set/way=256/2 cpu1: L1 Dcache 32K linesz=64 set/way=128/4 cpu1: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 0, cpu_id: 2 NOTTCE:  S32 T TA: s323pw_pdomrin_on: bootingnup cor  2u 0) nning cpu2: MPIDR=80000002 cpu2: MIDR=410fd034 Cortex-A53 r0p4 cpu2: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu2: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu2: L1 Icache 32K linesz=64 set/way=256/2 cpu2: L1 Dcache 32K linesz=64 set/way=128/4 cpu2: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 0, cpu_id: 3 ngTICE:  SS32TT-A:: 32_pwr_rodain_on: booting up cpre 3 (0n cpu3: MPIDR=80000003 cpu3: MIDR=410fd034 Cortex-A53 r0p4 cpu3: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu3: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu3: L1 Icache 32K linesz=64 set/way=256/2 cpu3: L1 Dcache 32K linesz=64 set/way=128/4 cpu3: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 0 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 4 (0) NOTICE:  S32 TF-A: s32_pwr_domain_on_finish: cpu 4 running cpu4: MPIDR=80000100 cpu4: MIDR=410fd034 Cortex-A53 r0p4 cpu4: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu4: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu4: L1 Icache 32K linesz=64 set/way=256/2 cpu4: L1 Dcache 32K linesz=64 set/way=128/4 cpu4: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 1 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 5 (0) cpu 5 running cpu5: MPIDR=80000101 cpu5: MIDR=410fd034 Cortex-A53 r0p4 cpu5: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu5: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu5: L1 Icache 32K linesz=64 set/way=256/2 cpu5: L1 Dcache 32K linesz=64 set/way=128/4 cpu5: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 2 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 6 (0) nning cpu6: MPIDR=80000102 cpu6: MIDR=410fd034 Cortex-A53 r0p4 cpu6: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu6: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu6: L1 Icache 32K linesz=64 set/way=256/2 cpu6: L1 Dcache 32K linesz=64 set/way=128/4 cpu6: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 3 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 7 (0) 7 running cpu7: MPIDR=80000103 cpu7: MIDR=410fd034 Cortex-A53 r0p4 cpu7: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu7: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu7: L1 Icache 32K linesz=64 set/way=256/2 cpu7: L1 Dcache 32K linesz=64 set/way=128/4 cpu7: L2 Unified 1024K linesz=64 set/way=1024/16   System page at phys:00000000a0010000 user:ffffff8040315000 kern:ffffff8040311000 Starting next program at vffffff8060097300 ClockCycles samples:  0 62957977  1 62957977  2 62957978  3 62957977  4 62957977  5 62957977  6 62957977  7 62957977 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the NXP S32G399A RDB Board!! Starting watchdog... Starting serial driver ... Starting Networking driver (/dev/socket)... Starting SPI driver (/dev/spi0,1,2,3,4,5)... Starting I2C 0/1/2/3/4 driver (/dev/i2c0,1,2,3,4)... Starting USDHC0 memory card driver... Path=Starting CAN driver... 0 - imx  target=0 lun=0     Direct-Access(0) - SDMMC: AAM20E Rev: 1.0 # # # # slog2info -c   Process 4117 (slog2info) exited status=0. ghccu# slog2info -w & [1] 12309                                           random.4                  low     0  -----UNSYNC-----                                           random.4                 high     0  -----UNSYNC----- Jan 01 00:00:00.022                      console.3                           0  -----ONLINE-----                                          console.3                  out     0  -----UNSYNC----- Jan 01 00:00:00.027                       random.4                           0  -----ONLINE-----                                           random.4              default     0  -----UNSYNC----- Jan 01 00:00:00.028                    random.4..0                           0  -----ONLINE-----                                        random.4..0                 slog     0  -----UNSYNC----- Jan 01 00:00:00.050             devc_serlinflexd.7                           0  -----ONLINE-----                                 devc_serlinflexd.7                 slog     0  -----UNSYNC----- Jan 01 00:00:00.055                   spi_master.8                           0  -----ONLINE-----                                       spi_master.8               normal     0  -----UNSYNC----- Jan 01 00:00:00.059                   spi_master.9                           0  -----ONLINE-----                                       spi_master.9               normal     0  -----UNSYNC----- Jan 01 00:00:00.063                  spi_master.10                           0  -----ONLINE-----                                      spi_master.10               normal     0  -----UNSYNC----- Jan 01 00:00:00.067                  spi_master.11                           0  -----ONLINE-----                                      spi_master.11               normal     0  -----UNSYNC----- Jan 01 00:00:00.088             devb_sdmmc_mx8x.17                           0  -----ONLINE-----                                 devb_sdmmc_mx8x.17                 slog     0  -----UNSYNC----- Jan 01 00:00:04.268                       qconn.20                           0  -----ONLINE-----                                           qconn.20                 slog     0  -----UNSYNC----- # # # # io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw # Jan 01 00:00:14.060                    iopkt.16408                           0  -----ONLINE----- Jan 01 00:00:14.060                    iopkt.16408          main_buffer*     0  detect_armv8ce_hw: armv8ce is supported! Jan 01 00:00:14.061                    iopkt.16408          main_buffer      0  tcpip starting Jan 01 00:00:14.062                    iopkt.16408          main_buffer      0  smmu support is disabled Jan 01 00:00:14.063                    iopkt.16408          main_buffer      0  initializing IPsec... Jan 01 00:00:14.063                    iopkt.16408          main_buffer      0   done   Jan 01 00:00:14.064                    iopkt.16408          main_buffer      0  IPsec: Initialized Security Association Processing.   Jan 01 00:00:14.067                    iopkt.16408          main_buffer      0  /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw Jan 01 00:00:14.068             io_pkt_v6_hc.16408                           0  -----ONLINE----- Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog*     0  INF[src/pfe_drv.c:1346]: VERSION INFO         Driver version: 1.8.0         Driver commit hash: 57b6eefdb35cbff7a43ecfbdca3334760b1d0553         PFE_CFG_MULTI_INSTANCE_SUPPORT: 0         PFE_CFG_LOCAL_IF: 6         PFE_CFG_MASTER_IF: 6         PFE_CFG_SC_HIF: 1         PFE_CFG_HIF_RING_LENGTH: 256         PFE_CFG_PFE0_PROMISC: 1         PFE_CFG_PFE1_PROMISC: 1         PFE_CFG_PFE2_PROMISC: 1     Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1353]: --- Safe IRQ enabled. No InterrupAttach() or InterruptAttach_r() allowed.   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:94]: 45724 bytes read   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:100]: Loaded firmware file: /proc/boot/s32g_pfe_class.fw   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:94]: 23352 bytes read   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:100]: Loaded firmware file: /proc/boot/s32g_pfe_util.fw   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe1/EMAC1 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe2/EMAC2 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1467]: Issuing PFE peripheral reset...   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1468]: PFE reset OK.   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2826]: PFE CBUS p0x46000000 mapped @ v0x1e2a574000 (0x1000000 bytes)   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2831]: HW version 0x101   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_hw_feature.c:95]: Silicon S32G3   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  WRN[hw/s32g/pfe_platform_master.c:2843]: Fail-Stop mode disabled   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2093]: PFE_ERRORS:Parity instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2108]: PFE_ERRORS:Watchdog instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2124]: PFE_ERRORS:Bus Error instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2137]: PFE_ERRORS:FW Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2150]: PFE_ERRORS:Host Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2163]: PFE_ERRORS:Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2176]: PFE_ERRORS:ECC Err instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:1097]: BMU1 buffer base: p0xc0000000   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[src/oal_mm_qnx.c:98]: (DRIVER) event 1 - Driver runtime error: mmap64() failed: 1   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[src/oal_mm_qnx.c:171]: (DRIVER) event 1 - Driver runtime error: Can't get memory block   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[hw/s32g/pfe_platform_master.c:1125]: (DRIVER) event 1 - Driver runtime error: Unable to get BMU2 pool memory   Jan 01 00:00:14.256             io_pkt_v6_hc.16408                 slog      0  ERR[src/pfe_drv.c:1529]: (DRIVER) event 1 - Driver runtime error: Unable to initialize the platform   Jan 01 00:00:14.257                    iopkt.16408          main_buffer      0  Unable to init /proc/boot/devnp-pfe-2.so: No such device   Jan 01 00:00:14.257             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1302]: PFE entry failed, PFE driver terminated     # # # # # #     Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  I feel very sorry for late response. Not sure if the issue has been resolved? May I know if there was a environment variable skip_scmi_reset_agent set in your uboot? If not, try setting the following: "setenv skip_scmi_reset_agent '1'" BR Chenyin   Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for the reply. 1. I suggest reviewing the "PFE_QNX_DRV_IntegrationManual.pdf", which is included in PFE driver release package and assure that each step(Building, Running driver) is correct. 2. If the DTB file worked well in Linux, then the original one in QNX should be replaced with it. Would you mind trying it again and let me know the test result. BR Chenyin Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for you reply. Yes, I understand the situation now. Will investigate it and reply you later when there are any findings. BR Chenyin Re: PFE on S32G A53 QNX ERROR 1.The location of the pfe DDR cannot use the example provided in the NXP manual and must be changed to an idle location to prevent overlap with the reserved memory. 2.I haven't made any dynamic changes.My run cmd is:io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so pfe0_link=1000-1-3,pfe0_mac=025556000050,class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw And I did not make any dynamic changes, I did not modify the environment variables of uboot. Linux and QNX use the same uboot image. So, I understand that the configuration of Serdes on QNX should be the same as Linux, right?  Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Glad that the ddr issue resolved, would you mind sharing the reasons? For the ping issue mentioned, have you mentioned the driver limitation below: BR Chenyin Re: PFE on S32G A53 QNX ERROR Hi, We have resolved the ddr error, but there may be an new issue during ping. The pfe0 in our board is directly connected to the external swtich through MAC-TO-MAC(SGMII MODE). In a Linux environment, this link is normal and can communicate with the external environment normally, such as ping being OK. But after replacing Linux with the current QNX, the ping problem will occur. In Linux, we changed the device tree and configured pfe0 to fix sgmii mode. I suspect it's related to this, but I don't know how to configure it in QNX。 The log please see the attach. Re: PFE on S32G A53 QNX ERROR 160 is hex 0xa0,it seems that pfe_ddr is ok # pidin sys=asinfo Header size=0x00000108, Total Size=0x00001050, #Cpu=8, Type=257 Section:asinfo offset:0x00000b90 size:0x00000200 elsize:0x00000020 0000) 0000000000000000-0000ffffffffffff o:ffff a:0010 p:100 c:0 n:/memory 0020) 0000000000000000-00000000ffffffff o:0000 a:0010 p:100 c:0 n:/memory/below4G 0040) 0000000080000000-00000000ffffffff o:0020 a:0017 p:100 c:0 n:/memory/below4G/ram 0060) 0000000880000000-00000008dfffffff o:0000 a:0017 p:100 c:0 n:/memory/ram 0080) 00000000ff800000-00000000ff83afff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/atf 00a0) 0000000080000000-0000000083ffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/pfe_ddr 00c0) 0000000050800000-000000005080ffff o:0000 a:0003 p:100 c:0 n:/memory/gicd 00e0) 0000000050900000-00000000509fffff o:0000 a:0003 p:100 c:0 n:/memory/gicr 0100) 0000000088000080-0000000088007fff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/fdt 0120) 00000000800d10a8-00000000815fa8b3 o:0000 a:0005 p:100 c:0 n:/memory/imagefs 0140) 0000000080080fa0-00000000800d10a7 o:0000 a:0007 p:100 c:0 n:/memory/startup 0160) 00000000800d10a8-00000000815fa8b3 o:0000 a:0007 p:100 c:0 n:/memory/bootram 0180) 00000000a0000000-00000000a0007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01a0) 00000000a0014000-00000000ff7fffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01c0) 00000000ff83b000-00000000ffffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01e0) 0000000880000000-00000008dd5e2fff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram Re: PFE on S32G A53 QNX ERROR Hello, @Chen  Thanks for reply.The return code see the log. BR SandalWood  Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for the post. Seems the memory is not correctly mapped, may I know if there is a log indicating that as_add_containing() was successful called? BR Chenyin
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使用 UUU 闪存 i.MX8MM SD 卡的问题 我一直在尝试在 i.MX8MM 上闪存 SD 卡,但遇到了一些问题。我查看了文档,但并没有完全解开我的困惑。 关于 UUU,我已经下载了最新的 1.4.127 版:https://github.com/NXPmicro/mfgtools/releases/tag/uuu_1.4.127 而且我还下载了最新的预构建的 Linux 二进制文件 L5.10.9_1.0.0_MX8MM:https://www.nxp.com/webapp/Download?colCode=L5.10.9_1.0.0_MX8MM& apptype=License 我使用 UUU 通过以下方式将这个 5.10 Linux 版本闪存到我的 eMMC 中: uuu.exe uuu.auto 闪烁和启动都很正常。然后,我尝试通过更新 uuu.auto 文件将其闪存到 SD 卡,具体方法如下: # SD Programming: FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${sd_dev} FB: ucmd mmc dev ${sd_dev} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk FB: ucmd if env exists sd_ack; then ; else setenv sd_ack 0; fi; FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 FB: done # Emmc programming: #FB: ucmd setenv fastboot_dev mmc #FB: ucmd setenv mmcdev ${emmc_dev} #FB: ucmd mmc dev ${emmc_dev} #FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic #FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk #FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; #FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 #FB: done 在以下步骤中失败了: uuu.exe uuu.auto uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.4.127-0-g08c58c9 Success 0 Failure 1 2:2 7/ 8 [ ] FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 这让我觉得我不能简单地把一个换成另一个。所以我的问题是,如何使用 uuu 将 v5.10 预发布的 Linux 二进制文件闪存到 i.mx8mm EVK 上的 SD 卡中? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Issue flashing i.MX8MM SD card with UUU 我同意,UUU 的文档非常少,如果不反复试验,很难使用。 如果恩智浦能派一名以英语为母语的应用工程师对其进行彻底更新,提供适当的使用案例,并采用标准的 Linux 风格命令行帮助语法,用户将受益匪浅。 我可以帮忙,但自己没有足够的业余时间...... Re: Issue flashing i.MX8MM SD card with UUU 使用脚本没有问题。 你需要的是常见的基本知识。 因为从"FB: ucmd mmc partconf${sd_dev} ${sd_ack} 1 0", 可以了解到你对 emmc 和 SD 卡一无所知,因为你不知道 WIC。 下面是闪存 SD 卡的脚本。uuuuuu.sd.auto,即可使用。 uuu.sd.auto uuu_version 1.2.39 # 此命令将在 i.mx6/7 i.mx8MM、i.mx8MQ SDP: 启动 -f imx-boot-imx-boot-imx8mmevk-sd.bin-flash_evk 时 # 这个命令将在 ROM 支持直播模式时运行 # i.mx8QXP,i.mx8QM SDPS:启动 -f imx- 启动-imx-启动-imx8mmevk-sd.bin-flash_ev k # 使用 SPL 时将运行这些命令,如果没有 spl # SDPU 将被弃用,则跳过这些命令。请使用 SDPV 代替 SDPU # { SDPU:延迟 1000 SDPU:write -f imx-boot-imx8mmevk-sd.bin-flash_evk-offset 0x57c00 SDPU: jump # } # 这些命令将在使用 SPL 时运行,如果没有 spl 则会跳过 # if(SPL 支持 SDPV) # {SDPV:延迟 1000 SDP V:write-f imx-boot-imx8mmevk-sd.bin-flash_evk -skipspl SDPV: jump # } FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev${emmc_sd} FB: ucmd mmc dev${emmc_sd} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: 已完成 Re: Issue flashing i.MX8MM SD card with UUU 要想知道什么是 wic,你就应该掌握 yocto 知识。 而 wic 与 .sdcard 相同。 Re: Issue flashing i.MX8MM SD card with UUU 谢谢您的建议。如果通过 `.sdcard` 文件闪存,文档和 `uuu` 输出都会提到 sdcard: sd_all burn whole image to sd card arg0: _flash.bin arg1: _rootfs.sdcard 显然,在这种情况下,它是一个 `.wic` 文件。是否有地方提到过,而我却忽略了? 第二个问题:在内置命令起作用的同时,uuu.auto 文件也可以用于 SD 卡刷机吗? Re: Issue flashing i.MX8MM SD card with UUU 使用 uuu 版本命令只需要一个命令行 uuu -b sd_all imx-启动-imx8mmevk-sd.bin-flash_evkimx-image-multimedia-imx8mmevk.wic 建议阅读 uuu 手册或键入 uuu(不带参数)以显示帮助
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k32l2b31 writing to LPUART1->STAT |= (1<<25) cause semihost_hardfault i want to activate LIN Break detection on k32l2b31  bit LKDE must be set in status register i try LPUART1->STAT |= (1<<25) but it appear "semihost_hardfault" on debug who knows why ? best regards Re: k32l2b31 writing to LPUART1->STAT |= (1<<25) cause semihost_hardfault The "semihost_hardfault" when activating LIN break detection on the K32L2B31 most certainly suggests a problem that extends beyond simply setting the 'LKDE' bit. Possible causes include faulty LPUART clock configuration, accessing the peripheral before proper activation, memory access violations caused by an invalid base address, wrongly configured LIN break interrupts without a handler, or problems with the debugger/semihosting configuration. Before enabling LIN break detection, debug the initialization code, validate the base address, step through code with a debugger, check interrupts, simplify your code, and reference the datasheet to guarantee proper peripheral configuration. pa turnpike ez pass login Re: k32l2b31 writing to LPUART1->STAT |= (1<<25) cause semihost_hardfault The "semihost_hardfault" when enabling LIN break detection on the K32L2B31 likely indicates a problem beyond just setting the `LKDE` bit. Potential causes include incorrect LPUART clock configuration, accessing the peripheral before proper initialization, memory access violations due to a wrong base address, improperly configured LIN break interrupts without a handler, or issues with the debugger/semihosting setup. Debug by reviewing initialization code, verifying the base address, stepping through code with a debugger, checking interrupts, simplifying your code, and consulting the datasheet to ensure correct peripheral setup before enabling LIN break detection.
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UUUでi.MX8MM SDカードをフラッシュする際の問題 i.MX8MM で SD カードをフラッシュしようとしましたが、いくつか問題が発生しました。ドキュメントを調べましたが、私の混乱は完全には解消されませんでした。 UUU については、最新の 1.4.127 をダウンロードしました。https://github.com/NXPmicro/mfgtools/releases/tag/uuu_1.4.127 また、最新のビルド済み Linux バイナリ L5.10.9_1.0.0_MX8MM もダウンロードしました: https://www.nxp.com/webapp/Download?colCode=L5.10.9_1.0.0_MX8MM&appType=license 私は UUU を使用して、次の方法でこの 5.10 Linux リリースを eMMC にフラッシュしました。 uuu.exe uuu.auto 問題なく点滅し、起動しました。次に、次のように uuu.車載 ファイルを更新するだけで、これを SD カードにフラッシュしようとしました。 # SD Programming: FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${sd_dev} FB: ucmd mmc dev ${sd_dev} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk FB: ucmd if env exists sd_ack; then ; else setenv sd_ack 0; fi; FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 FB: done # Emmc programming: #FB: ucmd setenv fastboot_dev mmc #FB: ucmd setenv mmcdev ${emmc_dev} #FB: ucmd mmc dev ${emmc_dev} #FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic #FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk #FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; #FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 #FB: done これは次のステップで失敗しました: uuu.exe uuu.auto uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.4.127-0-g08c58c9 Success 0 Failure 1 2:2 7/ 8 [ ] FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 つまり、単純にどちらかを他のものと交換することはCANないと思うのです。私の質問は、uuu を使用して、v5.10 プレリリース Linux バイナリを i.MX8MM EVK の SD カードにフラッシュするにはどうすればよいかということです。 i.MX 8M | i.MX 8M ミニ | i.MX 8M ナノ Re: Issue flashing i.MX8MM SD card with UUU UUU のドキュメントは非常に乏しく、試行錯誤を繰り返さないと使いにくいということに同意します。 NXP が英語を母国語とするアプリケーション エンジニアを配置し、徹底的に更新して適切な使用例を提供し、標準的な Linux スタイルのコマンド ライン ヘルプ構文を採用すれば、ユーザーには大きなメリットがもたらされるでしょう。 手伝うことはCANのですが、私自身に十分な自由時間がありません... Re: Issue flashing i.MX8MM SD card with UUU スクリプトを使用しても問題ありません。 必要なのは共通の基本的な知識です。 「FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0」から、WIC について知らないのと同じように、emmc と SD カードについても知識がないことがわかります。 以下は SD カードをフラッシュするためのスクリプトです。uuu uuu.sd.車載 を使って使用します。 uuu.sd.車載 uuu_バージョン 1.2.39 # このコマンドは、i.MX6/7、i.MX8MM、i.MX8MQの場合に実行されます。 SDP: ブート -f imx-boot-imx8mmevk-sd.bin-flash_evk # このコマンドはROMがストリームモードをサポートしているときに実行されます # i.MX8QXP、i.MX8QM SDPS: boot -f imx-boot-imx8mmevk-sd.bin-flash_evk # これらのコマンドはSPLを使用するときに実行され、SPLがない場合はスキップされます # SDPU は廃止されます。SDPUの代わりにSDPVを使用してください # { SDPU: 遅延1000 SDPU: -f imx-boot-imx8mmevk-sd.bin-flash_evk を書き込みます-オフセット 0x57c00 SDPU: ジャンプ # } # これらのコマンドはSPLを使用するときに実行され、SPLがない場合はスキップされます # if (SPL は SDPV をサポート) # { SDPV: 遅延1000 SDPV: -f imx-boot-imx8mmevk-sd.bin-flash_evk を書き込みます-スキップスプル SDPV: ジャンプ # } FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${emmc_sd} FB: ucmd mmc dev ${emmc_sd} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: 完了 Re: Issue flashing i.MX8MM SD card with UUU WIC が何であるかを知るには、yocto の知識が必要です。 wic は .sdcard と同じです。 Re: Issue flashing i.MX8MM SD card with UUU ご意見ありがとうございます。ドキュメントと `uuu` 出力はどちらも、`.sdcard` ファイル経由でフラッシュされた場合は SD カードについて言及しています。 sd_all burn whole image to sd card arg0: _flash.bin arg1: _rootfs.sdcard 明らかにこのCASEは `.wic` ファイルでした。それは私が見逃したどこかに記載されていますか? 2 番目の質問: 組み込みコマンドが機能する場合、SD カードのフラッシュに uuu.車載 ファイルも使用できますか? Re: Issue flashing i.MX8MM SD card with UUU uuu組み込みコマンドを使用した1つのコマンドラインのみ uuu -b sd_all imx-boot-imx8mmevk-sd.bin-flash_evkimx-image-multimedia-imx8mmevk.wic uuuのマニュアルを読むか、パラメータなしでuuuと入力してヘルプを表示することをお勧めします。
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SWO on S32K344 with S32 Design Studio Hi is there any complete example how to make SWO running using S32 design studio? How to configure pinMUX, clocks, etc? I've tried multiple examples with J-link and PEMicro debuggers, but with no success. I've been using also retarget_itm.c library for ITM configuration (delivered by NXP).  Re: SWO on S32K344 with S32 Design Studio Hi @Julián_AragónM, Has this issue been resolved? I am encountering the same problem, where the MCU enters a hard fault after configuring the TPIU registers, and J-Link is also unable to write data to these registers. Could this be due to some safety protection? Is there any additional configuration I need to perform before writing to these TPIU registers? I would greatly appreciate any help or insights. Re: SWO on S32K344 with S32 Design Studio Hi @jakub-holoubek, I have sent you a private message through the community. Re: SWO on S32K344 with S32 Design Studio Hi @Julián_AragónM, ok thanks. 🙂 I'm aware of that retarget_itm library. However my suspicion is that there is some issue with TPIU related registers. Which are probably accessed by debugger itself: Cortex m7 TPIU registersCortex m7 TPIU registers In case I'm setting them from the code the MCU goes to hard fault. And same happens also in case I connect the debugger (tried J-Link, PEMicro, Lauterbach) and want to enable the SWO through debugger's settings - MCU goes into hard fault.  Re: SWO on S32K344 with S32 Design Studio Hi @jakub-holoubek, I apologize for the late reply. This may be an issue with the implementation of trace and our architecture. There is an internal discussion with the SW team now. I will try to update you if anything else comes up. As of now, you can create a new project in S32DS with prinft ITM, but the retarget_itm library does not work as expected. Best regards, Julián Re: SWO on S32K344 with S32 Design Studio Hi, @Julián_AragónM, yes, I'm using S32K3-T-BOX board. Those TRACE signals are valid for ETM interface. However I need to communicate using ITM through JTAG_TDO pin - so it is routed to JTAG connector. That pin is used for SWO communication in case the SWD protocol is used instead of JTAG - which is my case. Re: SWO on S32K344 with S32 Design Studio Hi @jakub-holoubek, Are you using the S32K344 evaluation board? By default, all TRACE signals are DISABLED. Best regards, Julián Re: SWO on S32K344 with S32 Design Studio Hi @Julián_AragónM, thanks for reply. I've checked that tutorials. One issue I've got is that MCU goes to the hard fault once I want to write/read some TPIU registers. For example this code: *((volatile unsigned *)(ITM_BASE + 0x400F0)) = 0x00000002; /* "Selected PIN Protocol Register": Select which protocol to use for trace output (2: SWO NRZ, 1: SWO Manchester encoding) */ *((volatile unsigned *)(ITM_BASE + 0x40010)) = SWOPrescaler; /* "Async Clock Prescaler Register". Scale the baud rate of the asynchronous output */ Once trying to set one of those registers the MCU goes to hard fault. I've found in reference manual of ARM M7 core, that TPIU is not configured in M7 cores - can you confirm that?  Or is there any other register I have to set before writing into TPIU related registers? Re: SWO on S32K344 with S32 Design Studio Hi @jakub-holoubek, I believe this is a question for SEGGER instead. There is no other example for configuring this with S32DS specifically, but you can use the following posts as guidance:  Tutorial: Using Single Wire Output SWO with ARM Cortex-M and Eclipse | MCU on Eclipse. PEmicro Forums Topic: Problem with ITM-printf in S32DS using Multilink ACP Rev.B Solved: SWV (ITM --> SWO) on S32k324 not working - NXP Community Also, SEGGER has a dedicated page in their knowledge base for their J-Link SWO Viewer: J-Link SWO Viewer - SEGGER Knowledge Base & UM08001 J-Link / J-Trace User Guide - SEGGER Knowledge Base. Best regards, Julián Re: SWO on S32K344 with S32 Design Studio For example in this article: Single Wire Output (SWO) support within S32 Design Studio, enabled by PEmicro's GDB Server It would be nice have more details, including sources. 
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Wire ACK Fault in DAP access Hello, I have just recently installed McuExpresso 10.3.0. Previously I was using McuExpresso 10.0.2. When I downloaded the latest SDK for FRDM K64 and tried to debug a demo example, I got this error. Failed on connect: Nn(05). Wire ACK Fault in DAP access I dont understand what is wrong. Kindly, help me with this. Thanks, Saad. Re: Re:  Wire ACK Fault in DAP access Iam also facing the same issue when iam trying to connect to IMXRT1064 using SWD i keep getting error : Wire Ack Fault in DAP Access. Kindly help me with this. Re: Wire ACK Fault in DAP access Thanks for trying. It worked in several cases on my side. Maybe indeed your device is permanently bricked. Re: Wire ACK Fault in DAP access Tried the script....no dice.  But thanks for pointing me in that direction. Re: Wire ACK Fault in DAP access As the screenshot indicates: "Resurrect locked Kinetis device": this feature exists for Kinetis devices only. If you happen to have an LPC: try erasing the flash from the bootloader, or you might use a recover script like described here: https://mcuoneclipse.com/2023/07/25/linkserver-scripting-and-how-to-recover-mcus-with-a-script/ Re: Wire ACK Fault in DAP access In mcuxpressoide-11.7.1_9221 there is no such thing as "Resurrect locked ..." Re: Wire ACK Fault in DAP access I have the same issue, do you find a solution? Re: Wire ACK Fault in DAP access @CBI   Did you manage to find the solution for this? I am facing the same problem and tried the same solution but it is not working for me as well Re: Wire ACK Fault in DAP access Hi, We are also having the same problem as CBI. Is your problem resolved? If so please post it here. Thank you very much. Re: Wire ACK Fault in DAP access The Problem has not been solved for me... I search a solution !!! Re: Wire ACK Fault in DAP access Hi all,  I am young in this forum Meanwhile When I perform this  I have the following result The detail infos in the console: Executing flash operation 'Resurrect locked Kinetis device' (Resurrect locked Kinetis device) - Mon Mar 01 16:30:41 CET 2021 Checking MCU info... Scanning for targets... Executing flash action... MCUXpresso IDE RedlinkMulti Driver v11.3 (Jan 11 2021 16:41:13 - crt_emu_cm_redlink.exe build 9) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/binard/Documents/MCUXpressoIDE_11.3.0_5222/workspace/frdmkw38_heart_rate_sensor_freertos/Debug\MKW38A512xxx4.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Connecting to probe 1 core 0 (using server started externally) reports: 'Ee(42). Could not connect to core.' Retrying... Reconnected to existing LinkServer process. Server OK but no connection to probe 1 core 0 (after 3 attempts) - Ee(42). Could not connect to core. ============= SCRIPT: kinetismasserase.scp ============= Kinetis Mass Erase Script Error: Wire Ack Fault - target connected? Assert NRESET Reset pin state: 00 Error: Wire not connected Power up Debug Error: Wire not connected Error: Wire not connected No Debug Power ============= END SCRIPT =============================== Failed on connect: Ee(42). Could not connect to core. No connection to chip's debug port (100) Target Connection Failed Unable to perform operation! Command failed with exit code 1 Re: Wire ACK Fault in DAP access Worked for me as well. Thanks man! Re: Wire ACK Fault in DAP access I found the problem was that the MCP was locked, It's a simple way of unlocking a MCU in MCUXpresso that I thought I'd share with other novices so they can get going again easily:     Step 1: Open the GUI Flash tool Step 2: Choose Resurrect locked... Step 3: Hit Run.   In a moment the MCU will be unlocked and ready for more programming action! Re: Wire ACK Fault in DAP access I have the same problem.  How did you solve the problem in the end? Re: Wire ACK Fault in DAP access I have the same problem.  How did you solve the problem in the end? Re: Wire ACK Fault in DAP access Good to know it. You are welcome! Have a great day, Jun Zhang ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the Correct Answer button. Thank you! ----------------------------------------------------------------------------------------------------------------------- Re:  Wire ACK Fault in DAP access Thanks, The issue has been resolved.:) Re:  Wire ACK Fault in DAP access Hello, I have done what you said to me. Now I am getting the following error 15: Target error from Commit Flash write 15: Target error from Commit Flash write Cannot halt processor. Debugging context: frdmk64f_lwip_tcpecho_bm Debug Re: Wire ACK Fault in DAP access Hi Saad, First, we need identify this issue is only on one project or a common issue for all project. - please create a NEW project in a NEW workspace, see how the connection works. - please test your project in a NEW workspace, how does it work? If both of above can't fix the issue, I suggest you update your K64 firmware. OpenSDA Serial and Debug Adapter|NXP  Have a great day, Jun Zhang ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the Correct Answer button. Thank you! -----------------------------------------------------------------------------------------------------------------------
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