S32K1xx SDK in S32DS Hello, I'm using S32DS 2018.R1 for years. I want to upgrade to v3.6.0, But I'm not able to find the latest S32 SDK in zip format. I installed the exe version, but it does not seem to be usable in S32DS.  Why doesn't the zip version appear in the download area ? Where is it available ? I already asked on this thread, with no answers : SDK in zip where to download - NXP Community Thank you for supporting Franck Re: S32K1xx SDK in S32DS Thanks. Very clear and helpful : Re: S32K1xx SDK in S32DS Personally I have tested the above mentioned RTDs with the S32DS 3.6 without any issues (so far). Additionally, some customers are using it the same way. However officially, it is recommended to follow the installation flow of each RTD in its respective release notes. On the other hand, you do not need to uninstall the 3.6 , you can have both of them (3.5 and 3.6 versions) installed at the same time. Re: S32K1xx SDK in S32DS Hi, Thank you for this answer. Very helpful ! You mention the latest version is fully tested with S32DS 3.5. Do you expect it to work with S32DS 3.6, or should I uninstall it and stick to 3.5 ? Thanks again for the support Franck Re: S32K1xx SDK in S32DS Hi, Thank you so much for your interest in our products and for using our community. There is no more SDK updates. Now we provide Real Time Drivers (RTD). You can found them in the following way: For S32K1, please go to Design Resources -> Software -> Real-Time Drivers for S32K1 -> Automotive SW - S32K1_S32M24x - Real-Time Drivers for Cortex-M For S32K3, please go to Design Resources -> Software -> S32K3 Standard Software -> Automotive SW - S32K3/S32M27x - Real-Time Drivers for Cortex-M The latest RTD version for S32K1 is the patch S32K1_S32M24X Real Time Drivers AUTOSAR R21-11 Version 2.0.0 P04, however you need to install the S32K1_S32M24X Real Time Drivers AUTOSAR 4.4 & R21-11 Version 2.0.0 before. The latest RTD version for S32K3 is the S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 5.0.0. At the moment both of them are fully tested in S32DS 3.5. Please follow the installation flow of each RTD in its respective release notes. Hope it helps you. Have a nice day!

S32K314 デバッグ状態でのみ割り込み処理機能に入ることができない S32K314 MCUでADCとSTMタイマーを使用し、jlink接続でデバッグしています。 デバッグ中に割り込み処理機能のブレークポイントを打つことができなかったこと、そしてコードの実行結果から、割り込み処理機能が動作していなかったのは事実であることがわかりました。 jlinkを抜いて再度電源を入れたところ、コードの実行結果に基づいて割り込み処理機能が正常に実行されました(デバッグフラッシュを使用しました)。 また、ADCとTIMERのレジスタを確認したところ、割り込みフラグとイネーブルビットが設定されていることが分かりました。 次に、NVICレジスタISERを確認しましたが、すでに設定されています。 RTDバージョン:SW32K3_S32M27x_RTD_R21-11_4.0.0_S2311_DS_uupdatesitezip S32DSバージョン:3.5 Jlinkファームウェア:J-Link V11コンパイル May 8 2024 15:36:02 Jlinkドライバー:v9.6 では、デバッグモードで割り込みに応答できない理由として考えられるものは何でしょうか。 ありがとうございました

S32DS DRAM U-Boot 代码生成 我正在使用 S32DS DRAM 工具来分析我的主板，并且能够生成功能性的 Arm Trusted Firmware 代码。当我更改设置以生成 U-Boot 代码时，它会创建与 ATF 相同的代码集。我已经创建了一个干净的新项目来尝试生成 U-Boot 代码，但没有生成。这个功能有用吗？ 据我所知，AT-F 生成的代码与 U-Boot 代码库不兼容，生成的文件不存在于 U-Boot 代码树中。

IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello, without setting the sample bit in cfgr1 the lpspi4 works in master mode as aspected. With the sample bit in cfgr1 set for the delayed sck for thr sdi the lpspi4 is not transferring anything. The transfer is not starting. In the attachment is the modified source from the  evkmimxrt1060_lpspi_edma_b2b_transfer_master example. What can be the problem that the lpspi4 with activated sample bit in cfgr1 is no more working?Does a clock component need to be activated in addition to the clock for lpspi4 in order to use the delayed sck feature? Thanks for an answer kalimann i.MXRT 106x Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello Habib, i have found a solution. For the sck pin software input on field (SION) must be set to 1. IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 1U); BR kalimanni Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello Habib, Thank you very much for your information. It's good that you were able to reproduce the problem. I'm eagerly awaiting the solution. BR kalimanni Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello again @Kalimanni . Sorry for taking a while to get back to you. I was able to replicate your issue creating an example code based in your application, I will be working in order to solve it, and I will get back to you with more updates as soon as possible. BR Habib. Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello Habib, thank you for your answer. The answer to the first question: In the project that you provide me the file called "peripherals.c" is empty, is this a mistake? - No mistake, i have played around with the MCUXpresso Config Tools. I think the config tool has generated this peripherals files. Because i have nothing modified the generated procedures are empty. This files should be not needed but this makes no difference. The answer to the second question: I did not see in the shared project where the sample bit is configured, can you provide the code section do you configure this bit? - In the source directory in the file lpspi_edma_b3b_transfer_master.c in the main function you can find the master configuration. The sample bit will be set if masterConfig.enableInputDelay is set true in the procedure LPSPI_MasterInit from the lpspi driver file fsl_lpspi.c. The comment characters at the beginning of line 357 must be removed. /*Master config*/ LPSPI_MasterGetDefaultConfig(&masterConfig); masterConfig.baudRate = TRANSFER_BAUDRATE; masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT; masterConfig.pcsToSckDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U); masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U); masterConfig.betweenTransferDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U); // masterConfig.enableInputDelay = true; <== remove the comment characters srcClock_Hz = LPSPI_MASTER_CLK_FREQ; LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz); BR, kalimanni Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello again @Kalimanni. Sorry for taking a while to get back to you. I am still checking the code, however in order to support you better, can you provide me the next information around your code? In the project that you provide me the file called "peripherals.c" is empty, is this a mistake? I did not see in the shared project where the sample bit is configured, can you provide the code section do you configure this bit? BR, Habib Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello Habib, Have you been able to test the lpspi master yet? Does the problem also occur for you if the sample bit is set? BR kalimanni Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Hello Habib_MS, Thank you very much for your answer. I have zipped the whole project and attached it. It is adapted for Teensy 4.1. But that only affects the linker script. All the required sources should be there. The files peripherals.h and peripherals.c should be found in the board subdirectory. BR kalimanni. Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1   Hello @Kalimanni,  Sorry for taking a while to get back to you.  I will verify the code and get back to you with a response as soon as possible.   Just one question: the code you provided needs the header file called "peripherals.h". In order to support you better, could you share me the code inside the function called "BOARD_InitBootPeripherals"?  BR  Habib.  Re: IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1 Does anyone have any idea why the SPI transmission does not work when the sample bit is set, even though it is only supposed to make the Sck signal fed back via a gate available for reading the input data (MISO). I have an LED on Sck. If the bit is not set, you can see the LED short glow faintly during transmission. If the sample bit is set, the LED lights up at full brightness and stays on -> no transmission. Why is the Sck signal only present on the 1st edge and then remains in this state? kalimanni

GD3162 gate driver Can anyone clarify the requirements needed for sensing short circuit and over current faults using ISENSE pin of gate driver? In my case, when I'm trying to set a threshold voltage for OCTH and SCCOMPTH (after enabling OCSNS and SCSNS bits to 1) and even after giving a voltage greater than the threshold to the ISENSE pin , it is sporadically detecting SC fault (OC fault is not at all being detected). I'm attaching the schematic which shows the INSENSE pin connection : Instead of directly connecting to the MOSFET terminal, we have designed a circuit mentioned above for phase current cut off. Please explain what else is needed to get an SC and OC fault and cutoffs respectively Re: GD3162 gate driver Yes, we have masked the OC fault and disabled over current fault management in the MODE2 register. We only want a PWM cut off using SSD whenever the current reaches a certain value. Yes, you are correct to figure out that the safing logic (SBC) has a direct access, but we are currently not using the failsafe state. But I still doubt that if I'm giving a constant voltage at the ISENSE pin which is greater than the threshold then how does the filter time cause the sporadic occurrence of the fault? Please clarify this, Tomas. And also is it correct to ay that DESAT_fault will always occur at times of short circuit at greater voltages? Re: GD3162 gate driver Hello Anand, Circuit connections look appropriate. As the ISENSE/COMP is a dual purpose pin, please confirm that ISNCMP_EN bit in MODE2 register is set to 0 to activate ISENSE functionality. Also make sure that OC fault is not masked by setting the OCM bit to 1 in MSK1 register. You mention sporadic detection of SC, no detection of OC. This could be due to the filter times on these 2 faults, filter time on OC is typically longer. Please configure using SCFF/SCFILT (100ns to 1.1µs) and OCFILT (0.5µs to 5µs) in CONFIG2 and resp. CONFIG1 registers. The positive pulse width on Isense must be much greater than these filter times to ensure reliable detection. From your circuit, SC and OC will always be triggered simultaneously. Is there any added value in enabling both then? OC could be masked if you want to directly interrupt PWM operation... Also, maybe the MCU/safing logic has direct access to the PH_OC_Cutoff signal? In this case, similar behavior could be achieved at lower cost (no need for optocoupler) by driving the FSENB line low (FSSTATE=0). This will turn OFF the driver using SSD as well. BRs, Tomas

S23K312EVB MCUに存在するADCに接続するジャンパーピンを特定するのを手伝ってくれる人はいますか 日時:S23K312EVB どうもありがとうございます！

Watchdog timer usage imx6ull Hello, We are planning to use the Watchdog timer for our existing system for any type of os failure or hardware failure, and we are using the IMX6ULL board so can you suggest which watchdog we can use for the best output and feasibility point of view? i.MX6UL Re: Watchdog timer usage imx6ull Hello @amiraj_patel  I hope you are doing very well. You can refer to the imx6ul device tree, the only wdog used is the wdog1, you can use wdog2 and wdog3, just you must declare it on the device tree. I hope this can helps to you. Best regards, Salas.

How to obtain the commutation timing sequence table? Hello all:     I am testing the BLDC using the MCSPTE1 AK144 kit.      When I was reading the AN12435.pdf, I saw the Figure 4 "Six-step switching sequence" of page 5, and please refer to the attached sequence.png file.     I want to know how this switching sequence is obtained? What method can be used to obtain the sequence?     Thanks! Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hello Leo:    Ok, I understand now. I will continue my research. Thanks for your help. Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hi, Thank you so much for your interest in our products and for using our community. You could refer to Figure 2. 3-phase BEMF voltages and phase currents of a BLDC motor from the same app note. On the other hand, Six-step commutation is a very common method for driving a 3-phase star-connected BLDC motor, maybe there are more detailed documentation about this on the web. We usually just describe the basics to implement motor control with our MCUs. Hope it helps you. Have a nice day!

IMX8QM DP++ (DisplayPort Dual-Mode) Hi, We've a custom (imx8qm) board with an mDP (mini DisplayPort) connector, and I'd like to connect an external HDMI screen using a passive mDP-HDMI adapter. My understanding is that this should be possible if DP++ (DisplayPort Dual-Mode) is supported. I have a few questions regarding DP++ support on the i.MX8QM: i.MX8QM DP++ Support: Does the i.MX8QM processor itself support DP++? Cadence Firmware DP++ Support: Does the Cadence firmware for the i.MX8QM's DisplayPort controller support DP++? Device Tree Configuration: Are there any necessary device tree (dtb) configurations required to enable and utilize DP++ functionality? If so, could you please provide details on the specific settings? Thank you for your assistance. Re: IMX8QM DP++ (DisplayPort Dual-Mode) Hello, Unfortunately DisplayPort Dual-Mode is not supported in i.MX8QM, you need to look into another adapter. I apologize the inconvenience that this may affect your design. Best regards.

DAC 和 ADC 位于同一 SAI 上 你好， 我正在尝试设置一个设备树，以便我们可以使用相同的 SAI（SAI1）来使用 AK4458 DAC 和 AK5558 ADC。我已经成功为 AK4458 设置了一个简单的音频卡设备树节点，但现在我正尝试集成 AK5558。我只是想知道这是否可以通过简单的音频卡实现。请注意，它们应该使用相同的格式。它们都使用 TDM256、32 位、MSB。这是我当前测试设备树的摘录。在当前配置下，在相应卡上开始录制时似乎没有任何 RX 帧同步。 / { custom-audio-card { compatible = "simple-audio-card"; #address-cells = <1>; #size-cells = <0>; simple-audio-card,name = "Custom Audio"; system-clock-fixed; system-clock-direction-out; simple-audio-card,dai-link@0 { format = "left_j"; bitclock-master = <&sai1cpu0_master>; frame-master = <&sai1cpu0_master>; sai1cpu0_master: cpu { sound-dai = <&sai1>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; codec { sound-dai = <&ak4458>; prefix = "ak4458"; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <0 0 0 0 0 0 0 0>; }; }; simple-audio-card,dai-link@1 { format = "left_j"; bitclock-master = <&sai1cpu1_slave>; frame-master = <&sai1cpu1_slave>; sai1cpu1_slave: cpu { sound-dai = <&sai1>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; codec { sound-dai = <&ak5558>; prefix = "ak5558"; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <0 0 0 0 0 0 0 0>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; }; }; }; &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; // TODO ! clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; assigned-clocks = <&clk IMX8MM_CLK_SAI1>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; // SAI will output the MCLK fsl,dataline = <1 0x01 0x01>; status = "okay"; }; 回复：DAC 和 ADC 位于同一 SAI 上 我的密码配置确实错误！另外，我现在在 RX 同步模式下使用 sai。据我所知，一切都按预期进行！

Serdes Driver Not Showing Under Peripherals View Hi, I'm trying to configure the Serdes RTD driver to be able to use GMAC with Serdes. But when I go to the peripheral view I can't find Serdes in the list. What is the process to add Serdes configuration to a project in Design Studio ? I checked and serdes RTD driver is present under  C:\NXP\S32DS.3.6.0\S32DS\software\PlatformSDK_S32XX_4_0_0\RTD\Serdes_TS_T40D11M50I0R0 Thank you for your help .   Re: Serdes Driver Not Showing Under Peripherals View Hello @yanis-waabi,  After some research I can conclude that there is no supported procedure to add SerDes in S32DS. If you see the examples folder of the module, you can see that there are examples only for EB Tresos.  I apologize for the inconveniences.

IPS 大家好， S32G3参考手册中使用的IPS总线是什么？在多种情况下，“IPS”缩写被用于多种语境中。我正在寻找它的完整形式和规格。在其中一个例子中，我注意到它将“外围总线接口”称为（IPS），这听起来与缩写不符。它是 (IPS) NXP专有的吗？S32G2 S32G3 S32G-VNP-RDB3 S32G-VNP-RDB2 回复：IPS 谢谢您的回复。我很欣赏提供详细信息的方式。继续努力吧。

How to use imxvideoconvert_g2d and imxcompositor_g2d on imx8dxp with Wind River Linux. Hi, team I would like to use imxvideoconvert_g2d and imxcompositor_g2d on the SoC of imx8dxp. Due to certain circumstances, I need to use Wind River Linux. How can I use imxvideoconvert_g2d and imxcompositor_g2d? Can they be used by adjusting the Linux kernel configuration? Please let me know. Best Regards, Re: How to use imxvideoconvert_g2d and imxcompositor_g2d on imx8dxp with Wind River Linux. Hello, The imxvideoconverter plugin is available and runnign on VXworks you  just make sure that gstreamer is correctly installed on your system. If you continues with issue please send a case to winriver.  https://www.windriver.com/support Regards

S32G3 ubuntu login in username & passwd Hi, I recently used yocyo to compile fsl-image-ubuntu, but after burning the generated image to the sd card, the login is not like fsl-image-auto, which can be used by using "root". Please tell me how to log in to ubuntu  S32G-VNP-RDB3  Re: S32G3 ubuntu login in username & passwd Hi, @carlos_o : Thanks for your suggestion,you are right! Re: S32G3 ubuntu login in username & passwd Hi @jiajun_cheng, Please refer to the BSP User Manual of the version you are using. There at the chapter 3.1.3 BSP Ubuntu Build you can find the user and password.   [page 13, Linux BSP 42.0 User Manual for S32G3 platforms] 

S32K144 MCUを使用して同じFTMインスタンスのFTMチャネルで異なる周波数を使用する方法 私はS32K144 MCUを使用しており、FTMペリフェラルインスタンス0を使用しています。 FTM0_CH0とFTM0CH1で異なる周波数を生成したい。 しかし、私が観察したことは、APIによって1つのチャネルの周波数/周期を変更すると、 次のようになりますFtm_Pwm_Ip_UpdatePwmPeriodAndDuty(FTM_INSTANCE_0、channel0、35000、12000、TRUE); その後、他のチャンネルの周波数も変更されます。 すべてのチャンネルのMOD登録が同じであることがわかりました。したがって、周波数を変更するためにMOD値を変更すると、FTMインスタンス全体の周期が変更されます。 しかし、同じFTMインスタンスのチャネルで異なる周波数を使用したい場合はどうでしょうか。 どうすればそれを達成できますか?

s32k312 can not debug Hi NXP,    my environment is  jlink v11  and s32DS. it  works until yesterday, when starting debug, it can stop at main entry,  then run step into, or any other operation, it goes to unknown state. the abnormal as attached. 1. debug can't  halt CPU. 2. read sram failed. but with the same hardware and elf file,  i use ozone , it works normally.  here my debug cofig. it's same compare to it's working time. 回复： s32k312 can not debug i dont know what cause this problem, after totally reinstall S32DS , solved.  but after few days use, S32DS debuger seems responses slower than normal. currently, use OZone to program and debugger instead. Re: s32k312 can not debug Hi, Senlent Ozone is software on PC, my board and jlink are the same. i just use it instead of S32DS debug function, all others are same. Re: s32k312 can not debug Hi@victory I don't find any problem with your configuration, and your other debuggers (ozone) can burn and debug your hardware normally, so the possible reason may be your J-LINK tool or the link problem.

S32K396 SDADC measurement of AC signals shows attenuation Hello, I am using the S32K396 SDADC to measure two different frequencies of sine wave signals with the same peak-to-peak value, but the measured signals show varying degrees of attenuation. Specifically, when measuring a 1V 5kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1051/32768)×5=0.16V(1051/32768)×5=0.16V. When measuring a 1V 3kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1691/32768)×5=0.26V(1691/32768)×5=0.26V. My software configuration and code are as follows. Here are my configuration and code. /*================================================================================================== * INCLUDE FILES * 1) system and project includes * 2) needed interfaces from external units * 3) internal and external interfaces from this unit ==================================================================================================*/ #include "Clock_Ip.h" #include "Sdadc_Ip.h" #include "check_example.h" #include "Siul2_Port_Ip.h" #include "Siul2_Dio_Ip.h" #include "IntCtrl_Ip.h" #include "SGEN_conf.h" /*================================================================================================== * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) ==================================================================================================*/ /*================================================================================================== * LOCAL MACROS ==================================================================================================*/ #define SDADC_INSTANCE_USED 0U /* The SDADC hardware instance used in the example */ #define DMA_CHANNEL_USED DMA_LOGIC_CH_0 /* The DMA logical channel used in the example */ #define NUM_SAMPLES 16U #define GET_COMPLEMENT_OF_2(x) ((uint32)(~((uint32)(x)) + 1U)) #define SDADC_INVALID_DATA 0xFFFF sint16 data[1700]; sint16 cali_data[1700]; uint16 cnt_data =0; uint32 sfr_data=0; #define SDADC_0 0U /*================================================================================================== * LOCAL CONSTANTS ==================================================================================================*/ /*================================================================================================== * LOCAL VARIABLES ==================================================================================================*/ #define ADC_START_SEC_VAR_CLEARED_16_NO_CACHEABLE #include "Adc_MemMap.h" static volatile uint16_t ResultsBuffer[NUM_SAMPLES + 1U]; /* Plus 1 to check for overflow */ #define ADC_STOP_SEC_VAR_CLEARED_16_NO_CACHEABLE #include "Adc_MemMap.h" /*================================================================================================== * GLOBAL CONSTANTS ==================================================================================================*/ /*================================================================================================== * GLOBAL VARIABLES ==================================================================================================*/ /*================================================================================================== * LOCAL FUNCTION PROTOTYPES ==================================================================================================*/ void fifo_notification(void); /*================================================================================================== * LOCAL FUNCTIONS ==================================================================================================*/ void fifo_notification(void) { //Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 1U); Sdadc_Ip_GetConvData(SDADC_INSTANCE_USED,13,&data[cnt_data]); //Sdadc_Ip_ApplyCalibration(SDADC_0,7,&data[cnt_data],&cali_data[cnt_data]); //Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U); cnt_data+=13; if(cnt_data >= 1680) { sfr_data=Sdadc_Ip_GetStatusFlags(SDADC_INSTANCE_USED); Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U); } } int main(void) { /* Initialize clock driver */ Clock_Ip_Init(Clock_Ip_aClockConfig); Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals); Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U); SGEN_init_M1(3,8,SWG_TRIG_SW); IntCtrl_Ip_Init(&IntCtrlConfig_0); /* Initialize SDADC driver */ Sdadc_Ip_EnableInterruptEvents(SDADC_INSTANCE_USED,1); Sdadc_Ip_Init(SDADC_INSTANCE_USED, &SdadcIpConfig_0); // Sdadc_Ip_DoCalibration(SDADC_0); /* Start DSPSS thread and SDADC conversion */ Sdadc_Ip_ReloadConversion(SDADC_INSTANCE_USED); /* Wait until buffer is full: the last element was written by DMA */ while (1) { // Sdadc_Ip_SwTriggerConversion(SDADC_INSTANCE_USED); } } I used the SDADC's FIFO interrupt to transfer the collected data to the data array, and the FIR filtering is not enabled in the SDADC. I measured a 1V 3kHz sine signal and a 1V 5kHz sine signal, and the obtained data arrays are plotted in the following images. when measuring a 1V 5kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1051/32768)×5=0.16V(1051/32768)×5=0.16V. When measuring a 1V 3kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1691/32768)×5=0.26V(1691/32768)×5=0.26V.  Could you please let me know if there is any configuration error? Re: S32K396 SDADC measurement of AC signals shows attenuation Thank you for your reply. , I'll to  to contact my NXP representative. Re: S32K396 SDADC measurement of AC signals shows attenuation Hi again, I'm glad to read that you have found the reason for the signal attenuation. Regarding your issue with enabling FIR filter, I note you are using a board that is no available in the NXP page, which do not allow me to debug your issue on my side. Is this issue is reproducible in the S32K396-BGA-DC1? If so, how? If not, I'll need to ask you to contact your NXP representative or whoever provided you with the S32K396-LQFP-DC to follow up with your issue please. An apology for the inconvenience. Have a nice day! Re: S32K396 SDADC measurement of AC signals shows attenuation @_Leo_ ，Thank you for your reply. I found the reason for the signal attenuation; it is caused by the low-pass filter circuit in the signal input circuit. The development board I am using is the S32K396-LQFP-DC, and the filter circuit for the SDADC0 AN0 and AN1 channels is shown in the figure below. Now, I am testing the AN_2 and AN_3 channels of SDADC0, and the input circuit is shown in the figure below： I used the SDADC's FIFO interrupt to transfer the collected data to the data array, and the FIR filtering is not enabled in the SDADC. I measured a 2V 10kHz sine signal , and the obtained data arrays are plotted in the following images. In this case, the SDADC works well; however, after enabling the FIR filter, the output data has issues. The conversion data read after filtering seems incomplete, and there is an abnormal downward offset in the signal, as shown in the figure below. The schematic and code files for the development board are shown below. Re: S32K396 SDADC measurement of AC signals shows attenuation Hi, Thank you so much for your interest in our products and for using our community. Please share your complete project in a zip, as we as HW (board connections) & SW (IDE and RTD versions) installation details in order to reproduce your issue from our side, like plug & play. Feel free to share any details to speed up the test and therefore the resolution of the problem. Have a nice day!

PTN3460 Design Review Hi Team, Kindly looking for PTN3460 eDP to LVDS converter Hardware Design review. Thankyou. Regards, Nagendra Prasad Re: PTN3460 Design Review Hi Nagendra_Nash Sure, but open a new ticket on our page please, we need to have a record of our conversation and information shared for your protection and ours. Once you create the ticket, I or a coworker can help you privately. Have a great day and best of luck. Re: PTN3460 Design Review Hi RafaR Waiting for your response. Regards, Nagendra Re: PTN3460 Design Review Hi RafaR Can we have this review through mail.  Thank you. Regards, Nagendra Re: PTN3460 Design Review Hi Nagendra_Nash Sure!, Please send me what you want me to review I will be waiting for your response Have a great day and best of luck.

i.MX93 Linux reboot not working We have a custom board based on i.MX93 running with Linux 6.6.52, and in principle everything works fine. But calling reboot stuck at the end and does not restart the CPU and the board. In U-Boot the command reset works perfect. I followed the calls and can see, both, U-Boot and Linux kernel, calls    invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); In U-Boot the CPU restarts, in Linux nothing is happening after that PSCI call. I tried CONFIG_ARM_PSCI_CHECKER to see if PSCI is working and the tests done during Linux boot finished with success. So it looks like the according PSCI call PSCI_0_2_FN_SYSTEM_RESET is not working correct under Linux. Any idea what could be the reason? Linux Re: i.MX93 Linux reboot not working Solved! In old version of imx93.dtsi only watchdog 3 (wdog3) is available and activated by default. In newer version several watchdogs are available and disabled by default. So you have to activate them explicitly by setting status to okay. And it seems that wdog3 is needed for the reboot in the Linux system. So after explicitly activating wdog3 via the device tree reboot is working.

FRDM-KL25Z SPI 中的 MOSI 和 MISO 空闲状态 KL25Z 上的 MOSI 和 MISO 线路的默认空闲状态是什么 - 低或高？从我的测试来看，它们都处于高空转状态。但是我用于 SD 卡的分线板似乎在 MOSI 空闲状态为低、MISO 空闲状态为高的情况下工作效果更好。我尝试将 MOSI 线的端口配置设置为 LOW，但它实际上并没有变低。我还尝试使用 MOSFET 2n7000 晶体管作为逆变器，将空闲高电平信号反转为空闲低电平信号，但这会导致 MISO 线路出现问题。 我已查看过 KL25 子系列参考手册，但没有在任何地方看到此信息。 回复：FRDM-KL25Z SPI 中的 MOSI 和 MISO 空闲状态 我已经确定 MOSI 和 MISO 在 SPI 模式下的 KL25Z 上均处于高电平空闲状态。这是我的示波器的屏幕截图，其中包含 SPI 模式下 SD 卡的工作命令和响应。黄色是 MOSI；紫色是 MISO。您看不到命令和响应的详细信息，因为我捕获了全部 6 个命令，但您可以看到下降到 0。