How to send and Receive LPUART Using DMA RTD 3.0.0 , S32K312 Hi community,  My MCU details are as follows:  MCU: S32K312 SDK: 3.0.0 (PLATFORMSDK_S32K3_S32K312_M7_3.0.0_PATH) IDE: S32 Design Studio for S32 Platform 3.5 I'm trying to configure the UART DMA for sending and receiving data (messages), I found the example here --> S32K312 UART Transmit & Receive Using DMA. I have changed from LPUART6 to LPUART4 all the other peripheral configurations remain the same (Dma_lp, IntCtrl_lp, MCAL/Rm).  I can successfully send data to the UART terminal, but I have these problems: 1. The UART sends data only once to the UART terminal, how to configure the DMA to send continuously in the loop? 2. The lpUART send seems to work but receiving and sending to the UART terming does not work. how to modify my code so that I can receive and send the same data back to the terminal in loop?   Here is my code attached. Re: How to send and Receive LPUART Using DMA RTD 3.0.0 , S32K312 thanks @Julián_AragónM  i will closed this one Re: How to send and Receive LPUART Using DMA RTD 3.0.0 , S32K312 Hi @Gama_, I can see you have also entered an internal case for the same issue. I will keep supporting you through the internal case in order to avoid any confusion. Best regards, Julián

ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? I am trying to resolve a problem I'm having with a kernel panic on the LS1046a. Our custom board has a PCIe switch and 12 PCIe slots, with each PCIe slot containing an ASM3142 dual USB host controller. Intermittently, I receive kernel panics from routines related to the Linux XHCI implementation. These always seem to occur in 1 of 2 places. Either in the xhci_irq routine, or the xhci_handshake routine, but in either location, the panic always occurs on the instruction: dmb oshld This is a data memory barrier instruction, and the panic is caused by an SError (shown below).  I have no idea what could possibly cause an SError at this instruction, as there were no obvious illegal memory accesses prior to this. I am hoping the ESR_EL1 register may offer some clues, but I don't know how to parse it. According to the AArch64-Registers document on developer.arm.com, the ESR_EL1 register value 0xbf000002 can be parsed as: (bits 31:26) ESR_ESL1.EC = 0b101111   ==>  SErrror (bit 25)  ESR_ESL1.IL = 0b1 (32 bit instruction) (bit 24)  ESR_ESL1. = 0b1 (Implementation defined) Then, ISS bits 23:0 are an implementation defined value and I can't find any documentation that explains NXP's custom codes for the arm64 implementation in the LS1046a. Does anyone know how to interpret the ISS value 0x000002 on an SError exception for  the LS1046a? Or where I can download something that documents this? Importantly, does this offer any assistance at all in figuring out why a data memory barrier command would generate such an exception? Alternatively, does anyone have any clue at all what might be happening here?  I'm stumped on what could be the problem. Any assistance is appreciated. ------------------------------ [ 353.446849] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 353.446857] CPU: 0 PID: 185 Comm: kworker/0:3 Tainted: G O 6.1.41-devel #49 [ 353.446862] Hardware name: LS1046A Copier Board (DT) [ 353.446864] Workqueue: events xhci_handle_command_timeout [ 353.446873] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 353.446877] pc : xhci_handshake+0x68/0x110 [ 353.446884] lr : xhci_handshake+0x60/0x110 [ 353.446887] sp : ffffffc00adf3b40 [ 353.446889] x29: ffffffc00adf3b40 x28: 0000000000000000 x27: 0000000000000000 [ 353.446895] x26: 0000000000000000 x25: ffffffc00b379210 x24: 0000000000000000 [ 353.446899] x23: 0000000000000000 x22: 0000000000000008 x21: ffffffc00b360038 [ 353.446904] x20: 00000053693ee8a8 x19: 00000000004c4b40 x18: ffffffc00e463c88 [ 353.446909] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000001 [ 353.446913] x14: 00000000000003bb x13: 0000000000000000 x12: 0000000000000000 [ 353.446917] x11: 0000000000000000 x10: 00000000000009e0 x9 : ffffffc00adf3d70 [ 353.446922] x8 : ffffff8801c7fb40 x7 : fefefefefefefeff x6 : 000000023074d81b [ 353.446926] x5 : 00ffffffffffffff x4 : 002e7ddb00000000 x3 : 0000000000000018 [ 353.446931] x2 : 0000000000000000 x1 : ffffffc00adf3b00 x0 : 0000000000000000 [ 353.446936] Kernel panic - not syncing: Asynchronous SError Interrupt [ 353.446938] CPU: 0 PID: 185 Comm: kworker/0:3 Tainted: G O 6.1.41-devel ##4 [ 353.446942] Hardware name: LS1046A Copier Board (DT) [ 353.446943] Workqueue: events xhci_handle_command_timeout [ 353.446947] Call trace: [ 353.446948] dump_backtrace+0xf0/0x130 [ 353.446955] show_stack+0x18/0x28 [ 353.446959] dump_stack_lvl+0x68/0x84 [ 353.446965] dump_stack+0x18/0x34 [ 353.446970] panic+0x1a0/0x998 [ 353.446974] nmi_panic+0xac/0xb0 [ 353.446979] arm64_serror_panic+0x64/0x78 [ 353.446982] do_serror+0x34/0x80 [ 353.446984] el1h_64_error_handler+0x34/0x50 [ 353.446987] el1h_64_error+0x64/0x68 [ 353.446990] xhci_handshake+0x68/0x110 [ 353.446994] xhci_handle_command_timeout+0x180/0x5c0 [ 353.446997] process_one_work+0x1fc/0x350 [ 353.447001] worker_thread+0x44/0x440 [ 353.447004] kthread+0xf8/0x110 [ 353.447007] ret_from_fork+0x10/0x20 Re: ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? Refer to the doc of "ARM Cortex-A72 MPCore Processor" for the interpretation of "ISS" filed in SError exception. ISS=2 means "Slave Error". It might related to a PCIe Error. Please comment out "ls_pcie_fix_error_response" in "drivers/pci/controller/dwc/pci-layerscape.c" and run the test again, then share the crash log Re: ls1046a kernel panic in xhci_irq. How do I parse NXP custom ISS field in esr_el1? Discussing with the AE team, will provide more update later.

LS1028A GPIOs Reg Hi 1. In LS0128A Reference Manual, Section "The GPIO module as implemented on the chip" was mentioned. Where is this section available? 2. I can see 3 sets of GPIOs GPIO 1 to 3. How are these different? It seems we can not use GPIO1_DAT0 and GPIO2_DAT0 simultaneously. Is this correct? Thank you Re: LS1028A GPIOs Reg Dear yipingwang Thank you. Re: LS1028A GPIOs Reg 1. This is a mistake in LS1028ARM, there is no this section "The GPIO module as implemented on the chip". 2. The base addresses of these 3 sets are different. GPIO1 base address: 230_0000h GPIO2 base address: 231_0000h GPIO3 base address: 232_0000h You can use GPIO1_DAT0 and GPIO2_DAT0 simultaneously.

Issue in working with arduino uno for S32k116 EVB. Hello all, Background: S32 DS 3.4 Software and for the example S32K1xx SDK RTM v4.0.3 Example Projects --> lpuart_echo_s32k116.  I'm working on lpUART with S32K116 EVB, everything is working as expected with the open a terminal emulator(tera term in my case). But my question was how to do the same from arduino uno intead of open terminal? I've tried to connect the pins tx, rx and gnd pins of arduino uno to s32k116 EVB pins PTA 2 and 3 which is said to be arduino compatible pins. but didn't get succeed in getting output as Hello World for the input Hello Board.  As we can see from the above figure, the first graph is the signal sent from arduino to S32k board and the second one is recieved from s32k board. The expected output from second figure was Hello World, but in my case i am getting back the same signal that has been sent. Am I missing something to include in order to work with arduino uno? Any suggestions or help would be highly appreciated! I've also attached necessary source file with this message for our reference.  Thanks & regards, Santhosh Re: Issue in working with arduino uno for S32k116 EVB. Hello @Julián_AragónM , Thank you so much for your resonse! It is working as expected with arduino uno as well. and the code I used in adruino IDE as follows: void setup() {   // Initialize serial communication at 9600 baud   Serial.begin(9600);     // Wait for a moment to ensure serial connection is established   delay(1000); } void loop() {   // Send "Hello Board" message followed by a newline (LF only)   Serial.print("Hello Board\n");     // Wait for 3 second before sending the next message   delay(3000); } Thanks & regards, Santhosh Re: Issue in working with arduino uno for S32k116 EVB. Hi @santhosh23, I believe this is because the board is expecting a "\n" when comparing the buffers at the EOL. It seems you are transmitting both CR and LF ("\r\n") in each message. This can be seen configuring Tera Term from CR+LF (which only echoes the characters) to LF (which does return the "Hello World"): Could you try sending "Hello Board\n" only?  Best regards, Julián

S32G3 QSpi NorFlash Hi, I was looking at the AN13563 document and saw that"S32G does not have internal flash", but in "S32G3 Reference Manual" annexes "S32G3_memory_map.xlsx",I see that the address from 0x0-0x1fff ffff is the QSPI AHB Buffer So I've got a few questions for you. 1. Is this QSPI AHB Buffer referring to the external 64M size flash? 2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know,or maybe we should go to that document. 3. When I need to perform an erasure and write action on an external flash, how do I go about it? Please guide me,because the flash in the previous project was inside the chip. MY environments: S32G-VNP-RBD3, S32DS 3.5  S32G-VNP-RDB3 S32G3  Re: S32G3 QSpi NorFlash Hello @jiajun , Thanks for contacting NXP support. Here is the information I was able to find for all your questions: Q1. Is this QSPI AHB Buffer referring to the external 64M size flash? A1. This memory region, from 0x00_0000_0000 to 0x00_1FFF_FFFF, is not the 64M flash directly, it is the AHB buffer, that works like an intermediary between the real flash and the processors reading it. There is a direct mapping between the addresses in ram buffer and the flash device. You can read more about this in the following sections of the reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]: 39.5 Flash memory mapped AMBA bus 39.5.1 AHB bus access read considerations 39.5.5.2 AHB RX Data Buffer Register (ARDB0 - ARDB127)   39.6.2.8 Flash memory read Q2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know, or maybe we should go to that document. A2. This migration of data occurs during the boot process, you can find more info about it in the following documents: Reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]: 31.7 Boot flow 31.7.1 Boot flow phases 31.7.2 Boot flow diagram AN13456 - S32G3 Boot Process [Rev. 1, 02/2023] 6. BootROM 7.2. QSPI Boot You can also check the application note “AN13750 - Enabling Multicore App” [Rev. 0, 11/2022] for the RDB2, although it may no work exactly like that in the RDB3, it can give you a good idea on how the mapping of the ram and the flash is done. As you will see in that App note, the exact mapping will is related your linker file. Q3. When I need to perform an erasure and write action on an external flash, how do I go about it? A3. There are two ways to do it: one is with the flash tool, you can also check the steps in the “AN13750 - Enabling Multicore App”, in section “6. Deployment on s32g-vnp-rdb2”, step 8. If you want to do it during runtime you can check the RTD example “Qspi_Ip_Example_S32G399A_M7”, there you can see how to init, erase, write and read the QSPI flash. You can also go inside the functions definitions for more details about the registers usage. Please let us know if this information answers all your questions.

"FreeRTOS Task Aware Debugger for GDB" no information Hi NXP: I'm using FreeRTOS for developing with PEMicro(MultiLink) in my project, and my code works in FreeRTOS system. I'd like to debug further detail information of FreeRTOS status by "FreeRTOS Task Aware Debugger for GDB" from NXP, but it can't display any message, please help me, thanks. environment: S32DS Product=>3.5.0.202207261815 RTD S32K3XX=>5.0.0.202410011049 FREERTOS S32K3XX=>5.0.0.202409270704 FreeRTOS Task Aware Debugger for GDB=>1.0.8.202407261901 attachment: 20250102-task_list(FreeRTOS)_empty.png (stop step) 20250102-task_list(FreeRTOS)_no_information.png (full run) 20250102-console_message.txt (connected status with PEMicor) Re: "FreeRTOS Task Aware Debugger for GDB" no information Hi NXP: sorry~~I solved, never mind. thanks.

S32G PFE relation Hi, I want to know the relations between nodes of DTS(pfe_netif0,pfe_netif1,pfe_netif2,pfe_mdio0,pfe_mdio1,pfe_mdio2) and the controllers of PFE_EMAC0,PFE_EMAC1,PFE_EMAC2.Thank you. Re: S32G PFE relation Thanks a lot. Re: S32G PFE relation Hello, @piaochunri  Thanks for the reply. The pfe_netifX stands for the Linux network interface, while the pfe_mdioX stands for the MDIO interface. At last, PFE_EMAC_X is the ethernet MACs. BR Chenyin Re: S32G PFE relation The version of bsp is 35.0. Re: S32G PFE relation Hi, @piaochunri  Thanks for the questions. May I know which version BSP is referenced during your work? May I know if the other queries posted from your side are with the same code base? Thanks in advance. BR Chenyin

S32K3 FlexIO SPI Clk Cs time control hello , I'm using flexio emulate SPI, but there's a problem -> How to control flexio SPI's spitime like Lpspi? like clk2cs/ cs2cs Re: S32K3 FlexIO SPI Clk Cs time control Hi @Vandarkholme. Unfortunately, the RTDs do not support to configure timing parameters for SPI protocol emulation with FlexIO. This limitation arises because the RTDs are restricted to use only 2 timers and 2 shift registers. One timer is dedicated to generate CS output signal and the other timer is used for the shift registers control and the SCK generation. In this way, there is no control logic to adjust the timing parameters to generate specific delays neither a register to modify the timers. Please let me know if you have more doubts. - RomanVR.

Load some data into the Data RAM memory in MC33PT2000? MC33PT2000, During program execution, need to modify some data in DATARAM. While debugging, it was discovered that rewriting all 192 data  to DATARAM was the only effective method. Is it possible to change a specific data in DATARAM Using a simple method? How can the code be written? Solenoid Controller Re: Load some data into the Data RAM memory in MC33PT2000? Thanks! Re: Load some data into the Data RAM memory in MC33PT2000? Dear Hongyu, please use the PSC simulator. Please check the videos in this link. Please also check the section 8.1.2.2 in the PT2000 datasheet. With Best Regards, Jozef Re: Load some data into the Data RAM memory in MC33PT2000? Thank you! But, I didn't describe it clearly. Actually, I want to enable real-time data exchange between the microcontroller (for example: S32K144) and the MC33PT2000 (writing data to DATARAM). What method should I use? Re: Load some data into the Data RAM memory in MC33PT2000? Dear Hongyu, the DataRAM access is described in the section 2.8 in the PT2000SWUG attached. Please refer to it. With Best Regards, Jozef

i.MX8MN power down sequence Dear Team, We have observed that some power-down timing results do not meet the SoC's requirements. According to the specification, the power-down timing range must be between 0 and 10 ms. However, our measurement results did not meet this specification. As far as I know, the power-down behavior will depend on the capacitor value and loading on the PCBA, which may explain why the timing range specified in the document cannot be met by all products. Would a failure in power-down timing have any impact on the product? Could we ignore the failures? Here are the test results. T1. Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off, the test results are -0.43ms~-0.3ms. T3. Delay from NVCC_DRAM off to digital 1.8 V off, the test results are -0.18ms~-0.14ms. T4. Delay from digital 1.8 V off to analog 1.8 V off, the test results are -0.31ms~-0.19ms. T5. Delay from analog 1.8 V off to VDD_SOC off, the test results are -34.9us~-31.1us. T9. Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off, the test results are -3.97us~-2.53us. Please provide recommendations. Re: i.MX8MN power down sequence The understanding of the customer is correct. If PCA9450 is used for i.MX8MN application, the measurement result should be fine because all power rails will be discharged completely by the PMIC. Re: i.MX8MN power down sequence I will confirm it . Re: i.MX8MN power down sequence Hi Rita, This is the data measured on our design. Will there be any risks if we cannot meet the power-down requirement? Re: i.MX8MN power down sequence Which board are you using? NXP reference board or the board you design yourself?

What is the purpose of the RX Pin and the ADC I and Q channels, at that pin, on the PN512? I do not understand the purpose of the ADC I and Q channels on the PN512. PN512 provides a way of reading the value by reading register 0x3b but I don't understand what the values I am getting are supposed to represent. With the Field turned off I get a value of 0x88. With the Field turned on I get a value of 0xf0, sometimes 0xff. If someone could provide an explanation, that would be great. Thank You NFC Frontend Solutions NFC Reader Library Re: What is the purpose of the RX Pin and the ADC I and Q channels, at that pin, on the PN512? Hi, ADC_I and ADC_Q, both are just ADC sampling values, indicating the variation of a noise into RX. For a device featuring LPCD functionality, please consider our latest focus products from our NFC Readers portfolio. Regards, Eduardo. Re: What is the purpose of the RX Pin and the ADC I and Q channels, at that pin, on the PN512? Thank you for your reply,  To follow up, when I am reading register 0x3B what do the values in that register represent? Voltage? Current?  The PN512 document simply describes it as "the actual value of ADC I/Q channel". What kind of value is it?  Is there a way to use that value to detect the presence of a tag?  Thank You Re: What is the purpose of the RX Pin and the ADC I and Q channels, at that pin, on the PN512? Hello @user_leo, Hope you are doing well. I and Q are part of the RX section of the device: These two signals could be taken to judge the overall RX signal quality. You can see an example of ADC I channel behavior in AN11038 Fast Verification of PN512 and amplifier, Section 3.1.1. Regards, Eduardo.

SIUL書き込みピン時間 こんにちは SIUL出力として設定されたピンを使用して機能時間を測定しようとしていますが、ピンのHIGHとLOWを実行するには1.8usから2.2us(オシロスコープを使用して測定)かかることがわかります。RTD ドライバーで定義されている関数 Siul2_Dio_Ip_WritePin を使用しています。MCUは160MHzで動作するS32K311で、SIULペリフェラルは30MHzで動作します。 データシートでは、ピンの立ち上がり/立ち下がり時間(hw)が1〜18nsであると指定されているため、残りの時間はRTDドライバーによって消費される必要があり、分解を確認すると、この機能にあまり時間が必要ないとは思われません。何かが足りないのでしょうか?なぜMCUはWrite pinコマンドを実行するために~2usが必要なのですか? Re:SIUL書き込みピン時間 さて、Siul2_Dio_Ip_WritePin機能のLOCK / UNLOCKセクションを削除しましたが、現在は265nsかかります。 おっしゃるように、各命令が5サイクルかかり、REGISTER SETセクションに10の命令が必要な場合、それは400nsでなければならず、これは測定された265nsとほぼ一致します。 サポートしてくれてありがとう! Re:SIUL書き込みピン時間 次のコードを想定します。 while(1) { Siul2_Dio_Ip_WritePin(DEBUG_1_PORT, DEBUG_1_PIN, 0); Siul2_Dio_Ip_WritePin(DEBUG_1_PORT, DEBUG_1_PIN, 1); } Siul RTD ドライバーに足を踏み入れると、次のようになります。 void Siul2_Dio_Ip_WritePin(... args ...) { ... empty asserts ... /* LOCK code */ SchM_Enter_Dio_DIO_EXCLUSIVE_AREA_01(); /* End LOCK code /* REGISTER SET code Siul2_Dio_Ip_PinsChannelType pinsValues = (Siul2_Dio_Ip_PinsChannelType)base->PGPDO; pinsValues &= (Siul2_Dio_Ip_PinsChannelType)(~((Siul2_Dio_Ip_PinsChannelType)1U << (15U - pin))); pinsValues |= (Siul2_Dio_Ip_PinsChannelType)(((Siul2_Dio_Ip_PinsChannelType)value & 1U) << (15U - pin)); base->PGPDO = pinsValues; /* End REGISTER SET code /* UNLOCK code */ SchM_Exit_Dio_DIO_EXCLUSIVE_AREA_01(); /* End UNLOCK code */ } REGISTER SET中に行われた操作をリストすると、LOCK + REGISTER SET + UNLOCKの3つのセクションに分割します。 1 x メモリ読み取り 2 x サブトラクション 2 x ビットシフト 4 x ロジック演算 1 x メモリ書き込み Cortex M7(S32K311)を使用すると、120MHzのコアクロック== 83nsで、1回の操作で1サイクルあたり約10サイクルかかると仮定しています(間違っている場合は訂正してください)。 ですから、私が見る2usの時間のほとんどは、LOCK / UNLOCKセクションから来ていると思います。 コードが上記のように単純であると仮定して、RTDからLOCK / UNLOCKセクションを削除できますか?

Why are LPM modes disabled on i.MX93 VOLT_LOW_DRIVE parts 9302 Hi, recently we started replacing i.MX9352 (full-featured SoC) with i.MX9302 (low cost alternative). We noticed that U-Boot disables imx93-lpm driver when it detects VOLT_LOW_DRIVE part: int ft_system_setup(void *blob, struct bd_info *bd) { if (fixup_thermal_trips(blob, "cpu-thermal")) printf("Failed to update cpu-thermal trip(s)"); if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311() || is_imx9301()) disable_cpu_nodes(blob, 1); if (is_imx9332() || is_imx9331() || is_imx9312() || is_imx9311() || is_imx9302() || is_imx9301()) disable_npu_nodes(blob); if (is_imx9101()) { disable_eqos_nodes(blob); disable_flexcan_nodes(blob); disable_parallel_display_nodes(blob); } if (is_voltage_mode(VOLT_LOW_DRIVE)) { low_drive_freq_update(blob); disable_lpm(blob); } return ft_add_optee_node(blob, bd); } Note the disable_lpm(blob) function call in case of VOLT_LOW_DRIVE voltage mode is detected. However, lpddr4x_timing.c for i.MX9302 defines 3 FSP (frequency set-points)? If we re-enable imx93-lpm driver and test with: root@board:sys# echo 1 > /sys/devices/platform/imx93-lpm/mode Board gets stuck and only hard-reset helps! Question: Why is LPM not supported on i.MX9302? Are you actively working on supporting this feature? Thanks, BR, Primoz Re: Why are LPM modes disabled on i.MX93 VOLT_LOW_DRIVE parts 9302 Hi Please refer the git log LFU-586-2 imx93: Add Low performance parts 9302/9301 support Add support for iMX93 low performance parts 9302 and 9301 which restrict to low drive voltage only. The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU and A55 core1 (9301) disabled. Best Regards Zhiming

s32k312 spi transmit Hello, I currently have two SPI channels, which are lpspi0 and lpspi1. Each SPI channel has different clock polarity, phase, and transmission bit width. I have created two SPI driver configurations. What I want to know is, how can I associate the driver with the two SPI channels?    For example,：: lpspi0 → configured to communicate with spi externalDevice_0 lpspi1 → configured to communicate with spi externalDevice_1 Re: s32k312 spi transmit Hi @fengba_360  The mapping between an SpiExternalDevice and an SpiPhyUnit is configured with the help of the SpiExternalDevice > SpiHwUnit parameter, as illustrated in the screenshot below: As mentioned in the tooltip, you need to choose the CSIB parameter, from the dropdown list, according to the order in which the LPSPI instances were configured inside the SpiPhyUnit. As per the attached screenshots, if you would like your SpiExternalDevice_0 to be associated to the LPSPI0 instance, you should select the SpiHwUnit as CSIB0, since LPSPI0 is configured as the first SpiPhyUnit. In the same logic, if you would like your SpiExternalDevice_1 to be associated to the LPSPI1 instance, you should select the SpiHwUnit as CSIB1, since LPSPI1 is configured as the second SpiPhyUnit. BR, VaneB

S32G399A - Is Device Tree Configuration for U-Boot required? Dear NXP fellows, I see, for example, that in the Release BSP41.0 of U-Boot, there is no specific DTS or DTSI files concerning the S32G399A board in https://github.com/nxp-auto-linux/u-boot/tree/release/bsp41.0-2022.04/arch/arm/dts . The Arm-Trusted Firmware has the DTS files for the S32G boards. However, I saw one project where the developer patched U-boot for including the configurations required by the S32G boards. So, my question is: Are the DTS configurations in this case managed exclusively by the ATF or I do have to manage the DTS in U-Boot too? Thanks for your help, Best regards, Guilherme Re: S32G399A - Is Device Tree Configuration for U-Boot required? Hello @chenyin_h , Thank you very much for the answer! Best regards, Guilherme Re: S32G399A - Is Device Tree Configuration for U-Boot required? Hello, @GuilhermeS32G3  Thanks for the post From BSP's perspective, the dts is managed by ATF, you may not need to modify the files under u-boot. BR Chenyin

MPC5777C-Parallell accesses through EBI Hello! I am working with a MPC5777C in dual core configuration. While measuring the hardware resource contention interference in timing, my teammate noticed a 40% increase in task execution time when both cores were acessing the EVB's external SDRAM through the EBI. The on-chip SRAM has two Platform RAM Controllers that allow parallel memory acessess, atenuating inter-core interference when each controller is allocated to different cores. I know that the MPC5777C does not have two EBIs, but is there a way to decrease intercore interference coming from the EBI? Best regards,  Matheus Re: MPC5777C-Parallell accesses through EBI This answers my question. Thank you, David! 🙂 Re: MPC5777C-Parallell accesses through EBI It is expected to use internal SRAM memory (internal SRAM is split into two halves according address line 18 (see Table 9-2. XBAR slave port assignments). It can be beneficial if one core accesses slave port 2 and second core accesses slave port 4 (or otherwise) as both accesses goes in parallel. You can split EBI data bus to two 16-bit halves, but it does not help as it will be sequential access anyway. There is only one dedicated XBAR slave port for EBI module what means only one master can access EBI at a time. Re: MPC5777C-Parallell accesses through EBI Hello! I think I did not use the correct reply button previously, so I believe you did not receive a notification. Sorry for that. Could you evaluate the previous reply that I made, please? Best regards, Matheus Re: MPC5777C-Parallell accesses through EBI Hello! In my understanding, your solution will not atenuate shared resources competition impact on timing. It will just define which core will take more interference by "losing" the resource competition more times (i.e., having lower access priority). In the example that I mentioned, the on-chip SRAM has two Platform Memory Controllers that could be allocated individually for each core. This configuration leads to lower interference because I would be dedicating independent controllers to individual cores. I was expecting for the EBI somethig like using 16 bits of the bus for one core and 16 bits for other. I just need to make 16 bits access to the EBI, so if it could be possible, would work for me. Best regards Re: MPC5777C-Parallell accesses through EBI SDRAM cannot be connected to the EBI module, I suppose you mean SRAM. Pay attention to XBAR priority, choosing of round-robin arbitration scheme would solve this issue and both cores would have equal chance to access the slave. Or you may set up fixed priority to define higher priority for one core over other (or other master).

i;MX8MP LVDS clock polarity Hi all,  We are using an #i.MX8MP  application processor to drive a LVDS panel on one of our custom board. The panel is currently not looking as expected. The text is barely readable, and we see some black (moving) flicker when we display a red screen. We have contacted the vendor of the panel, and they suggested to invert the polarity of the LVDS clock (from falling edge to rising edge or from rising edge to falling edge depending on the current setting).  We then had a look at the reference manual of the #i.MX8MP. We did not find any relevant registers/information about the clock polarity of the LVDS interface. Do you have some information about the polarity of the clock? What is the default setting? Can this be configured?  We have tried to swap the plus and minus clock signals as an alternative, but that does not work (voltage levels are different, so that is not unexpected). We also tried changing the polarity of the pixel clock in the LCDIF. However, then the panel looked exactly the same. Does someone have some other suggestions to troubleshoot or fix our problem? Kind regards,  Yoshi Re: i;MX8MP LVDS clock polarity Hi,  Thank you for your reply. It was indeed an issues on our PCB.  Kind regards,  Yoshi Re: i;MX8MP LVDS clock polarity Hi @YoshiDev! Is not possible to change the polarity in the iMX8MP. What BSP version are you using? What Display model are you using? Have you configured well the device tree, clock rate, etc? The most of cases behaviors like that are normal when the configuration is not the correct one. I recommend to check your layout and verify the impedance of the LVDS signals too. Best Regards! Chavira

i;MX8MP LVDS クロック極性 皆さん、こんにちは #i.MX8MPアプリケーションプロセッサを使用して、カスタムボードの1つでLVDSパネルを駆動しています。パネルは現在、期待どおりに表示されません。テキストはほとんど読めず、赤い画面を表示すると黒い(動く)ちらつきが見られます。パネルのベンダーに問い合わせたところ、LVDSクロックの極性を反転させることを提案しました(現在の設定に応じて、立ち下がりエッジから立ち上がりエッジへ、または立ち上がりエッジから立ち下がりエッジへ)。 次に、#i.MX8MPのリファレンスマニュアルを見ました。LVDS インターフェイスのクロック極性に関連するレジスタ/情報は見つかりませんでした。時計の極性についての情報はありますか?デフォルト設定は何ですか?これは構成できますか? 代わりにプラスとマイナスのクロック信号を入れ替えようとしましたが、うまくいきません(電圧レベルが異なるため、これは予想外ではありません)。また、LCDIFのピクセルクロックの極性を変更してみました。しかし、その後、パネルはまったく同じに見えました。誰かが私たちの問題をトラブルシューティングまたは修正するための他の提案を持っていますか? よろしくお願いいたします。 ヨッシー

S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast This question might be similar to this one: https://community.nxp.com/t5/S32K/S32K312-LPSPI-DMA-AsyncTransmitFast/m-p/1923811  I have to send two spi transaction to a device. I am trying to use Lpspi_Ip_AsyncTransmitFast. const Lpspi_Ip_FastTransferType ft[] = { { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf_wren, .RxBuffer = rxbuf_wren, .DefaultData = 0, .Length = 1, .KeepCs = false, }, { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf, .RxBuffer = rxbuf, .DefaultData = 0, .Length = 10, .KeepCs = false, } }; void send_spi_txn(void) { Lpspi_Ip_StatusType status = Lpspi_Ip_AsyncTransmitFast( ft, 2, Lpspi_Ip_Callback_lpspi_0_dma ); if (status != LPSPI_IP_STATUS_SUCCESS) { failed_spi_dma = true; } }   I have already tested using Lpspi_Ip_AsyncTransmit to send a single transaction and then sending another one from the completion callback, but this is obviously not ideal so would like to be able to use the transferlist instead. The issue is that no data is being sent. the first time Lpspi_Ip_AsyncTransmitFast is called it reports success, but every subsequent call fails. also can see that there are no spi transfers. on the logic analyzer, but when i just do Lpspi_Ip_AsyncTransmit everything works fine. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Hello, is there any further update on this topic? is there any example project available. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Unfortunately I can't post the project because I am only using S32DS to configure the RTD and to generate driver config files. But I was able to work through the issues and unsurprisingly it was a data cache issue with the DMA. as for the setup issues: didn't properly link the scatter gather channels. (each channel needs to link to the next one and last one needs to be marked as final) didn't have the tx/rx dma channels priorities correctly (rx higher than tx) didn't have the tx/rx dma channel complete interrupts prioritized correctly. (tx higher than rx) and the data cache issue boiled down to the MemMap.h files. nxp uses these defines: #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" /* Pointer to the DMA Initialization Configuration. Based on this configuration pointer, the DMA Driver obtains all information for the Logic Channels and corresponding Channel Configurations. The Pointer is loaded when Dma_Ip_Init() is called. */ static const Dma_Ip_InitType * Dma_Ip_pxInit; #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" and in the  _MemMap.h they define what the compiler should do. in this case #pragma GCC section bss ".mcal_bss_no_cacheable" #ifdef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE /** * @file Mcl_MemMap.h */ #undef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #define ENTERED_MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #ifndef MEMMAP_MATCH_ERROR #define MEMMAP_MATCH_ERROR #else #ifndef MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #error "MemMap.h, no valid matching start-stop section defined." #endif #endif /** * @file Mcl_MemMap.h */ #undef MEMMAP_ERROR #pragma GCC section bss ".mcal_bss_no_cacheable" #endif   for gcc unless you use the gcc version that comes with the s32ds ide or download their specific version of gcc these types of pragmas aren't supported. so for now i just went through all the rtd files that used dma and manually added the right section attributes to make them non-cacheable either .mcal_bss_no_cacheable or .mcal_data_no_cacheableso for the snippet above i had to add:   __attribute__((section(".mcal_bss_no_cacheable"))) static const Dma_Ip_InitType * Dma_Ip_pxInit; i replaced all the  _MemMap.h with empty dummy files to make the compiler happy which means i have to manually add all the __attribute__((section())) compiler directives. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Hi @not_a_duck, Could you share the project so that I can test it? Thank you, Daniel Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast correction: `Lpspi_Ip_LPSPI_0_IrqTxDmaHandler` actually does get called but only once. and then never again Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast @PetrS or @davidtosenovjan do either of you have any suggestions on what i can check? one additional thing i have noticed is that the dma interrupt for the tx channel is being called repeatedly. it is supposed to call Lpspi_Ip_LPSPI_0_IrqTxDmaHandler callback but it never does.

PCA9509P VOL on PORT A Hello team, What is is the meaning of "Iload=100µA"  in table 6? Is the test circuit shown in Figure 20, with RL=1.35kohms  used for this characterization? Best regards. Sylvain Re: PCA9509P VOL on PORT A Hello Thomas, As the solution will  be implemented in a design, I need an "official answer" from NXP. The answer “I don't think so” is not safe from my point of view  :-). An answer starting with “yes/no 100µA is a strict requirement” will be appreciated. Regards Re: PCA9509P VOL on PORT A Hello Sylvain, I do not think that 100μA is a strict requirement. Please try increasing the pull-up resistor on Port A to reduce the current and check if your VOL improves while keeping rise times within acceptable limits for your application. BRs, Tomas Re: PCA9509P VOL on PORT A Hello, I need some recommandations about Pullup on port A: In paragraph 6.4.1.2, it's written that he pull-up resistor on the A side of the PCA9509P should be chosen to provide at least 100 μA of pull-up current. Is-it mandatory to respect this condition? In my application the VIL of of the master is 0.3XVCC where as the VOL (side A)of PCA9509P is  0.25VCCA (maximum value). The power supply is 1.8V. so VIL(min)=0.3*1.8=0.54V and VOL(max)@100µA=0.25*1.8 =0.45V The margin is : VIL(min)-VOL(max)= 0.54-0.45=0.09V. This margin is very small, so I think that if I reduce  current in port A, the VOL of Port A will be also reduced and the margin will increased. isn't it? Sylvain     Re: PCA9509P VOL on PORT A Hello Sylvain, The PCA9509P is relatively old device and I did not find the relevant test details/results. However, I assume that the "Iload = 100µA" in Table 6 specifies the test condition under which the VOL on Port A was characterized. When the device is driving the output low, it must maintain the VOL value while sinking a current of 100µA. I do not think the circuit in Figure 20 was used directly for the VOL test in Table 6. The load current would be in mA range which significantly exceeds the 100µA condition specified for VOL characterization. BRs, Tomas