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RDDRONE-MBS772 SMBus Address not found Hi Team, I have been first trying to communicate to RDDRONE-BMS772 via SMBus using J18 header. I am connecting ESP32 and RDDRONE-BMS 772 board via the SMBUS header, I am connecting SDA, SCL and GND. I am using the below code, I have tested the code with a I2C display and I am able to find the slave address with the below code. I have enabled the SMBus using the CLI using "bms set smbus-enable 1" command and verified using bms get smbus-enable. I have tested UAVCAN it works fine and I am able to fetch the data using PixHawk. #include #define SDA_PIN 6 #define SCL_PIN 7 void setup() { Serial.begin(115200); Serial.println("\nI2C Scanner starting..."); Wire.begin(SDA_PIN, SCL_PIN, 100000); // SDA, SCL, 100kHz Serial.println("\nI2C Scanner starting..."); } void loop() { byte error, address; int count = 0; for (address = 1; address < 127; address++) { Wire.beginTransmission(address); error = Wire.endTransmission(); if (error == 0) { Serial.print("I2C device found at 0x"); Serial.println(address, HEX); count++; } } if (count == 0) { Serial.println("No I2C devices found."); } delay(2000); } Please suggest me what I could be doing wrong? my intention is to fetch the data like Voltage, Current, etc. using SMBus. Re: RDDRONE-MBS772 SMBus Address not found Hi @abhishekBLD , To make the Arduino work with this HW configuration, you could download this SMBus PackProbe.ino file at https://github.com/PowerCartel/PackProbe/tree/master and you could do the following changes: Change SCL_PIN to 0 to be able to use Digital pin 7 and 8 of the Arduino Uno. Change deviceAddress to 11.  And then make it work with the serial monitor instead of the console bridge: Follow instructions to convert the console/bridge to serial: https://github.com/PowerCartel/PackProbe/blob/master/PackProbe/PackProbe.ino#L74-L77  This should work with the mentioned HW. I hope this helps!  Kind regards, Cis Re: RDDRONE-MBS772 SMBus Address not found Hi @abhishekBLD , I can see that SMBus is also working with BMS6.0 from the RDDRONE-BMS772.  I programmed the nuttx.bin at RDDRONE-BMS772/Binary at main · NXPHoverGames/RDDRONE-BMS772 · GitHub.  However I did notice that there is a bug in version 6.0 that is fixed in version 7.2.  The cell voltage is only showing the full integer voltages in mv notation (4000mV or 3000mV) and this does not correspond to actual cell voltages on my RDDRONE-BMS772 (e.g. 4123mV or 3978mV). To get the BMS7.2 for the RDDRONE-BMS772, you can follow the instruction to build and make the .bin, but just configure it for the RDDRONE-BMS772.  Please follow: GitHub - NXPHoverGames/MR-BMS771.  When you are at the step to configure and make the binary (GitHub - NXPHoverGames/MR-BMS771), make sure to configure for the RDDRONE-BMS772, for example:  tools/configure.sh -e rddrone-bms772:bms But if you did not get any messages via SMBus, I doubt that this will fix that problem. Meaning that it is either a HW issue or a SW issue.  In the attached picture you can see the pinning that I use. Unfortunately I'm not allowed to share the code that I'm using on the Arduino. Maybe I will still find a way to share an example or a link.  For the BMS code, you should have the same code as I tested with.   Pinout of the SMBus connection between RDDRONE-BMS772 and an Arduino Uno board:    I hope this information and picture helps debugging the problem!   Kind regards,   Cis Re: RDDRONE-MBS772 SMBus Address not found Hi @cisvmierlo, I am using BMS version 6.0 which I have cloned from the latest github repo https://github.com/NXPHoverGames/RDDRONE-BMS772/tree/main?tab=readme-ov-file  can you please test SMBUS communication from the above given repo? I am using RDDRONE-BMS772, that's why I am using above link instead of what you provided (BMS771). can you confirm if both has the same firmware, because as I can see BMS771 is used for 7S-14S? bms set smbus-enable 1 bms save I have done above two commands earlier as well and I could see it when I do bms get-all. Also I have check continuity and everything is fine. Please look into it and suggest solutions. Re: RDDRONE-MBS772 SMBus Address not found Hi @abhishekBLD , Thank you for your interest in the RDDRONE-BMS772 small all-in-one BMS for mobile robotics! I'm sorry that you've run into this issue.  Which SW version are you using on the RDDRONE-BMS772?  You can see the BMS version when the SW is started on the CLI or when issuing a "reboot" (command). Currently the latest version (7.2) can be found at the git repository of the MR-BMS771: https://github.com/NXPHoverGames/MR-BMS771, this SW can be used by the RDDRONE-BMS772 as well when configured correctly I've just tested SMBus with an Arduino Uno on the following RDDRONE-BMS SW version: BMS version: BMS7.2-11.0-RDDRONE-BMS772.  SDA port Dpin7 and SCL port Dpin8.  I can see that you are using the correct SMBus connector J18 and correctly enabling SMBus with the command "bms set smbus-enable 1".  Did you also save the parameters with the "bms save" command? otherwise a repower or reset could reset the smbus-enable parameter to 0. I cannot see your actual setup, but I would advise to keep the wires short and maybe lowering the I2C speed to the I2C slow mode ( e.g. 25kHz) when using I2C for board to board communication.  If you can share your BMS version number, I can test the SMBus on that as well.  Kind regards,  Cis
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IMXRT1176 OTFAD 通过 SWD 读取时解密闪存 您好, 我目前正在使用 OTFAD 加密存储在 IMXRt1176 外部闪存中的代码。 我已经进行了两次测试,一次是我用烧在熔丝中的KEK进行加密,另一次是我用不同的密钥进行加密。 在第一次测试中,软件运行符合预期,而在第二次测试中,软件不运行也符合预期。 当我使用 MCUXpresso 中的内存浏览器读取外部闪存时,我发现当我使用不正确的密钥加密图像时,闪存内容看起来是加密的,但当我使用正确的密钥时,闪存内容看起来与未加密的图像一模一样。 我的理论是,我从 CPU 的地址空间读取闪存,而 OTFAD 正在运行,因此它在我读取闪存内容时进行解密。如果 OTFAD 使用了不正确的密钥,那么内容就无法正确解密,从而导致与原始图像不匹配。 以上说法正确吗? 如果是的话,我在使用 PEMicro Cyclone 编程器验证时遇到了一个问题,我想应该与此有关。当我对新设备进行编程时,验证通过。当我重新编程时,它没有通过。我认为在第二轮中,OTFAD 已经加载了密钥,并在 Cyclone 回读时解密了图像。如果已解密,则验证失败,因为它与加密图像不匹配。 我知道程序是正确的,因为我可以运行软件,它也会报告更新的版本号。 Re: IMXRT1176 OTFAD Decrypting Flash when reading over SWD 你好@rnicolls、 是的,这是 OTFAD 的预期结果。 祝您愉快, Kan ------------------------------------------------------------------------------- 注: - 如果本帖回答了您的问题,请点击"标记正确" 按钮。谢谢! - 我们会在最后一次发帖后的 7 周内跟踪主题,之后的回复将被忽略 如果您以后有相关问题,请另开新主题,并参考已关闭的主题。 ------------------------------------------------------------------------------- Re: IMXRT1176 OTFAD Decrypting Flash when reading over SWD 嗨,Kan、 是的,我总是在编程前清除,但问题依然存在。我还尝试执行大规模擦除,然后进行 RESET,然后进行编程和验证,但这会导致编程步骤失败。 您能否确认,由于 OTFAD 正在运行,通过 SWD 读取闪存将显示未加密的数据? Best、 罗里 Re: IMXRT1176 OTFAD Decrypting Flash when reading over SWD 你好@rnicolls、 谢谢你的澄清!也许你是对的,需要使用"PEMicro" 进行检查,也许它可以直接读取闪存内容进行验证。 顺便问一下,在重新编程之前,您是否尝试过大规模擦除?有什么不同吗? 祝您愉快, Kan ------------------------------------------------------------------------------- 注: - 如果本帖回答了您的问题,请点击"标记正确" 按钮。谢谢! - 我们会在最后一次发帖后的 7 周内跟踪主题,之后的回复将被忽略 如果您以后有相关问题,请另开新主题,并参考已关闭的主题。 ------------------------------------------------------------------------------- Re: IMXRT1176 OTFAD Decrypting Flash when reading over SWD 嗨,Kan、 我正在使用 PEMicro Cyclone FX 进行编程和验证。 Re: IMXRT1176 OTFAD Decrypting Flash when reading over SWD 你好@rnicolls、 请问您使用哪种工具对闪存进行编程和验证?通过高效密码学标准(SEC)工具还是其他工具?请予以澄清。 祝您愉快, Kan ------------------------------------------------------------------------------- 注: - 如果本帖回答了您的问题,请点击"标记正确" 按钮。谢谢! - 我们会在最后一次发帖后的 7 周内跟踪主题,之后的回复将被忽略 如果您以后有相关问题,请另开新主题,并参考已关闭的主题。 -------------------------------------------------------------------------------
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I2C Fast Mode Rise/Fall Time Lower Limit The I2C standard (UM10204) specifies a lower limit for the rise/fall time in fast mode. Is this specified to manage undershoot and prevent EMS? If these are not issues, is it not necessary to adhere to the lower limit? ※This is the opinion of another manufacturer that handles I2C. Re: I2C Fast Mode Rise/Fall Time Lower Limit Hi Tomas, Thank you for your quick response. This is very helpful. However, if that's the case, why is there no minimum limit on rise time in Fast-mode Plus, even though it is even faster? Re: I2C Fast Mode Rise/Fall Time Lower Limit Hi Keitaro, The lower limit is defined not only to manage electromagnetic susceptibility and undershoot, but also to ensure robust signal integrity and interoperability across I²C-compliant devices. Here are the key reasons for this specification: - Signal Integrity: Excessively fast transitions can cause reflections, ringing, and timing violations, especially in systems with longer traces or higher capacitance. The lower limit helps maintain stable communication. - EMS and Undershoot: Fast edges increase high-frequency emissions and can lead to undershoot due to inductive effects. The timing limits help mitigate these risks. - Device Compatibility: The I²C bus is designed for multi-device, multi-vendor environments. Adhering to timing specifications ensures reliable operation across all compliant devices. While it may be technically feasible to operate outside the lower limit in controlled environments where EMS and undershoot are not concerns, doing so would mean deviating from the I²C standard. This could compromise compatibility and long-term reliability. In summary, even if EMS and undershoot are not immediate issues, I recommend adhering to the specified timing limits to maintain compliance and ensure consistent performance. BRs, Tomas
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Flexcomm1 I2C 配置 嗨,团队、 我一直在尝试使用 Flexcomm1 配置 I2C。我无法在主服务器和从机之间建立连接。我正在尝试通过更改执行相同的示例代码。以下是为从 FC4 转移到 FC1 而对示例代码(SDK_2_11_1_EVK MIMXRT685\ boards\ evkmimxrt685\ driver_examples\ i2c\ polling_b2b\ master)所做的更改的快照。 #define gdy112x_i2c_base I2C1 #define i2c1_master_clock_frequency CLOCK_GetFlexCommClkFreq(1U) #define gdy112x_i2c_baudrate (100000U) /* GDY112X 地址(7 位) */ #define GDY112X_7BIT_I2C_ADDR (0x3A)   int main(void) {   /* 将 Flexcomm1 初始化为 I2C */ i2c_master_config_t 主配置; I2C_MasterGetDefaultConfig(&masterConfig);   /* 更改默认波特率配置 */ 主配置.波特率_Bps= gdy112x_i2c_baudrate; /* 初始化 I2C 主外设 */ I2C_MasterInit(gdy112x_i2c_base, &主配置, i2c1_master_clock_frequency);   /*该函数用于从主站向从站/从主站向从站写入和读取数据/* void GDY1121_MinimalI2CTest(void) { status_t 状态; uint8_t reg = WHO_AM_I_REG; uint8_t whoami = 0; PRINTF("开始最小 I2C 测试...\r\n"); // 1) 发送寄存器地址(写) 状态 = I2C_MasterStart(gdy112x_i2c_base, GDY112X_7BIT_I2C_ADDR, kI2C_Write); 如果(status != kStatus_Success) { PRINTF("启动(写入)失败,status=%d\态", status); 返回;    } 状态 = I2C_MasterWriteBlocking(gdy112x_i2c_base, &reg, 1, kI2C_TransferNoStopFlag); 如果(status != kStatus_Success) { PRINTF("写注册地址失败,status=%d\状态", status); I2C_MasterStop(gdy112x_i2c_base); 返回; }   //2) 重启并读取 1 字节 状态 = I2C_MasterRepeatedStart(gdy112x_i2c_base, GDY112X_7BIT_I2C_ADDR, kI2C_Read); 如果(status != kStatus_Success) { PRINTF("重复启动(读取)失败,status=%d\r\n", status); I2C_MasterStop(gdy112x_i2c_base); 返回;    } 状态 = I2C_MasterReadBlocking(gdy112x_i2c_base, &读取, 1, kI2C_TransferDefaultFlag); 如果(status != kStatus_Success) { PRINTF("读取 WHO_AM_I 失败,status=%d\(......)。", status); I2C_MasterStop(gdy112x_i2c_base); 返回;    } // 3) 停止 I2C_MasterStop(gdy112x_i2c_base); PRINTF("WHO_AM_I 读取成功:0x%02X\读取成功", whoami); }   /* pin_mux.c/* void BOARD_InitPins(void) { /* PIO0_8 :FC1_I2C_SCL */ const uint32_t port0_pin8_config =(/* 引脚配置为 FC1_TXD_SCL_MISO_WS*/ iopctl_pio_func1 | /* 启用上拉/下拉功能 */ iopctl_pio_pupd_en | /* 启用上拉功能 */ iopctl_pio_pullup_en | /* 启用输入缓冲区功能 */ iopctl_pio_inbuf_en | /* 正常模式 */ iopctl_pio_slew_rate_normal | /* 正常驱动 */ iopctl_pio_fulldrive_di | /* 模拟多路复用器已禁用 */ iopctl_pio_anamux_di | /* 伪输出漏极已禁用 */ iopctl_pio_psedrain_di | /* 输入函数未反转 */ iopctl_pio_inv_di); IOPCTL_PinMuxSet(IOPCTL, 0U, 8U, 端口 0_pin8_config);   /* PIO0_9 :FC1_I2C_SDA */ const uint32_t port0_pin9_config =(/* 引脚配置为 FC1_RXD_SDA_MOSI_DATA */ iopctl_pio_func1 | /* 启用上拉/下拉功能 */ iopctl_pio_pupd_en | /* 启用上拉功能 */ iopctl_pio_pullup_en | /* 启用输入缓冲区功能 */ iopctl_pio_inbuf_en | /* 正常模式 */ iopctl_pio_slew_rate_normal | /* 正常驱动 */ iopctl_pio_fulldrive_di | /* 模拟多路复用器已禁用 */ iopctl_pio_anamux_di | /* 伪输出漏极已禁用 */ iopctl_pio_psedrain_di | /* 输入函数未反转 */ iopctl_pio_inv_di); IOPCTL_PinMuxSet(IOPCTL, 0U, 9U, 端口 0_pin9_config); }   运行后,系统在函数 I2C_MasterTransferBlocking()函数中挂起。请指示 Re: Flexcomm1 I2C configuration 你好@Pablo_Ramos,此问题已在票据中解决 案例: 00737268. 谢谢! Re: Flexcomm1 I2C configuration 嗨,纳兹明、 您能帮我解决以下问题吗? I2C 引脚有输出吗?如果有,能否分享一个片段? I2C_MasterTransferBlocking 在哪种情况下会挂起? 如果不做任何改动就使用该示例,是否可行? 顺祝商祺! 巴勃罗
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i.MX 93 Maximum Design Current for VDD_SOC What is the maximum current the VDD_SOC rail should be designed for? There is conflicting information at different places. The Hardware Design Guide (Rev. 2.3) and the datasheet (Rev. 6.1) both state a current of 2700 mA.  On the other hand, in the reference schematics (SCH-51943 PDF: SPF-51943), a table on page 10 states a required current of 1500 mA. The PMIC itself is configured in dual-phase mode, which could deliver up to 6A.  What is the correct maximum VDD_SOC current the PMIC needs to be designed for? The PF9453 seems to be an option for powering the i.MX 93. This PMIC features only single-phase mode for the VDD_SOC with up to 2700 mA output current. Are there any limitations to using the PF9453 PMIC instead of the PCA9451 for powering the VDD_SOC rail? Can the i.MX 93 run with full performance and temperature range with the PF9453?  We know that the PF9453 does not support the extra buck converter for the VDDQ_DDR rail, and therefore, only LPDDR4 is supported. Are there any other known drawbacks to using the PF9453 instead of PCA9451? Re: i.MX 93 Maximum Design Current for VDD_SOC Hello, Is the PCA9451 older than the PF9453? Yes, that is correct. What is the reason you still see most i.MX 93 designs are equipped with the PCA9451, and not the PF9453? Because PCA9451 was designed for i.MX93 and was released at the same time. PF9453 is focused for for Industrial, IoT, smart appliance, and portable applications where size and efficiency are critical. Best regards. Re: i.MX 93 Maximum Design Current for VDD_SOC Hi @JorgeCas  Thank you for the quick response. Is the PCA9451 older than the PF9453? In other words, what is the reason you still see most i.MX 93 designs are equipped with the PCA9451, and not the PF9453? Re: i.MX 93 Maximum Design Current for VDD_SOC Hello, What is the maximum current the VDD_SOC rail should be designed for? The maximum current of VDD_SOC in i.MX93 is 2700 mA. On the other hand, in the reference schematics (SCH-51943 PDF: SPF-51943), a table on page 10 states a required current of 1500 mA. The PMIC itself is configured in dual-phase mode, which could deliver up to 6A.  This table shows the max output current of BUCK1/BUCK3 in dual-phase configuration (4000 mA), this is the output current from PMIC that is connected to VDD_SOC power rail of i.MX93. What is the correct maximum VDD_SOC current the PMIC needs to be designed for? It is 2700 mA, the dual phase configuration of BUCK1/BUCK3 in PCA9450 is enough to provide the current for this power rail since is able to provide up to 4000mA. Are there any limitations to using the PF9453 PMIC instead of the PCA9451 for powering the VDD_SOC rail? There are no limitations when using PF9453 instead of PCA9451 for powering the VDD_SOC rail. The only limitation that I can see is use LPDDR4x, it will be more difficult since you do not have an additional BUCK regulator to provide 0.6V of VDDQ, you may need to add an additional regulator, this issue does not occur in PCA9451. Can the i.MX 93 run with full performance and temperature range with the PF9453? Yes, you can. Are there any other known drawbacks to using the PF9453 instead of PCA9451? No, there are no any other known drawbacks to using the PF9453 instead of PCA9451. Best regards.
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SJA1110 CBS configuration Hi,  I am using SJA110 - EVM board to test credit based shaping parameters. I have  CBS parameters as below IdleSlope = 50Mbps SendSlope=-50Mbps Lo_credit = -750 Hi_Credit = 73 How can set these values in CBS registers (Explanation given in user manual is not clear to me) I dont get expected results with Hi_credit = 73 and lo_credit = 750. Note: by setting default which is 0x3FFFFFFF I observe correct bandwidth at switch output which is 50Mbps
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LMT101ENMFWD-ACD LCD 10.1'' HDMI with i.MX 8M Plus EVK Board Hi,  i am using LMT101ENMFWD-ACD LCD 10.1" with the i.MX 8M Plus EVK Board through HDMI connection.  i have flashed the i.MX 8M Plus EVK with LF_v6.12.34-2.1.0_images_IMX8MPEVK.zip image When the board boots up, the default resolution causes the content on the display to be squished. i tried to update the weston.ini file but no impact happens.  could you please tell me step by step how to update the resolution? thanks Eslam Graphics & Display i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: LMT101ENMFWD-ACD LCD 10.1'' HDMI with i.MX 8M Plus EVK Board Hello, You may refer to the following community document if you are using HDMI port it is pretty straight forward: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-to-change-the-HDMI-pixel-clock-and-change-the-panel/ta-p/2131344 Hope this helps, Best regards/Saludos, Aldo.
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iMX95 Arm Mali-G310 GPUベンチマーク 皆さんこんにちは 何か見逃しているのかもしれませんが、Linux Arm 用のバージョンがないのに、なぜ NXP は GFXBench と Antutu からの GPU ベンチマークの結果を表示しているのでしょうか? ドキュメントE1R05_Prior_NXP_2024.pdfを参照しています 私の理解では、Arm Mali-G310 は、Arm アーキテクチャでのみ利用可能な設計であるSO、これら 2 つは一致しません。 誰か説明してもらえますか? ありがとう、 デビッド Re: iMX95 Arm Mali-G310 GPU benchmarking こんにちは@Cerviik GFXBench は Linux 用です。 AntutuはAndroid専用です。 よろしくお願いします。 ダニエル
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how to write data flash (S32K328) I want to store some boot information in the dataflash area when designing the boot. Is there any related routine documentation that can be used as a reference? Currently, I have used AI to generate some operation methods (registers, c40uip), but none of them have been successful, and I don't know how to find the cause。 Re: how to write data flash (S32K328) Thank you, but I encountered a problem when using C40_SP for flash operations: the boot is at core0 0x00400000, and when I perform a write operation on the address of core0 (0x00440000), it enters a hard fault. I confirm that the boot area code is only before 0x00440000 and there is no out of bounds issue, but operating on core1 area (0x00600000) with the same code is not a problem. What is the reason for this. My rewrote code is as follow /************ erase code******************/ if (C40_IP_STATUS_SECTOR_PROTECTED == C40_Ip_GetLock(sector_number)) { printf("RAM: Sector %d is protected, clearing lock\r\n", sector_number); C40_Ip_ClearLock(sector_number, 0); } C40_Ip_MainInterfaceSectorErase(sector_number, 0);do { t_ReturnValue = C40_Ip_MainInterfaceSectorEraseStatus(); } while (C40_IP_STATUS_BUSY == t_ReturnValue); /************ write code******************/ C40_Ip_MainInterfaceWrite(addr, length, data, 0); do { t_ReturnValue = C40_Ip_MainInterfaceWriteStatus(); } while (C40_IP_STATUS_BUSY == t_ReturnValue); Re: how to write data flash (S32K328) There are RTD drivers, specifically Mem_43_INFLS (RTD 6.0.0): https://www.nxp.com/design/design-center/software/automotive-software-and-tools/real-time-drivers-rtd:AUTOMOTIVE-RTD Pay attention to example  C40_Ip_Example_S32K358 /** * @brief Main function of the example * @details Initializes IP C40 driver and erase, write, read internal flash memory */
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OpenSSL 3 and black key? Hi, We are interested in being able to use CAAM to support OpenSSL with black keys for signing operations. OpenSSL 3 recommends using a new interface called "Provider". It appears there's no ready CAAM "Provider" implementation without using something like OP-TEE. Could someone confirm or deny this? If there's no ready implementation, any suggestions, is there any official support integrating black key sign/verify operations to mbedTLS, OpenSSH, OpenGPG, etc..? Thanks, Christian i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Security Re: OpenSSL 3 and black key? Have also checked with internal security team, no positive answer without OPTEE. Regards Harvey Re: OpenSSL 3 and black key? If possible we'd like to _not_ have to use OPTEE. Do you know if that's possible? Regard, Christian Re: OpenSSL 3 and black key? Hi, Hope that the section <10.4.8 OpenSSL TLS offload to OP-TEE PKCS#11 via pkcs11-provider> of UG10163.pdf be helpful. Regards Harvey
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Is there a simple way to update the DTB and kernel image on an eMMC? During development, we need to frequently update the DTB and kernel image. Using an SD card is very convenient; a card reader can read and write the DTB and kernel image on a FAT partition. However, using an eMMC is very inconvenient. Is there a simpler method? Re: Is there a simple way to update the DTB and kernel image on an eMMC? Here is the better way, I believe. How to upgrade Linux Kernel and dtb on eMMC without UUU  Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, To enter on fastboot mode you need: 1. Turn on the board and stop boot flow pressing any key to enter in U-boot. 2. In U-boot enter next command: fastboot 0 Use the next command to send the file with UUU: uuu -v -b fat_write mmc 0:1 Example: uuu -v -b fat_write hello_world.elf mmc 0:1 hello_world.elf Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Use fastboot, as you mentioned before. Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, What are you referring for? Upload DTB with fastboot or flash eMMC from SD card or both? Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? How to do this specifically? Is there any guidance document? Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, You can update the DTB file configuring your board in fastboot from U-boot and transfer the file with UUU. Regarding flash the image I suggest you re-flash with UUU or try to flash the eMMC from SD card but I think this process is more complicated.  Best regards.
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Load initial bootloader thought CAN interface? Can the initial bootloader file be loaded through the CAN interface on a brand new MCU, thus eliminating the need for a JTAG connector? Re: Load initial bootloader thought CAN interface? Hello @klv222  Please describe your question in more detail. Which chip are you referring to? Which bootloader file?  Thank you. BR Alice Re: Load initial bootloader thought CAN interface? Yes, it is possible in some MCU families to load the initial bootloader through the CAN interface on a brand-new MCU, potentially eliminating the need for a JTAG connector, but this depends entirely on the MCU’s built-in features. Many modern microcontrollers ship from the factory with a ROM-resident bootloader that supports communication over interfaces such as CAN, UART, USB, or SPI. If CAN is supported in this factory bootloader, the MCU can be programmed directly via the CAN bus on first power-up, provided the correct boot mode pins or configuration are set. However, if the MCU does not include a CAN-capable ROM bootloader, JTAG or SWD is still required at least once to install an initial bootloader. Additionally, JTAG remains valuable for low-level debugging, recovery from misconfiguration, and unbricking devices, even if it is not required for normal production programming.   change healthcare
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Patch suggestion for linux-imx busfreq-imx8mq driver Hi NXP, Please consider the patch below for linux-imx. I tested this on branch lf-6.6.52-2.2.0 (imx8mm/imx8mn hardware), but it also applies on older branches. When switching DDR frequency, the busfreq driver will always make a print to the kernel log buffer via printk(). In a use case where the DDR frequency switches often, this leads to spamming the log buffer. We encountered this exact case, and all other messages from the dmesg buffer are pushed out as a consequence. Using pr_debug() will depend on the definition of DEBUG and will not spam dmesg by default. diff --git a/drivers/soc/imx/busfreq-imx8mq.c b/drivers/soc/imx/busfreq-imx8mq.c index 5e36962285ef..9914d19183be 100644 --- a/drivers/soc/imx/busfreq-imx8mq.c +++ b/drivers/soc/imx/busfreq-imx8mq.c @@ -205,9 +205,9 @@ static void reduce_bus_freq(void) } if (audio_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to audio bus mode\n"); + pr_debug("ddrc freq set to audio bus mode\n"); if (low_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to low bus mode\n"); + pr_debug("ddrc freq set to low bus mode\n"); } static void reduce_bus_freq_handler(struct work_struct *work) @@ -296,7 +296,7 @@ static int set_high_bus_freq(int high_bus_freq) cur_bus_freq_mode = BUS_FREQ_HIGH; if (high_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to high bus mode\n"); + pr_debug("ddrc freq set to high bus mode\n"); return 0; } i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Patch suggestion for linux-imx busfreq-imx8mq driver Hi, Thank you for your interest in NXP Semiconductor products, Thanks for the suggestion, I will pass it down to the software team. Regards
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Eth_43_GMAC on S32K344 Hello, I use S32K3-T-BOX, MCAL RTD 2.0.0 22_03, Eth_InternalLoopback example and PE micro multilink. I added configuration for all necessary pins according to SCH-50735.pdf and disable Loopback mode. I also added a loop with a delay for cyclic Eth_transmit and flashing the U37 LED to check the run. After Debug_FLASH everything works as expected and the T-BOX sends ethernet message cyclically, the problem occurs after turning the T-BOX off and on. LED U37 flashes to indicate software is running, but the Ethernet message is not being sent. It occurs to me that the multilink is doing some initialization that doesn't happen after the device is restarted, but I don't know how to solve this problem. If anyone has a solution, I would appreciate any advice. Regards won0020 Re: Eth_43_GMAC on S32K344 Thank you very much, osif delay solved my problem. Re: Eth_43_GMAC on S32K344 Hi @won0020 , have you programmed both FLASHs - S32k3 and Flash attached to SJA1110? You also start with the lwip demo - please refer to S32K3 Automotive Telematics Box (T-Box) lwIP Example Guide Training Presentation - refer to slide 15 where small workarounds are described. Best regards, Pavel Re: Eth_43_GMAC on S32K344 Hi, S1 is off, LED U36 also flashes green. Re: Eth_43_GMAC on S32K344 Hi @won0020 , Jumper S1 needs to be set to OFF to enable NVM boot for SJA1110. Best regards, Pavel
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[LPSPI] 周辺FIFOによる複素転送 コミュニティの皆さん、こんにちは。 皆さんがお元気でいらっしゃることを願っています。ペリフェラルのFIFO機能を利用したSPI通信の管理について、支援を求めています。 バックグラウンド: 現在、#i.MX-RT1050##とADCデバイス間のSPI通信を含むプロジェクトに取り組んでいます。データ転送プロセスを合理化し、効率を高めるために、ペリフェラルコマンド/データFIFOを使用して実装することを検討しています。ただし、この機能をプロジェクトに統合するには、いくつかの課題に直面しています。 サポートのリクエスト: ペリフェラルコマンド/データFIFOを使用して、LPSPI_MasterTransferNonBlockingや他の関数を1回呼び出すだけで複数のCSサイクルとの通信を管理しながら、SPI通信を効果的に管理する方法についてのガイダンス、洞察、またはリソースを提供できる方がいると幸いです。 タイムダイアグラムリファレンス: 参考までに、SPI通信プロセスを示すタイムダイアグラムの画像を添付しました。 あなたの時間と援助のために事前に感謝します。皆様からのご回答とご意見をお待ちしております。 よろしくお願いいたします。 i.MXRT 105倍
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How to set Lpi2c speed of S32K312 in RTD5.0? Hi NXP: we're developing project with S32K312 and getting I2C speed issue. I set Lpi2c parameters by reference manual and getting correct speed 1Mbit/s by GUI(Lpi2c_setting.png),but I measured I2C speed about clock waveform(LA_I2C_waveform.png) about 2.667Mhz. Is it correct? thanks. attachment: I2C_setting_from_reference_manual.png Lpi2c_setting.png clock_ip_referencepoints.png LA_I2C_waveform.png current environment: MCU:S32K312/100pin S32DS Product:3.5.0.202207261815 RTD S32KXX:RTD5.0.0.202407261948 BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Yes, I'm afraid you shouldn't select LPI2C_FASTPLUS_MODE with 1 Mbit/s because the reference manual says so. Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I modified I2C parameters from fast+ mode to fast mode in master mode, and GUI show 400000(Baud rate), but I measured speed about 385Khz. it looks like not accurate about GUI value and LA value, thanks. attachment: 20250306-2-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: just now, I saw reference manual as you posted information(LPI2C master mode operation supports up to fast Mode = 400KHz), so S32K312 only supports fast mode in master mode(Up to 400Khz). if I want to adjust more than 400Khz, it is invaild for usage, Is it correct? thanks. BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I always use I2C master mode as LPI2C_FASTPLUS_MODE which support 1 Mbit/s.however, I created simple project by GPIO and I2C function and set I2C parameters as current project, and also tested I2C speed is about 888~914Khz on our PCB board. now you can change MCU package of attachment from 100pin to 172pin for your EVB testing,thanks. attachment: 20250306-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Sorry for the inconvenience. It would be best if S32 Design Studio would warn you when you select master mode but exceed 400 kbps data rate. S32K3XXRM mentioned: •LPI2C slave mode operation supports up to high speed mode = 3.4MHz (3.4 Mbps data rate; effective data rate reduces according to I2C protocol). •LPI2C master mode operation supports up to fast Mode = 400KHz (400 kbps data rate; effective data rate reduces according to I2C protocol). Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I tried to change Clock_Ip_ReferencePoints from custom(8Mhz) to AIPS_SLOW_CLK(30Mhz), and also changes I2C timing that it calculated I2C baud rate 1000000. but I measured waveform about 864KHz. now I confuse about calculating result of Lpi2c GUI. please help us, thanks. attachment: clock_ip_referencepoints2.png LA_I2C_waveform2.png Lpi2c_setting2.png BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Nelson, The LPI2C_CLK comes from AIPS_SLOW_CLK. So would you please configure AIPS_SLOW_CLK in clock_ip_referencepoints.png? Otherwise, the S32 Configuration Tool may use the wrong frequency (80MHz CUSTOM) for calculation. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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L6.6.3 iw612 load txpower_cfg fail Hi I am trying add txpwrlimit_cfg while loading WiFi driver, but got the following error, same settings/files in L6.1.55 was fine. And without set txpwrlimit_cfg parameter, WiFi driver load succesfully and working fine. root@imx93:~# modprobe moal mod_para=nxp/wifi_mod_para.conf [ 17.532015] mlan: loading out-of-tree module taints kernel. [ 17.578136] wlan: Loading MWLAN driver [ 17.585593] wlan: Register to Bus Driver... [ 17.600828] vendor=0x0471 device=0x0205 class=0 function=1 [ 17.606578] Attach moal handle ops, card interface type: 0x109 [ 17.612532] rps set to 0 from module param [ 17.617918] SDIW612: init module param from usr cfg [ 17.623162] card_type: SDIW612, config block: 0 [ 17.627774] cfg80211_wext=0xf [ 17.630789] max_vir_bss=1 [ 17.633448] cal_data_cfg=none [ 17.636416] ps_mode = 1 [ 17.641499] auto_ds = 1 [ 17.643983] host_mlme=enable [ 17.649504] fw_name=nxp/sduart_nw61x_v1.bin.se [ 17.654084] txpwrlimit_cfg=nxp/txpower_QSM_US.bin [ 17.658916] SDIO: max_segs=128 max_seg_size=65535 [ 17.663765] rx_work=1 cpu_num=2 [ 17.666995] Enable moal_recv_amsdu_packet [ 17.671074] Attach mlan adapter operations.card_type is 0x109. [ 17.682854] wlan: Enable TX SG mode [ 17.686391] wlan: Enable RX SG mode [ 17.693610] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 18.046530] Wlan: FW download over, firmwarelen=1004248 downloaded 916048 [ 18.453634] WLAN FW is active [ 18.456624] on_time is 18307253173 [ 18.460061] Download txpwrlimit_cfg=nxp/txpower_US.bin [ 18.487779] VDLL image: len=88200 [ 18.519055] fw_cap_info=0x487cff03, dev_cap_mask=0xffffffff [ 18.524681] uuid: 521d887a0a925da4a1fe6a6f39966212 [ 18.529497] max_p2p_conn = 8, max_sta_conn = 16 [ 18.559956] Register NXP 802.11 Adapter mlan0 [ 18.566109] wlan: uap%d set max_mtu 2000 [ 18.574646] Register NXP 802.11 Adapter uap0 [ 18.608521] Register NXP 802.11 Adapter wfd0 [ 18.619407] wlan: version = SDIW612---18.99.2.p66.17-MM6X18437.p3-GPL-(FP92) [ 18.636305] wlan: Register to Bus Driver Done [ 18.645522] wlan: Driver loaded successfully [ 21.266693] FW trigger fw dump [ 21.269817] =====FW trigger dump==== [ 21.273726] ==== Start Receive FW dump event ==== [ 21.278586] === START DRIVER INFO DUMP=== [ 21.278825] FW in debug mode (0xe3) [ 21.394221] Drv info total bytes = 336781 (0x5238d) [ 21.399129] === DRIVER INFO DUMP END=== [ 22.215633] ==== FW DUMP END: 1336880 bytes ==== [ 22.224118] fw dump total length is 1336892 [ 22.228385] Start to process hanging [ 22.232045] Cancel all pending cmd and txrx queue [ 22.236901] WIFI auto_fw_reload: fw_reload=1 [ 22.241239] ========START IN-BAND RESET=========== [ 22.246180] woal_reset_intf: get bss info failed [ 22.250927] Cancel all pending cmd and txrx queue [ 22.390250] woal_close: woal_disconnect failed [ 22.662577] FW wake up [ 22.666271] SDIO Trigger FW In-band Reset success [ 22.666304] SDIO: max_segs=128 max_seg_size=65535 [ 22.677190] rx_work=1 cpu_num=2 [ 22.681162] Enable moal_recv_amsdu_packet [ 22.686153] Attach mlan adapter operations.card_type is 0x109. [ 22.693545] wlan: Enable TX SG mode [ 22.697059] wlan: Enable RX SG mode [ 22.701957] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 23.067701] Wlan: FW download over, firmwarelen=1004248 downloaded 916048 [ 29.077402] Fail to poll firmware status: firmwarestat=0x0 [ 29.082928] FW failed to be active in time! [ 29.087135] wlan_dnld_fw fail ret=0xffffffff [ 29.091440] WLAN: Fail download FW with nowwait: 0 [ 29.096577] SDIO Func0 (0x0-0x9): 43 03 02 02 03 00 00 02 03 00 [ 29.103437] SDIO Func1 (0x10-0x17): 00 00 00 00 00 00 00 00 [ 29.109526] SDIO Func1: (0x8) 00 (0x58) 00 (0x5c) 0d (0x5d) 00 (0x60) 01 (0x61) 00 (0x62) 00 (0x64) 10 (0x65) 00 (0x66) 00 (0x68) 00 (0x69) 00 (0x6a) 00 [ 29.123829] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.235469] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.245502] woal_request_fw failed [ 29.248901] Firmware Init Failed [ 29.252479] SDIO Func0 (0x0-0x9): 43 03 02 02 03 00 00 02 03 00 [ 29.258736] SDIO Func1 (0x10-0x17): 00 00 00 00 00 00 00 00 [ 29.264745] SDIO Func1: (0x8) 00 (0x58) 00 (0x5c) 0d (0x5d) 00 (0x60) 01 (0x61) 00 (0x62) 00 (0x64) 10 (0x65) 00 (0x66) 00 (0x68) 00 (0x69) 00 (0x6a) 00 [ 29.279066] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.389834] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.489860] Free module params [ 29.492947] ========END IN-BAND RESET=========== OS LINUX Product: WiFi IW6XX Protocol: Wi-Fi Re: L6.6.3 iw612 load txpower_cfg fail Hello @shaun_wu  Thanks, after force change FW and driver to 6.6.23 fixed this issue. root@quilt-imx93-qsm:~# modprobe moal mod_para=nxp/wifi_mod_para_qsm.conf [ 22.253697] mlan: loading out-of-tree module taints kernel. [ 22.317581] wlan: Loading MWLAN driver [ 22.326493] wlan: Register to Bus Driver... [ 22.338429] vendor=0x0471 device=0x0205 class=0 function=1 [ 22.344079] Attach moal handle ops, card interface type: 0x109 [ 22.349968] rps set to 0 from module param [ 22.355413] SDIW612: init module param from usr cfg [ 22.360371] card_type: SDIW612, config block: 0 [ 22.364935] cfg80211_wext=0xf [ 22.367927] max_vir_bss=1 [ 22.370569] cal_data_cfg=none [ 22.373554] ps_mode = 1 [ 22.376013] auto_ds = 1 [ 22.378482] host_mlme=enable [ 22.381390] fw_name=nxp/sduart_nw61x_v1.bin.se [ 22.385857] txpwrlimit_cfg=nxp/txpower_US.bin [ 22.390616] SDIO: max_segs=128 max_seg_size=65535 [ 22.395338] rx_work=1 cpu_num=2 [ 22.398522] Enable moal_recv_amsdu_packet [ 22.402675] Attach mlan adapter operations.card_type is 0x109. [ 22.414743] wlan: Enable TX SG mode [ 22.418371] wlan: Enable RX SG mode [ 22.426370] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 22.778840] Wlan: FW download over, firmwarelen=1038668 downloaded 936668 [ 23.181312] WLAN FW is active [ 23.184329] on_time is 22921111967 [ 23.187759] Download txpwrlimit_cfg=nxp/txpower_US.bin [ 23.221031] VDLL image: len=102000 [ 23.265041] fw_cap_info=0x487cff03, dev_cap_mask=0xffffffff [ 23.270673] uuid: 521d887a0a925da4a1fe6a6f39966212 [ 23.275483] max_p2p_conn = 8, max_sta_conn = 16 [ 23.410178] Register NXP 802.11 Adapter mlan0 [ 23.414909] wlan: uap%d set max_mtu 2000 [ 23.424961] Register NXP 802.11 Adapter uap0 [ 23.541433] Register NXP 802.11 Adapter wfd0 [ 23.547371] wlan: version = SDIW612---18.99.3.p10.1-MM6X18437.p21-GPL-(FP92) [ 23.584774] wlan: Register to Bus Driver Done [ 23.591295] wlan: Driver loaded successfully Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you try 6.6.23 on this problem? We have a similar fix on 6.6.23 release. Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  We are able to reproduce your issue, and we are internally tracking this problem. I'll update to you when we get progress. Thanks! Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hi @shaun_wu  Attached our Tx power file, system can't allow upload binary file. Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you share txpower_US.bin you used? Best Rergards Shaun Re: L6.6.3 iw612 load txpower_cfg fail It's only one place could to set tx power in wifi_mod_para.conf, and I upgrade nxp-wlan-sdk in L6.1.55 same initial command and txpower_US.bin without any problem. Re: L6.6.3 iw612 load txpower_cfg fail Platform is i.MX 9302A1 Base on imx-6.6.3-1.0.0 NXP-wlan-sdk SRCREV=:a84df583155bad2a396a937056805550bdf655ab" wlan: version = SDIW612---18.99.2.p66.17-MM6X18423.p6-GPL-(FP92) And wifi_mod_para.conf setting was. SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 fw_name=nxp/sduart_nw61x_v1.bin.se txpwrlimit_cfg=nxp/txpower_US.bin } Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  The problem might be tx_pwr config already downloaded, you download again then error reported. You could try cut off power supply then reboot the system. Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you sahre the version you get these error report? Best Regards Shaun
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S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello I used S32K344 to test the RTC wake-up function. When setting the RTC timing time, I referred to the conversion method in the sample program as shown below: However, the time was deviated during the actual test. What is the reason? BestRegards, Simon Re: S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello Simon, The internal SIRC is not precise: To get precise RTC, use the external SXOSC with 32.768Khz crystal. Regards, Daniel
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Installing new SDK causes automation project migration I have S32 DS 3.5 and S32K344 micro. It was originally set with SDK/RTD V2.0.0 It became necessary to add SDK 4.0.0, so that one project would migrate to 4.0.0 and another project stays at 2.0.0 SDK 4.0.0 gets installed properly and both SDKs appear under project settings. I was expecting that by attaching/detaching SDK I can control which SDK current project would use. However those "attached/detached" check-boxes seems to have no effect. Regardless of that all projects would use 4.0.0 and it is was not possible to keep one project with 2.0.0 Is there a way to avoid that? Re: Installing new SDK causes automation project migration That works, thank you Re: Installing new SDK causes automation project migration Hi @sstelmak  S32DS 3.5 can keep one RTD version only (plus additional extensions packages/stacks). The solution is to install more S32DS instances. Just use different folder name of S32DS like: c:\NXP\S32DS.3.5_RTD_200\ c:\NXP\S32DS.3.5_RTD_400\ And install corresponding RTD package to those instances. Regards, Lukas
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iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi, We have a customer is trying to build the smart-lock application for SLN-VIZN3D-IOTDG board. They followed the instructions in the reference manual:  SLN-VIZN3D-IOT SW Developer Guide (nxp.com) When building the smart_lock main application, they get the following errors: What is the resolutions for the above errors, Here are some old tickets related to same issue: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31: followup - NXP Community Re: RT1064: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31 - NXP Community Thanks. Ayman Sydhom Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi Kerry, The customer confirmed that the app builds fine after downgraded the MCUXpresso. Thanks. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   You are welcome!   I already test both two IDE versions, so, I am sure of this solution.    Yes, after your end customer also make it works, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, kerry Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Thanks Kerry. Will communicate the resolution to our customer and let you know if this solved the issue or not. Regards. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. I know your failed issues reason, your used IDE version is high, as I also test it on my side, my MCUXpresso IDE is the v11.9.0, then same build result to you.   So, I download the older MCUXPresso IDE Version to : V11.4.1, as the get start also mentioned: You can download it from this linker: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE Download the previous version: Then, you need to download the SLN-VIZN3D-IOT SDK https://mcuxpresso.nxp.com/en/builder?hw=SLN-VIZN3D-IOT You need to add it to the MCUXPresso IDE  Now, build your project again, you will find it is OK to use: Please try my method on your side. If you still have question about it, please kindly let me know. If your question is solved, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, Kerry
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