S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello I used S32K344 to test the RTC wake-up function. When setting the RTC timing time, I referred to the conversion method in the sample program as shown below: However, the time was deviated during the actual test. What is the reason? BestRegards, Simon Re: S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello Simon, The internal SIRC is not precise: To get precise RTC, use the external SXOSC with 32.768Khz crystal. Regards, Daniel

Installing new SDK causes automation project migration I have S32 DS 3.5 and S32K344 micro. It was originally set with SDK/RTD V2.0.0 It became necessary to add SDK 4.0.0, so that one project would migrate to 4.0.0 and another project stays at 2.0.0 SDK 4.0.0 gets installed properly and both SDKs appear under project settings. I was expecting that by attaching/detaching SDK I can control which SDK current project would use. However those "attached/detached" check-boxes seems to have no effect. Regardless of that all projects would use 4.0.0 and it is was not possible to keep one project with 2.0.0 Is there a way to avoid that? Re: Installing new SDK causes automation project migration That works, thank you Re: Installing new SDK causes automation project migration Hi @sstelmak  S32DS 3.5 can keep one RTD version only (plus additional extensions packages/stacks). The solution is to install more S32DS instances. Just use different folder name of S32DS like: c:\NXP\S32DS.3.5_RTD_200\ c:\NXP\S32DS.3.5_RTD_400\ And install corresponding RTD package to those instances. Regards, Lukas

iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi, We have a customer is trying to build the smart-lock application for SLN-VIZN3D-IOTDG board. They followed the instructions in the reference manual:  SLN-VIZN3D-IOT SW Developer Guide (nxp.com) When building the smart_lock main application, they get the following errors: What is the resolutions for the above errors, Here are some old tickets related to same issue: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31: followup - NXP Community Re: RT1064: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31 - NXP Community Thanks. Ayman Sydhom Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi Kerry, The customer confirmed that the app builds fine after downgraded the MCUXpresso. Thanks. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   You are welcome!   I already test both two IDE versions, so, I am sure of this solution.    Yes, after your end customer also make it works, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, kerry Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Thanks Kerry. Will communicate the resolution to our customer and let you know if this solved the issue or not. Regards. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. I know your failed issues reason, your used IDE version is high, as I also test it on my side, my MCUXpresso IDE is the v11.9.0, then same build result to you.   So, I download the older MCUXPresso IDE Version to : V11.4.1, as the get start also mentioned: You can download it from this linker: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE Download the previous version: Then, you need to download the SLN-VIZN3D-IOT SDK https://mcuxpresso.nxp.com/en/builder?hw=SLN-VIZN3D-IOT You need to add it to the MCUXPresso IDE  Now, build your project again, you will find it is OK to use: Please try my method on your side. If you still have question about it, please kindly let me know. If your question is solved, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, Kerry

L6.6, sn65dsi83 Error: I'm trying to make sn65dsi84 dsi2lvds bridge working with Linux kernel 6.6.52 (Yocto scartgap). After fixing problems with attaching mipi-dsi to SN65DSI83 driver: IMX8MM-sn65dsi83-yocto-scarthgap-mipi-dsi-is-not-initialized  and correcting LVDS timing parameters in DT: Error-Cannot-find-any-crtc-or-sizes - facing another problem: seems that MIPI-DSI is not sending data: SN65DSI83driver cannot lock PLL because it has DSI source clock. [ 2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110 my devicetree is: /dts-v1/; #include "imx8mm.dtsi" / { panel: panel10inch { width-mm = <210>; height-mm = <157>; compatible = "panel-lvds"; backlight = <&bl_lcd>; data-mapping = "vesa-24"; status = "okay"; enable-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; panel-timing { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; /* */ hfront-porch = <40>; hsync-len = <60>; hback-porch = <220>; /* */ vfront-porch = <7>; vsync-len = <10>; vback-porch = <21>; /* */ vsync-active = <0>; hsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; panel_in: endpoint { remote-endpoint = <&bridge_out>; }; }; }; }; }; &i2c1 { dsi_lvds_bridge: sn65dsi84@2c { compatible = "ti,sn65dsi83"; reg = <0x2c>; enable-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dsi_bridge>; vcc-supply = <&reg_1V8>; status = "okay"; of-depends-on = <&panel>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; bridge_in: endpoint { remote-endpoint = <&mipi_dsi_out>; data-lanes = <1 2 3 4>; }; }; port@2 { reg = <2>; bridge_out: endpoint { remote-endpoint = <&panel_in>; }; }; }; }; }; &lcdif { status = "okay"; }; &mipi_dsi { status = "okay"; port@1 { mipi_dsi_out: endpoint { remote-endpoint = <&bridge_in>; data-lanes = <1 2 3 4>; /*lane-polarities = <1 0 0 0 0>;*/ attach-bridge; }; }; }; bootlog is attached. Re: L6.6, sn65dsi83 Error: Found strange thing: [    2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110 [    2.948106] imx_sec_dsim_drv 32e10000.mipi_dsi: imx_sec_dsim_encoder_atomic_enable: Enter [    2.951027] sn65dsi83 0-002c: sn65dsi83_atomic_enable: Enter [    2.956980] sn65dsi83 0-002c: Unexpected link status 0x01 The sn65dsi83 probe function pries to lock PLL from MIPI-DSI before imx_sec_dsim_encoder_atomic_enable() function ensbles it. Moved piece of code that sets PLL to sn65dsi83_atomic_enable() function. Works now!

Port is not opening for enable communication using RPMSGs on i.MX93 Hi all,  Hope you are doing well. I am facing issue while trying to open the port of RPMSG by enabling tty driver. Please find below basic info. -> SDK: SDK_24_12_00_MCIMX93-EVK -> Project: rpmsg_lite_str_echo_rtos -> Development kit: Digi ConnectCore 91/93  The Procedure I followed: 1. boot up the Yocto Linux result: [ 0.022125] imx rpmsg driver is registered. 2. Compile the rpmsg_lite_str_echo_rtos in ubuntu and created .elf file 3. Transfer the elf file into /dev/firmware folder of i.MX93 4. enable the tty driver using modprobe imx_rpmsg_tty command on i.MX93 board 5. Load the firmware and run it using RemoteProc framework 6. I am getting data on LPUART4 as per below result on serial port: RPMSG String Echo FreeRTOS RTOS API Demo... 7. But it stuck on "rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK);" function Also, I am not getting the ttyRPMSG* serial port on /dev/ folder. Does anybody know how to solve it? and what are potential causes of this problem? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano i.MX2x i.MX50 i.MX51 i.MX53 i.MX6 All i.MX6DL i.MX6Dual i.MX6DualPlus | 6QuadPlus i.MX6Quad i.MX6S i.MX6SL i.MX6SoloX i.MX6UL i.MX7Dual i.MX7Solo i.MX7ULP i.MX8ULP i.MXRT Linux Yocto Project Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi @Zhiming_Liu ,  Thanks for the prompt response. I have few more questions about SDK: 1. When will the 25.06 SDK release? 2. How are the SDK versioning numbers spread out from 2.16 to 15.06 to 25.06? I want to understand this to select the SDK. Thanks Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, The SDK hub for 24.12 or 25.03 miss some configuration about rpmsg which cause the SDK generated from SDK hub can't use rpmsg feature. We will fix this issue in SDK 15.06 and please use SDK2.16 before SDK 25.06 release. Best Regards, Zhiming Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hey @Zhiming_Liu  I am able to download the SDK now. I compiled and executed the rpmsg_lite_str_echo_rtos_imxcm33 example and it was able to create the ttyRPMSG30 port and able to send test string from master (A55) to slave (M33) processor cores. Additionally, I tried to compare both the SDKs (2.16 and 24.12) to get to know if I am missing anything but unfortunately was not able to find anything as of now. I want to run RPMSG in SDK 24.12 as my project is based on that, so could you please provide me any information on how can I achieve that? I asked this in my first post but so far did not get any info on this so I will appreciate it. I also wanted to know why rpmsg example is not working on 24.12 or 25.03 either and when it would be fixed? Thanks. Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi  Thanks for reply. I couldn't be able to download the SDK version 2.16 or 2.15 as well. Please see the problem in the image. Now do you have other option to download it OR if you have 2.16 Version of SDK, could you provide me that along with its example directories? Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, You can select version here: Best Regards, Zhiming Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi  I am using "Dashboard | MCUXpresso SDK Builder" sdk and aould you tell me, how it differs with "https://github.com/nxp-mcuxpresso/mcux-sdk" sdk? The board I am using it is Digi ConnectCore 91/93. Also, I followed guideline from "https://docs.digi.com/resources/documentation/digidocs/embedded/dey/4.0/cc93/yocto-develop-cortex-apps_t_93.html" . Other than these, if you have any queries, please let me know. Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi Zhiming_Liu, Thanks for reply. Can you tell me how to download the lower version of SDK as you suggested SDK2.16? Although, I tried to download it, but I couldn't find any option to change the SDK version from MCUXpresso SDK Dashboard website. Could you guide me to this? Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, Please use SDK2.16 which can work. Best Regards, Zhiming

S32K358 hi sir： S32K358: How to do core 0 after the initialization clock is complete, then start core 2. I find that "MC_ME" has no kernel 2 related register. Re: S32K358 Hi nxpuser007: I already can debug core0 and core2 in the same time by s32ds, debug mode is OK. When I power off and power on the system, only core0 bootup and run, core2 don't do anything, do you have any experience about this problem? Thanks Br, BillWen Re: S32K358 When you step the code, where does it fail exactly? Re: S32K358 Why does starting kernel 2 and then initializing IPCF go to hardfault？ Re: S32K358 Hi @nxpuser007  take a look at this thread, there's an example how to start second core by software: https://community.nxp.com/t5/S32K/S32K324-seperate-core-code/td-p/1789569 Regards, Lukas

Modifying the ld file results in a compilation error due to overlapping sections Hi, developers, I encountered a compilation error with GCC when configuring DTCM as SRAM using S32K312. I haven't made any progress in finding the cause of the error. I referred to the community topic discussion, "How to modify the LD file to use ITCM and DTCM content," but following the manual and the discussion's LD file configuration led to a compilation error. Can anyone help me resolve this issue? I tried various versions of GCC, such as GCC9.2.0, GCC 10.2.0, GCC 10.3.1, GCC12.2.0。But all resulted in the same error. IDE: vscode cmake version: 3.28.1 GCC12.2.0 Erroe ScreenshootGCC12.2.0 Erroe Screenshoot GCC 10.2.0 Error ScreenShotGCC 10.2.0 Error ScreenShot Reference link for the topic discussion   https://community.nxp.com/t5/S32K/How-to-use-DTCM-1-memory-in-S32K314-controllers/m-p/1663024 https://community.nxp.com/t5/S32K/DTCM-ITCM-example/m-p/1606827#M21008 https://community.nxp.com/t5/S32K/Regarding-the-RAM-location-for-the-s32k312/m-p/1876369 https://community.nxp.com/t5/S32K/How-to-solve-the-RAM-resource-is-not-enough-on-S32K312/m-p/1538940#M18373 https://community.nxp.com/t5/i-MX-RT/uTasker-Compile-Error-in-MCUXpresso/m-p/1535822 @danielmartynek  @lukaszadrapa @davidtosenovjan Can you help me with this issue? Thank you. Regards, Ags  Re: Modifying the ld file results in a compilation error due to overlapping sections hi, @lukaszadrapa   thaks your response. i compare the link file you provided.  there wasn't  much difference.   I searched for a solution and found that the issue lies in the LD file configuration. The attribute "os_globle" was declared in the program but not configured in the LD file, leading to the error. In the LD.pdf documentation on overlapping, I identified this problem. Re: Modifying the ld file results in a compilation error due to overlapping sections Hi @DennyZhang  attached is linker file from RTD 4.0.0 which already contains definitions for DTCM. It's working on my side. Regards, Lukas 回复： Modifying the ld file results in a compilation error due to overlapping sections This discussion has a similar problem Re: How can I put my callback function into ITCM memory ? S32K344 - NXP Community

i.MX8 ULP Solo Emulation We want to evaluate whether the performance of i.MX8 ULP Solo/Single Core is acceptable to run latest NXP Android 14 release. Is there a u-boot or adb/debug console commands that we can run in real time to enable single core mode in i.MX8ULP Evaluation Kit (which has dual core)? Re: i.MX8 ULP Solo Emulation This save my time. Thanks for your info. Re: i.MX8 ULP Solo Emulation Thanks. It works!. evk_8ulp:/ $ cat /proc/cpuinfo processor : 0 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 evk_8ulp:/ Re: i.MX8 ULP Solo Emulation please try "setenv append_bootargs maxcpus=1 " Re: i.MX8 ULP Solo Emulation On Android 14, Here is the uboot printenv => printenv arch=arm baudrate=115200 board=imx8ulp_evk board_name=imx8ulp_evk bootcmd=boota mmc0 bootdelay=2 cpu=armv8 emmc_dev=0 ethaddr=00:04:9f:08:73:f6 ethprime=FEC fastboot_dev=mmc0 fdt_high=0xffffffffffffffff fdtcontroladdr=a3de8210 initrd_high=0xffffffffffffffff loadaddr=0x80400000 sd_dev=2 sec_boot=yes serial#=5fe72827b1363228 soc=imx8ulp soc_type=imx8ulp splashimage=0x90000000 splashpos=m,m vendor=freescale Environment size: 409/8188 bytes I try to "setenv maxcpus 1", and the android still boot up with 2 CPUs 130|evk_8ulp:/ $ cat /proc/cpuinfo processor : 0 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 processor : 1 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 The way that android set kernel parameters seems different from that of Linux. Please advise. Re: i.MX8 ULP Solo Emulation It should be the same as u-boot also is the bootloader in Android 14. Re: i.MX8 ULP Solo Emulation Thanks. That's for Linux. Does Android 14 has similar setting? Re: i.MX8 ULP Solo Emulation There is kernel parameter "maxcpus" which is maximum number of processors that kernel should use. For more information, you could refer to the Table 11 in the Release Notes below. i.MX Linux Release Notes (nxp.com)

JN5189 Hello, we know that in JN5189 sleep a total of PWR_E_SLEEP_OSCON_RAMON = 1, /*32Khz osc on and ram on*/ PWR_E_SLEEP_OSCON_RAMOFF = 2, /*32Khz Osc on and Ram off*/ PWR_E_SLEEP_OSCOFF_RAMON = 5, /*32Khz Osc off and Ram on*/ PWR_E_SLEEP_OSCOFF_RAMOFF = 6, /*32Khz Osc off and Ram off*/ Four modes, when I change the sleep mode from PWR_E_SLEEP_OSCOFF_RAMOFF to PWR_E_SLEEP_OSCON_RAMOFF.JN5189 cannot sleep, when performing PWR_ChangeDeepSleepMode (PWR_E_SLEEP_OSCON_RAMOFF); The system will restart , do I need to make other configurations in this mode? Why does the system restart as soon as it is executed? I want it to sleep all the time, and then I pass wake-up clock function ： WTIMER_StartTimerLarge(1, 128000); Wake up the system. Re: JN5189 Hello, We do not have an example with this type of conditions you are mentioning, but you can either determine by a wakeup timer when you will like to take out the system from the IDLE state and suspend the low power functionality. I highly recommend to give a look to the Connectivity Framework Reference Manual that is locate on the SDK->docs->wireless -> common. Specially into the chapters 3.4 for timers and 3.16 for low power details. Re: JN5189 Glad to hear from you, I've learned all of this, and now what I want to do is sleep the End Device for 10 seconds when End Device idle, and then wake up the system through wake timers. How do I write a program? Now I can't control the sleep time of the End Device.If you know what functions you can use to do this, please let me know.Thank you Re: JN5189 Hello, Thank you for the information and details, according to JN-AN-1243. as you are using this application on End Device mode, the End Device functionality by default is that the End Device should be sleepy 'Rx Off when idle'. The End Device will most likely be asleep and should wake up periodically to poll for incoming messages. That is the reason you see this feature on the default configuration of the AN. When the system is idle or if there is no activity in progress, main_task should suspend CPU operation with PWR_EnterLowPower(). I also recommend to give look to the Connectivity Framework Reference Manual that is locate on the SDK->docs->wireless -> common. Re: JN5189 The picture I just used was wrong, and the picture I tested today is as follows. Re: JN5189 Hello, I have used the SDK version 2.6.13 today to compile the latest AN1243 file, but the result is still the same.When sleep mode is  PWR_E_SLEEP_OSCON_RAMOFF the system will restart. I guess this shouldn't be an issue with the SDK version, but if you have time, I'd like you to test it out and share your results with me. Re: JN5189 Hello, Thank you in advance for the information can you please compile with this SDK version this is version 2.6.13 please also use the latest version of the AN. And please let me know the results. Re: JN5189 Hello, I have successfully compiled AN-1243 v2.7 using SDK2.6.8 this afternoon. But the same problem still exists, sleep can be normal when the sleep mode is set to PWR_ChangeDeepSleepMode(PWR_E_SLEEP_OSCOFF_RAMOFF) If the sleep mode is PWR_ChangeDeepSleepMode(PWR_E_SLEEP_OSCON_RAMOFF), the system will restart. The code I changed is as follows, and I changed it in the APP_cbTimerPoll function of app_end_device_node.c. Re: JN5189 Glad to receive your answer, I've tried to use SDK_2_6_8_JN5189DK6 before, but there is a problem with the compilation. make: *** No rule to make target '../../../../../../SDKPackages/SDKPackages/SDK_2_6_8_JN5189DK6/middleware/wireless/zigbee/tools/PDUMConfig/Source/PDUMConfig', needed by '../../../EndDevice/Source/pdum_gen.c'. Stop. I'm using SDK_2_6_5_JN5189DK6 can compile through. So how do I fix this. Re: JN5189 Hello, I really appreciate the information proportionated, I have the following observations. At the very end of the AN document you can find the revision history on how we recommend to try each version of the AN and which SDK version is recommend for each one.  For this specific case you mentioned that you ae using the AN 2.7 version with the SDK version 2.6.5. We have a newly version that I recommend on this specific case, can you please help upgrading your SDK version and you’re an version I would also include the image of the Revision History on this post. Re: JN5189 The following is a supplement to the answer I just answered, and the routine I used was the Zigbee 3.0 Base Device Template.But I was using version 2007 Re: JN5189 I'm very glad to hear from you.I'll give you more detailed information below 1.I'm using the example downloaded from the official website, and the file is JN-AN-1243. Its version number is 2007 2.I'm using SDK version 2.6.5 3.I only changed the sleep mode in the function APP_cbTimerPoll under app_end_device_node.c in EndDevice, and nothing else was changed Re: JN5189 Hello, Thank you for contacting NXP support. I'm looking forward to replicate your case can you please help me with some information in order to perform a test: Are you using an SDK example or is this a custom example? Can you please also share with me the SDK version you are currently using. Apart from the low power mode modification did you perform any other modification. I will really appreciate this information and details.

MIMXRT1176CVM8A (MIMXRT1176 Family's): For possibility of using GPIO SNVS as normal GPIOs. Hi Team, We are using MIMXRT1176CVM8A in our design whose SNVS bank's GPIO are not Tamper pins. We are not connecting battery to VDD_SNVS_IN since we have separate battery backed up RTC interface to the controller. We have connected 3.3V external supply to VDD_SNVS_IN. The output of the VDD_SNVS_ANA is 1.8V which is given to NVCC_SNVS supply.  However, owing to GPIO shortage in our design, we are thinking of using the SNVS Bank's GPIO as normal GPIO pins.  But if we connect the VDD_SNVS_ANA to NVCC_SNVS, then the max source/sink capability of the all the pins of SNVS bank comes to 1mA which is way below what we need. Hence, we are thinking of connecting external VDD_1V8 to the NVCC_SNVS. Can you please look into this and suggest if it can be done.?  Our intention is to connect external 1.8V to NVCC_SNVS and make use of the SNVS Bank's GPIO to have higher current drive capability to drive the MOSFET drivers of LEDs Re: MIMXRT1176CVM8A (MIMXRT1176 Family's): For possibility of using GPIO SNVS as normal GPIOs. The chip internal LDO VDD_SNVS_ANA should be tied together with NVCC_SNVS. I do not suggest using a configuration outside our recommendations. Best regards, Omar

Rom Bootloader not decrypting downloaded image from Internal Flash Hi All, I'm currently working on OTAP update. I have made my BLE device as client. I'm able to communicate with my device and Mobile using IOT Toolbox app, bleota file is transferred successfully to my PCB(having KW45 microcontroller) But after download my application is not running. I can also see using J-mem in the flash that file is downloaded. After system reset Rom Bootloader tries to install the Image from the flash but Bootloader could not decrypt the downloaded image fully and stops in between(I verified by seeing the memory location). Could you please help me out to solve this issue. One more point I would like to add, When I flash same file but in sb3 format using uart i.e. blhost -p COM8 receive-sb-file application.sb3, it flashes properly and my application is running. KW45 #OTAP Kinetis W Series MCUs Re: Rom Bootloader not decrypting downloaded image from Internal Flash Thank you, after updating NBU image and new sdk framework and driver, OTAP works fine now. Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hello, It is necessary to work with the matching NBU image for the SDK version of the application you are working with. This means that when you download your SDK, prior to loading any wireless SDK example, update your NBU image with the provided binaries in the following folder of the SDK. If you are using a custom board, with your own keys, you also need to march the NBU version and the SDK application you took as a base. Regards, Ricardo Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hi, I'm facing one more issue, I have sdk SDK_2_12_7_KW45B41Z82xxxA and we found out new ble controller binary kw45b41_nbu_ble_1_9_12_3.xip file, I have generated the sb3 file out of it because I'm using our own pcb and keys and certs, I can successfully flash generated sb3 via blhost utility, but when I flash application code through MCuxpresso debugger, application code is going to fault state, please refer the below image and when I revert to old sb3 file(this was also generated a year ago using this kw45b41_nbu_ble_1_9_10_0.xip verison), this fault is not coming, code runs fine. Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hi, below are the steps: Selected OTA protocol as OTAP Bluetooth LE Processor kw45 Select the bin/s19 file, selected application core Used the encryption key described in sb3kdk.txt I have used JSON file configurator as described in below image Replaced our keys in Keys_and_certs folder I have used below configuration for JSON for creating sb3 container After this two windows pop out that shows authentication key and encryption keys. After that I save generated sb3 file as binary in bleota format and this file I use to transfer via bluetooth.  NOTE: I have also used ISK option in JSON configuration, but it didn't change anything. Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hello, Could you please clarify the steps followed using the Over the air Programming application? Did you follow the Over The Air Programming User Guide? Regards, Ricardo Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hi, I'm uisng SDK verison 2.12.7, I have integrated otap_client example to my project using application developers guide. Bluethooth connection works fine for us, I can see my device in the NXP toolbox application, I can download whole application into the mentioned flash location. For generating new signed image, I have used Over the air Programming application, I'm using old root certificates files (generated by using SPSDK python files, OEM keys and certificate, for your reference please refer to attached image) which we have generated to burn the fuses at the time of flashing BLE firmware provided by NXP. I have also found FW update status in OTACFG register, it is returning 0x4412d283 at location 0x02006020, it indicates failure to process sb3 file or failure to erase/write update status to OTACFG page.  Thanks & Regards SShrivastava Re: Rom Bootloader not decrypting downloaded image from Internal Flash Hello, Hope you are doing well. Could you please clarify what SDK version are you using? Are you using the otap_client example as a base? What is the procedure you are following? Best Regards, Ricardo

1170 上的 M7 可以使用哪些 OCRAM？ 我遇到了一些问题，我认为这些问题可能是由于我对 1170 上的 FLEXRAM 的误解造成的...... 根据内存映射（参考手册第 3 章），似乎有三个不同的 OCRAM 块：OCRAM M7、OCRAM1 和 OCRAM2。我在 RM 中找不到任何信息表明哪个块是属于 FLEXRAM 的 OCRAM。 OCRAM 块实际上是 FLEXRAM 的一部分吗？ 另外两个真的具有 RM 内存映射中显示的大小吗？ 回复：1170 上的 M7 可以使用哪些 OCRAM？ @Kan_Li你能确认我的总结是否正确吗？ 回复：1170 上的 M7 可以使用哪些 OCRAM？ 好的，感谢您的快速回复。这非常有帮助。 所以让我澄清一下这一点，因为我发现 OCRAM/FLEXRAM 文档有点令人困惑...... 关于 OCRAM，从编程的角度来看（让我们忽略各种总线连接的内部工作原理，为此，假设我只使用 M7 核心），可能存在三种不同的内部 OCRAM 块： OCRAM1：位于 0x20240000，大小 = 512K OCRAM2：位于 0x202c0000，大小 = 512K OCRAM_M7 位于 0x20360000，大小 = 128K + flexram 配置分配给它的任何内容。 因此，即使我使用 flexram 配置设置 OCRAM=0，在 0x20360000 处仍然有 128K 的空间。 这一切都准确吗？

FCCU EOUT on fault Hello, I'm trying to test EOUT output on an MR-CANHUBK344 board. Before calling eMcem_Init, the pulldown keeps FCCU_ERR0 at 0v, and the pull-up keeps FCCU_ERR1 at 3.3v. If I set FCCU_CFG to 0x01000080 or 0x01000880 using eMcem_Init, EOUT behaves how I would expect: 1. FCCU_STAT starts at 0x10 2. ERR0 changes to 3.3v, and ERR1 changes to 0v 3. I call eMcem_Dcm_AssertSWFault(0) 4. I see that ERR0 changes to 0v, and ERR1 changes to 3.3v 5. I see that FCCU_STAT is now 0x2B (fault state) But if I set FCCU_CFG to 0x01000280 or 0x01000A80, I do not see EOUT respond: 1. FCCU_STAT starts at 0x20 2. ERR0 stays at 0v, and ERR1 stays at 3.3v (no change, which is expected) 3. I call eMcem_Dcm_AssertSWFault(0) 4. I see that ERR0 and ERR1 do not change (I don't understand why) 5. I see that FCCU_STAT is now 0x1B (fault state) What am I missing in the 0x01000280 or 0x01000A80 cases? I had expected ERR0 and ERR1 to change levels at the time of fault. Re: FCCU EOUT on fault Thanks for the help Peter, this worked! Re: FCCU EOUT on fault Hello, I spend some time on further testing, and the issue is in pin control in safe mode. SIUL2. MSCR [SMC] - pins are not controlled in safe mode (fault state) if the SMC is not set to 1. After I have set SMC = 1 the FCCU fault protocols propagate correctly on the EOUT pins. Let me know if it solves the issue. Best regards, Peter Re: FCCU EOUT on fault Hello, I have escalated it internally to see if application team can provide some insights here. Best regards, Peter Re: FCCU EOUT on fault Thanks Peter. It looks like I'm seeing that the EOUT output is open drain when in the faulted state. And that seems to be the case whether OBE output buffers are enabled or disabled.   To test this, I put a 22Kohm resistor between ERR0 and ERR1. So that I would see voltages other than 0v and 3.3v any time the EOUT pins are hi-z. If you look at the red "2" timing marker in both of these screenshots, you'll see that ERR0 and ERR1 go to hi-z at fault. These screenshots have OBE=0. But I saw the same behavior after re-running the test with OBE=1. In case my analog sampling was not fast enough to catch a brief push-pull edge, I also tried edge triggering (without the 22Kohm resistor). And I do not see an edge on fault. I'm using the eMcem driver here.     Re: FCCU EOUT on fault Hello, After measurements, I basically see the same behaviour as you. I have escalated it to the safety team, to see if anything is missing. Note that I haven't used any driver, so I expect there is either something missing in my tests, or there is an issue. I will feedback you as soon as I get any explanation. Best regards, Peter Re: FCCU EOUT on fault Hello, I have did the measurement once again. 2. Bi-stable protocol PS=0 Normal aligned with Reference manual: Fault -same config as above but NCF_E enabled 2. Bi-stable protocol PS=1 Normal Fault -same config as above but NCF_E enabled I am not able to catch the fault state on the scope. 3. Bi-stable protocol PS=0 and CM=1 I am not able to catch the fault state on the scope. I will add measurement later when I find out what is the root cause. Best regards, Peter   Re: FCCU EOUT on fault Thanks Peter. Maybe there are missing screenshots. In the two which include EOUT_SIG_E0, it is set to 0x00. And I don't see MSCR in any screenshots. Re: FCCU EOUT on fault Hello, Normal Mode and Fault Mode screenshots, similar to what I see. Why is this? Shouldn't they be changing? Or is there something missing with the configuration? Yes, looks like I have posted twice the same screenshot. The fault/config mode will have the same behavior (fault) on outputs. To measure this you will need a trigger on oscilloscope to catch the fault state as there is only small time window for fault. Alarm state. Once expired the FCCU or FOSU will reset the device and with it also the pins and config of FCCU. 1. SSS=1 setting for MSCR143 and MSCR144 2. Non-critical Fault-State EOUT Signaling Enable (EOUT_SIG_EN0 = 0x000000ff) Yes, this is essential for EOUT signaling. My configuration of FCCU can be seen on debugger screenshots. + the pins config. Best regards, Peter Re: FCCU EOUT on fault When in fault mode with EOUT enabled, does the FCCU set output on ERR0 and ERR1 with push-pull, or with open drain / hi-z? Re: FCCU EOUT on fault Thanks Peter. It looks like ERR0 and ERR1 pins did not change between your Normal Mode and Fault Mode screenshots, similar to what I see. Why is this? Shouldn't they be changing? Or is there something missing with the configuration? By the way, I am also doing these two things discussed in the previous support case #00696653 before testing. Were these also set for your measurements above? 1. SSS=1 setting for MSCR143 and MSCR144 2. Non-critical Fault-State EOUT Signaling Enable (EOUT_SIG_EN0 = 0x000000ff) Thank you Mike Re: FCCU EOUT on fault Hello, I have did the measurements: Here are the results: 1. BI-stable protocol PS=1 and measurement: 2. Bi-stable protocol PS=0 and measurement  3. Bi-stable protocol PS=0 and SM=1 normal mode Fault mode Best regards, Peter  

Alternative Programming Solutions for NTM88 and Accessing Unique ID During Programming Hello, I’m currently programming the NTM88 using CodeWarrior with a PE Micro Multilink, but this setup is not feasible for production. Is there an alternative programmer and software that can securely program the NTM88 and is better suited for production environments? Additionally, is it possible to access and read the unique ID of the NTM88 during the programming process? Any guidance or recommendations would be greatly appreciated. Thank you in advance! Best regards, Re: Alternative Programming Solutions for NTM88 and Accessing Unique ID During Programming Hello, The unique ID is programmed in flash, so it can be read like any other portion of flash. So yes, it can be read during programming using Cyclone programmer, or any other tool. Note that the unique ID is stored in the trim section, along with the other unique coefficients of the device. The user must be careful not to erase the trim page during the programming process. Hope this helps. Re: Alternative Programming Solutions for NTM88 and Accessing Unique ID During Programming Hello Erika, Thank you for your response and for pointing me toward the Cyclone Production Programmer and I appreciate the detailed information. I still have one question regarding the unique ID of the NTM88: Is there a way to retrieve and visualize the unique ID during the programming process using these tools? This would be crucial for our production workflow. Thank you again for your assistance! Re: Alternative Programming Solutions for NTM88 and Accessing Unique ID During Programming Hello,  The NTM88, can be effectively programmed using P&E Micro tools. For development purposes. For production environments, P&E Micro provides a variety of tools designed to streamline programming processes. One such example is the Cyclone Production Programmer, which allows for standalone, automated programming and is well-suited for integration into production lines. More information on the different tools available for development and production can be found here: http://www.pemicro.com/products/product_viewDetails.cfm?product_id=15320137&productTab=2 Hope this helps.

在s32K312中执行擦除操作后，我得到了PES位设置 亲爱的朋友们： 我想擦除并写入该扇区，但擦除后遇到了问题。首先，我将 flash_drv 代码复制到 ram 中。 1.我尝试擦除 00420000 并且长度为 2K（实际上我将擦除 8*8K 长度） 2.我解锁了SSPELOCK[0]的bit2，因为这个地址位于S32K312的block0中 3.我将地址0x00420000写入PFCPGM_PEADR_L 4. 我将 IP_FLASH->DATA[0] 设置为 0xFFFFFFFF，但我不知道这是否有必要，因为我在用户手册中没有找到此操作 5.我设置了MCR寄存器中的ERS位 事实上，执行步骤4后，我在监视窗口中遇到了MCRS中的PES位设置，如果我标记步骤4，那么在步骤5之后我也遇到了PES位设置。 你能帮助我吗？谢谢你 回复：在s32K312中执行擦除操作后，我得到了PES位设置 可能是因为系统时钟配置必须精确设置为 RM 第 24.7.2 节中列出的时钟选项之一系统时钟配置。 请检查所有时钟并告知我。 谢谢

PCA9617波形 该电路与 PCA9600 配合良好，但为了降低成本，我修改了电路板以使用 PCA9617 并检查了波形。 观察时钟波形，没有特别的失真， 所以看起来没有问题，但是在数据波形输出低电平的时候， 我观察到在时钟下降沿被拉高的波形。 我想知道这是否是由于时钟和数据之间的串扰造成的（安装 PCA9600DPZ 时没有问题）， 或者是修改电路板图案（图案切割/电缆焊接）的效果？ 我将非常感激您的意见。

PCA9617 waveform This circuit works fine with the PCA9600, but to reduce costs, I modified the board to use a PCA9617 and checked the waveform. Looking at the clock waveform, there is no particular distortion, so there doesn't seem to be a problem, but at the point where the data waveform is outputting Low, I observed a waveform that was pulled High at the falling edge of the clock. I wonder if this is due to crosstalk between the clock and data (there is no problem when the PCA9600DPZ is installed), or is it an effect of modifying the board pattern (pattern cutting/cable soldering)? I would appreciate your opinions. Re: PCA9617 waveform HI yuji0935  I think it's an effect of modifying the board pattern  (pattern cutting/cable soldering)about this glitch. Thanks! BR

Eth_43_PFE MasterProject_RDB2 こんにちは S32G-VPN-GDLBOX 900-47800 REV D1 と SW32G_RTD_4.4_4.0.2_D2306 を使用しています。 PFE-DRV_S32G_M7_MCAL_1.4.0からMasterProject_RDB2 EB Tresos環境でテストしています。イーサネットポートPFE_MAC1とPFE_MAC2は問題なく動作しますが、ポート1〜10 PFE_MAC0使用したいと思います。EB Tresos では、Serdes_1 の SerdesChannel_0 に "Use XPCS0" を追加し、Eth_43_PFE では EthCtrlPort を EMAC1 から EMAC0 に変更EthCtrlConfig_0。 ボード上のスイッチSW8がオン、SW10.1がオン、SW10.2がオフ、SW12.1がオン、SW12.2がオンオフ。 D33が緑色に点灯します。 残念ながら、1番から10番までのポートPFE_MAC0まだ通信が確立できていないので、どなたか解決策を思いつく方がいらっしゃいましたらお願いしたいと思います。 ご返信をよろしくお願いいたします。 よろしくお願いいたします WON0020さん、@tomasmrovec 日時:Eth_43_PFE MasterProject_RDB2 こんにちは McuGENCTRL1_EMAC0 Generic Control 1をMCU制御（MCU）の下に設定しましたが、 XPCS_0 2500 Mbps までの速度 (Serdes)、 EMAC0 (Eth_43_PFE) の 2500M への EthCtrlMacLayerSpeed そして今、私はPFE_MAC0をストックSJA1110 FWで使うことができるようになりました。 ありがとうございました。 日時:Eth_43_PFE MasterProject_RDB2 こんにちは@won0020、 この問題は、SJA1110内部FW/設定に関連しているようです。残念ながら、それは私の範囲外であるため、私はあなたを助けることはできません。https://community.nxp.com/t5/Other-NXP-Products/bd-p/other で新しい質問をしてください、そこでは、誰かがSJA1110に関連する問題であなたを助けることができるはずです。ご不便をおかけして申し訳ございません。 この情報が役に立ったかどうか教えてください。 日時:Eth_43_PFE MasterProject_RDB2 こんにちは GMAC0のVLANタグは次のように設定できます。 1) (Eth_FrameType)0x86DD Gmac_Ip_VlanConfigType vlanConfig = { .EnDoubleVlan = FALSE、 .EnSvlan = FALSE、 .OuterVlanIns = GMAC_VLAN_TAG_INSERTION、 .OuterVlanStrip = GMAC_VLAN_TAG_DO_NOT_STRIP、 }; Gmac_Ip_EnableVlan(INST_GMAC_0, &vlanConfig); Gmac_Ip_SetTxOuterVlanTagForInsertion(INST_GMAC_0, 0, GMAC_VLAN_TYPE_C_VLAN, 2); 2) (Eth_FrameType)0x8100 uint8_t tst_ipv6_udp_frm_data[] = { /* VLANタグ(2バイト)*/ 0x00U、0x02U、 /* イーサネットタイプ (2 バイト) */ 0x86U、0xDDU、 ... } どちらも、GMAC0をベクター VN5610Aに直接接続すると機能しますが、残念ながら、SJA1110Aを介してGMAC0を接続すると機能します。VLANタグを取り外した場合にのみメッセージを受信できます。 日時:Eth_43_PFE MasterProject_RDB2 こんにちは、@won0020、 このページは、S32G-PFE-M-Master-A-Slave-Simple-Demoのアプリケーションに役立つ場合があります。 日時:Eth_43_PFE MasterProject_RDB2 こんにちは 現在、外部ケーブルでgmac0接続を使用してsja1110aを使用しています。NDAをお持ちの同僚に、SDKを使用してsja110aをpfe_mac0を使用するように構成するように依頼しましたが、それが役立つかどうかお知らせします。 さらに、VLANを含む通信はスイッチを通過しません。これもSDKを使用して解決できると思います。

Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display Hi, I have deployed Linux (based on IMX Yocto Project LF6.1.55_2.2.0) on a custom iMX93 board. A MIPI (4 lanes) LCD Display is connected to the board. I am using a custom DTS with the kernel. The panel driver has been updated with manufacturer's provided initialization code and timing settings have been addressed. The panel shows the correct testing bar image when running the following modetest command: modetest -M imx-drm -D 1 -a -s 35@33:800x1280 -P 31@33:800x1280 Weston, however, doesn't start with 'use-g2d=true' (weston.ini). With 'use-g2d' disabled, weston will start, however all the windows will render very slow on the display panel.  When I test with '/usr/bin/weston-simple-egl', it reports ~8 fps, instead of ~60 fps (as I would expect when using g2d).  Here is the extract from the weston.log with g2d related errors: [10:02:08.254] weston 11.0.3 https://wayland.freedesktop.org Bug reports to: https://gitlab.freedesktop.org/wayland/weston/issues/ Build: 10.0.0-661-ga509c319+ [10:02:08.255] Command line: /usr/bin/weston --log=/run/user/0/weston.log --modules=systemd-notify.so [10:02:08.255] OS: Linux, 6.1.55-00011-g95af9f676d77-dirty, #109 SMP PREEMPT Mon Apr 8 11:44:52 CDT 2024, aarch64 [10:02:08.255] Flight recorder: enabled [10:02:08.255] Using config file '/etc/xdg/weston/weston.ini' [10:02:08.255] Output repaint window is 16 ms maximum. [10:02:08.255] Loading module '/usr/lib/libweston-11/drm-backend.so' [10:02:08.259] initializing drm backend [10:02:08.259] Trying logind launcher... [10:02:08.275] logind: session control granted [10:02:08.281] using /dev/dri/card0 [10:02:08.281] DRM: supports atomic modesetting [10:02:08.281] DRM: does not support GBM modifiers [10:02:08.281] DRM: supports picture aspect ratio [10:02:08.282] Loading module '/usr/lib/libweston-11/g2d-renderer.so' [10:02:08.314] g2d_open fail. [10:02:08.314] g2d_renderer_create faile. [10:02:08.315] failed to initialize g2d render My /etc/xdg/weston/weston.ini: [core] use-g2d=true repaint-window=16 gbm-format=argb8888 idle-time=0 #enable-overlay-view=1 [shell] [libinput] touchscreen_calibrator=true #[output] #name=HDMI-A-1 #mode=1920x1080@60 #transform=rotate-90 #[output] #name=HDMI-A-2 #mode=off # WIDTHxHEIGHT Resolution size width and height in pixels # off Disables the output # preferred Uses the preferred mode # current Uses the current crt controller mode #transform=rotate-90 [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize #start-on-startup=true I am running an imx-image-multimedia that was built with fsl-imx-wayland distro for iMX93 MCU. It seems like the following call fails within g2d-renderer.c : if(g2d_open(&gr->handle)) { weston_log("g2d_open fail.\n"); return -1; } Any idea why weston crashes at start when trying to open a g2d handle ? Has anyone experienced a similar issue?  Any input appreciated. Re: Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display Hi Abt, thank you for the response. Unfortunately, I've already tried adding this node to the DT, but I'm still encountering the same issue. I'll will have to keep looking into this. If I find the cause i will share it here! Re: Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display Hi elFunko, As tim_cargt mentioned, this is the DT entry that I was missing: &epxp { status = "okay"; };   Re: Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display Hi Abt, I'm currently facing the same issue. Could you perhaps share what the missing setting in the device tree was? That would be appreciated! Re: Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display Make sure the pixel pipleline is enabled in the device tree. &epxp { status = "okay"; }; Re: Weston doesn't start with g2d enabled on a custom imx93 board with MIPI display I figured it out. I was missing a setting in the device tree.

How to increase the hdmi clock on the imx8Mplus How to increase the HDMI clock in the samsung_phy_pll_cfg function in the drivers/phy/freescale/phy-fsl-samsung-hdmi.c file, given the screen resolution is 800x480 and the clock is 32MHz. Re: How to increase the hdmi clock on the imx8Mplus Shaojun,the problem has been resolved. Thanks for your support. Re: How to increase the hdmi clock on the imx8Mplus Please apply below patch You may need to add "video=HDMI-A-1:800x480@60" in uboot command line. diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index d1e93e5b9207..221e71ae2341 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -136,6 +136,15 @@ const struct phy_config samsung_phy_pll_cfg[] = { 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, }, + }, { + 32000000, { + 0x00, 0xD1, 0x36, 0x70, 0xAD, 0xA0, 0x85, 0x42, + 0x4F, 0x30, 0x33, 0x65, 0x00, 0xC1, 0x24, 0x80, + 0x6C, 0xF2, 0x67, 0x00, 0x10, 0x87, 0x30, 0x3A, + 0x74, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00, + }, }, { 33750000, { 0x00, 0xD1, 0x70, 0xF4, 0x82, 0x01, 0x80, 0x40, Re: How to increase the hdmi clock on the imx8Mplus Will check it.