SJA1110 CBS configuration Hi,  I am using SJA110 - EVM board to test credit based shaping parameters. I have  CBS parameters as below IdleSlope = 50Mbps SendSlope=-50Mbps Lo_credit = -750 Hi_Credit = 73 How can set these values in CBS registers (Explanation given in user manual is not clear to me) I dont get expected results with Hi_credit = 73 and lo_credit = 750. Note: by setting default which is 0x3FFFFFFF I observe correct bandwidth at switch output which is 50Mbps

LMT101ENMFWD-ACD LCD 10.1'' HDMI with i.MX 8M Plus EVK Board Hi,  i am using LMT101ENMFWD-ACD LCD 10.1" with the i.MX 8M Plus EVK Board through HDMI connection.  i have flashed the i.MX 8M Plus EVK with LF_v6.12.34-2.1.0_images_IMX8MPEVK.zip image When the board boots up, the default resolution causes the content on the display to be squished. i tried to update the weston.ini file but no impact happens.  could you please tell me step by step how to update the resolution? thanks Eslam Graphics & Display i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: LMT101ENMFWD-ACD LCD 10.1'' HDMI with i.MX 8M Plus EVK Board Hello, You may refer to the following community document if you are using HDMI port it is pretty straight forward: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-to-change-the-HDMI-pixel-clock-and-change-the-panel/ta-p/2131344 Hope this helps, Best regards/Saludos, Aldo.

iMX95 Arm Mali-G310 GPUベンチマーク 皆さんこんにちは 何か見逃しているのかもしれませんが、Linux Arm 用のバージョンがないのに、なぜ NXP は GFXBench と Antutu からの GPU ベンチマークの結果を表示しているのでしょうか? ドキュメントE1R05_Prior_NXP_2024.pdfを参照しています 私の理解では、Arm Mali-G310 は、Arm アーキテクチャでのみ利用可能な設計であるSO、これら 2 つは一致しません。 誰か説明してもらえますか? ありがとう、 デビッド Re: iMX95 Arm Mali-G310 GPU benchmarking こんにちは@Cerviik GFXBench は Linux 用です。 AntutuはAndroid専用です。 よろしくお願いします。 ダニエル

how to write data flash (S32K328) I want to store some boot information in the dataflash area when designing the boot. Is there any related routine documentation that can be used as a reference? Currently, I have used AI to generate some operation methods (registers, c40uip), but none of them have been successful, and I don't know how to find the cause。 Re: how to write data flash (S32K328) Thank you, but I encountered a problem when using C40_SP for flash operations: the boot is at core0 0x00400000, and when I perform a write operation on the address of core0 (0x00440000), it enters a hard fault. I confirm that the boot area code is only before 0x00440000 and there is no out of bounds issue, but operating on core1 area (0x00600000) with the same code is not a problem. What is the reason for this. My rewrote code is as follow /************ erase code******************/ if (C40_IP_STATUS_SECTOR_PROTECTED == C40_Ip_GetLock(sector_number)) { printf("RAM: Sector %d is protected, clearing lock\r\n", sector_number); C40_Ip_ClearLock(sector_number, 0); } C40_Ip_MainInterfaceSectorErase(sector_number, 0);do { t_ReturnValue = C40_Ip_MainInterfaceSectorEraseStatus(); } while (C40_IP_STATUS_BUSY == t_ReturnValue); /************ write code******************/ C40_Ip_MainInterfaceWrite(addr, length, data, 0); do { t_ReturnValue = C40_Ip_MainInterfaceWriteStatus(); } while (C40_IP_STATUS_BUSY == t_ReturnValue); Re: how to write data flash (S32K328) There are RTD drivers, specifically Mem_43_INFLS (RTD 6.0.0): https://www.nxp.com/design/design-center/software/automotive-software-and-tools/real-time-drivers-rtd:AUTOMOTIVE-RTD Pay attention to example  C40_Ip_Example_S32K358 /** * @brief Main function of the example * @details Initializes IP C40 driver and erase, write, read internal flash memory */

OpenSSL 3 and black key? Hi, We are interested in being able to use CAAM to support OpenSSL with black keys for signing operations. OpenSSL 3 recommends using a new interface called "Provider". It appears there's no ready CAAM "Provider" implementation without using something like OP-TEE. Could someone confirm or deny this? If there's no ready implementation, any suggestions, is there any official support integrating black key sign/verify operations to mbedTLS, OpenSSH, OpenGPG, etc..? Thanks, Christian i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Security Re: OpenSSL 3 and black key? Have also checked with internal security team, no positive answer without OPTEE. Regards Harvey Re: OpenSSL 3 and black key? If possible we'd like to _not_ have to use OPTEE. Do you know if that's possible? Regard, Christian Re: OpenSSL 3 and black key? Hi, Hope that the section <10.4.8 OpenSSL TLS offload to OP-TEE PKCS#11 via pkcs11-provider> of UG10163.pdf be helpful. Regards Harvey

Is there a simple way to update the DTB and kernel image on an eMMC? During development, we need to frequently update the DTB and kernel image. Using an SD card is very convenient; a card reader can read and write the DTB and kernel image on a FAT partition. However, using an eMMC is very inconvenient. Is there a simpler method? Re: Is there a simple way to update the DTB and kernel image on an eMMC? Here is the better way, I believe. How to upgrade Linux Kernel and dtb on eMMC without UUU  Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, To enter on fastboot mode you need: 1. Turn on the board and stop boot flow pressing any key to enter in U-boot. 2. In U-boot enter next command: fastboot 0 Use the next command to send the file with UUU: uuu -v -b fat_write mmc 0:1 Example: uuu -v -b fat_write hello_world.elf mmc 0:1 hello_world.elf Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Use fastboot, as you mentioned before. Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, What are you referring for? Upload DTB with fastboot or flash eMMC from SD card or both? Best regards. Re: Is there a simple way to update the DTB and kernel image on an eMMC? How to do this specifically? Is there any guidance document? Thanks. Re: Is there a simple way to update the DTB and kernel image on an eMMC? Hello, You can update the DTB file configuring your board in fastboot from U-boot and transfer the file with UUU. Regarding flash the image I suggest you re-flash with UUU or try to flash the eMMC from SD card but I think this process is more complicated.  Best regards.

Load initial bootloader thought CAN interface? Can the initial bootloader file be loaded through the CAN interface on a brand new MCU, thus eliminating the need for a JTAG connector? Re: Load initial bootloader thought CAN interface? Hello @klv222  Please describe your question in more detail. Which chip are you referring to? Which bootloader file?  Thank you. BR Alice Re: Load initial bootloader thought CAN interface? Yes, it is possible in some MCU families to load the initial bootloader through the CAN interface on a brand-new MCU, potentially eliminating the need for a JTAG connector, but this depends entirely on the MCU’s built-in features. Many modern microcontrollers ship from the factory with a ROM-resident bootloader that supports communication over interfaces such as CAN, UART, USB, or SPI. If CAN is supported in this factory bootloader, the MCU can be programmed directly via the CAN bus on first power-up, provided the correct boot mode pins or configuration are set. However, if the MCU does not include a CAN-capable ROM bootloader, JTAG or SWD is still required at least once to install an initial bootloader. Additionally, JTAG remains valuable for low-level debugging, recovery from misconfiguration, and unbricking devices, even if it is not required for normal production programming.   change healthcare

Patch suggestion for linux-imx busfreq-imx8mq driver Hi NXP, Please consider the patch below for linux-imx. I tested this on branch lf-6.6.52-2.2.0 (imx8mm/imx8mn hardware), but it also applies on older branches. When switching DDR frequency, the busfreq driver will always make a print to the kernel log buffer via printk(). In a use case where the DDR frequency switches often, this leads to spamming the log buffer. We encountered this exact case, and all other messages from the dmesg buffer are pushed out as a consequence. Using pr_debug() will depend on the definition of DEBUG and will not spam dmesg by default. diff --git a/drivers/soc/imx/busfreq-imx8mq.c b/drivers/soc/imx/busfreq-imx8mq.c index 5e36962285ef..9914d19183be 100644 --- a/drivers/soc/imx/busfreq-imx8mq.c +++ b/drivers/soc/imx/busfreq-imx8mq.c @@ -205,9 +205,9 @@ static void reduce_bus_freq(void) } if (audio_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to audio bus mode\n"); + pr_debug("ddrc freq set to audio bus mode\n"); if (low_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to low bus mode\n"); + pr_debug("ddrc freq set to low bus mode\n"); } static void reduce_bus_freq_handler(struct work_struct *work) @@ -296,7 +296,7 @@ static int set_high_bus_freq(int high_bus_freq) cur_bus_freq_mode = BUS_FREQ_HIGH; if (high_bus_freq_mode) - printk(KERN_DEBUG "ddrc freq set to high bus mode\n"); + pr_debug("ddrc freq set to high bus mode\n"); return 0; } i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Patch suggestion for linux-imx busfreq-imx8mq driver Hi, Thank you for your interest in NXP Semiconductor products, Thanks for the suggestion, I will pass it down to the software team. Regards

Eth_43_GMAC on S32K344 Hello, I use S32K3-T-BOX, MCAL RTD 2.0.0 22_03, Eth_InternalLoopback example and PE micro multilink. I added configuration for all necessary pins according to SCH-50735.pdf and disable Loopback mode. I also added a loop with a delay for cyclic Eth_transmit and flashing the U37 LED to check the run. After Debug_FLASH everything works as expected and the T-BOX sends ethernet message cyclically, the problem occurs after turning the T-BOX off and on. LED U37 flashes to indicate software is running, but the Ethernet message is not being sent. It occurs to me that the multilink is doing some initialization that doesn't happen after the device is restarted, but I don't know how to solve this problem. If anyone has a solution, I would appreciate any advice. Regards won0020 Re: Eth_43_GMAC on S32K344 Thank you very much, osif delay solved my problem. Re: Eth_43_GMAC on S32K344 Hi @won0020 , have you programmed both FLASHs - S32k3 and Flash attached to SJA1110? You also start with the lwip demo - please refer to S32K3 Automotive Telematics Box (T-Box) lwIP Example Guide Training Presentation - refer to slide 15 where small workarounds are described. Best regards, Pavel Re: Eth_43_GMAC on S32K344 Hi, S1 is off, LED U36 also flashes green. Re: Eth_43_GMAC on S32K344 Hi @won0020 , Jumper S1 needs to be set to OFF to enable NVM boot for SJA1110. Best regards, Pavel

[LPSPI] 周辺FIFOによる複素転送 コミュニティの皆さん、こんにちは。 皆さんがお元気でいらっしゃることを願っています。ペリフェラルのFIFO機能を利用したSPI通信の管理について、支援を求めています。 バックグラウンド： 現在、#i.MX-RT1050##とADCデバイス間のSPI通信を含むプロジェクトに取り組んでいます。データ転送プロセスを合理化し、効率を高めるために、ペリフェラルコマンド/データFIFOを使用して実装することを検討しています。ただし、この機能をプロジェクトに統合するには、いくつかの課題に直面しています。 サポートのリクエスト: ペリフェラルコマンド/データFIFOを使用して、LPSPI_MasterTransferNonBlockingや他の関数を1回呼び出すだけで複数のCSサイクルとの通信を管理しながら、SPI通信を効果的に管理する方法についてのガイダンス、洞察、またはリソースを提供できる方がいると幸いです。 タイムダイアグラムリファレンス: 参考までに、SPI通信プロセスを示すタイムダイアグラムの画像を添付しました。 あなたの時間と援助のために事前に感謝します。皆様からのご回答とご意見をお待ちしております。 よろしくお願いいたします。 i.MXRT 105倍

How to set Lpi2c speed of S32K312 in RTD5.0? Hi NXP: we're developing project with S32K312 and getting I2C speed issue. I set Lpi2c parameters by reference manual and getting correct speed 1Mbit/s by GUI(Lpi2c_setting.png),but I measured I2C speed about clock waveform(LA_I2C_waveform.png) about 2.667Mhz. Is it correct? thanks. attachment: I2C_setting_from_reference_manual.png Lpi2c_setting.png clock_ip_referencepoints.png LA_I2C_waveform.png current environment: MCU:S32K312/100pin S32DS Product:3.5.0.202207261815 RTD S32KXX:RTD5.0.0.202407261948 BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Yes, I'm afraid you shouldn't select LPI2C_FASTPLUS_MODE with 1 Mbit/s because the reference manual says so. Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I modified I2C parameters from fast+ mode to fast mode in master mode, and GUI show 400000(Baud rate), but I measured speed about 385Khz. it looks like not accurate about GUI value and LA value, thanks. attachment: 20250306-2-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: just now, I saw reference manual as you posted information(LPI2C master mode operation supports up to fast Mode = 400KHz), so S32K312 only supports fast mode in master mode(Up to 400Khz). if I want to adjust more than 400Khz, it is invaild for usage, Is it correct? thanks. BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I always use I2C master mode as LPI2C_FASTPLUS_MODE which support 1 Mbit/s.however, I created simple project by GPIO and I2C function and set I2C parameters as current project, and also tested I2C speed is about 888~914Khz on our PCB board. now you can change MCU package of attachment from 100pin to 172pin for your EVB testing,thanks. attachment: 20250306-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Sorry for the inconvenience. It would be best if S32 Design Studio would warn you when you select master mode but exceed 400 kbps data rate. S32K3XXRM mentioned: •LPI2C slave mode operation supports up to high speed mode = 3.4MHz (3.4 Mbps data rate; effective data rate reduces according to I2C protocol). •LPI2C master mode operation supports up to fast Mode = 400KHz (400 kbps data rate; effective data rate reduces according to I2C protocol). Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I tried to change Clock_Ip_ReferencePoints from custom(8Mhz) to AIPS_SLOW_CLK(30Mhz), and also changes I2C timing that it calculated I2C baud rate 1000000. but I measured waveform about 864KHz. now I confuse about calculating result of Lpi2c GUI. please help us, thanks. attachment: clock_ip_referencepoints2.png LA_I2C_waveform2.png Lpi2c_setting2.png BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Nelson, The LPI2C_CLK comes from AIPS_SLOW_CLK. So would you please configure AIPS_SLOW_CLK in clock_ip_referencepoints.png? Otherwise, the S32 Configuration Tool may use the wrong frequency (80MHz CUSTOM) for calculation. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

L6.6.3 iw612 load txpower_cfg fail Hi I am trying add txpwrlimit_cfg while loading WiFi driver, but got the following error, same settings/files in L6.1.55 was fine. And without set txpwrlimit_cfg parameter, WiFi driver load succesfully and working fine. root@imx93:~# modprobe moal mod_para=nxp/wifi_mod_para.conf [ 17.532015] mlan: loading out-of-tree module taints kernel. [ 17.578136] wlan: Loading MWLAN driver [ 17.585593] wlan: Register to Bus Driver... [ 17.600828] vendor=0x0471 device=0x0205 class=0 function=1 [ 17.606578] Attach moal handle ops, card interface type: 0x109 [ 17.612532] rps set to 0 from module param [ 17.617918] SDIW612: init module param from usr cfg [ 17.623162] card_type: SDIW612, config block: 0 [ 17.627774] cfg80211_wext=0xf [ 17.630789] max_vir_bss=1 [ 17.633448] cal_data_cfg=none [ 17.636416] ps_mode = 1 [ 17.641499] auto_ds = 1 [ 17.643983] host_mlme=enable [ 17.649504] fw_name=nxp/sduart_nw61x_v1.bin.se [ 17.654084] txpwrlimit_cfg=nxp/txpower_QSM_US.bin [ 17.658916] SDIO: max_segs=128 max_seg_size=65535 [ 17.663765] rx_work=1 cpu_num=2 [ 17.666995] Enable moal_recv_amsdu_packet [ 17.671074] Attach mlan adapter operations.card_type is 0x109. [ 17.682854] wlan: Enable TX SG mode [ 17.686391] wlan: Enable RX SG mode [ 17.693610] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 18.046530] Wlan: FW download over, firmwarelen=1004248 downloaded 916048 [ 18.453634] WLAN FW is active [ 18.456624] on_time is 18307253173 [ 18.460061] Download txpwrlimit_cfg=nxp/txpower_US.bin [ 18.487779] VDLL image: len=88200 [ 18.519055] fw_cap_info=0x487cff03, dev_cap_mask=0xffffffff [ 18.524681] uuid: 521d887a0a925da4a1fe6a6f39966212 [ 18.529497] max_p2p_conn = 8, max_sta_conn = 16 [ 18.559956] Register NXP 802.11 Adapter mlan0 [ 18.566109] wlan: uap%d set max_mtu 2000 [ 18.574646] Register NXP 802.11 Adapter uap0 [ 18.608521] Register NXP 802.11 Adapter wfd0 [ 18.619407] wlan: version = SDIW612---18.99.2.p66.17-MM6X18437.p3-GPL-(FP92) [ 18.636305] wlan: Register to Bus Driver Done [ 18.645522] wlan: Driver loaded successfully [ 21.266693] FW trigger fw dump [ 21.269817] =====FW trigger dump==== [ 21.273726] ==== Start Receive FW dump event ==== [ 21.278586] === START DRIVER INFO DUMP=== [ 21.278825] FW in debug mode (0xe3) [ 21.394221] Drv info total bytes = 336781 (0x5238d) [ 21.399129] === DRIVER INFO DUMP END=== [ 22.215633] ==== FW DUMP END: 1336880 bytes ==== [ 22.224118] fw dump total length is 1336892 [ 22.228385] Start to process hanging [ 22.232045] Cancel all pending cmd and txrx queue [ 22.236901] WIFI auto_fw_reload: fw_reload=1 [ 22.241239] ========START IN-BAND RESET=========== [ 22.246180] woal_reset_intf: get bss info failed [ 22.250927] Cancel all pending cmd and txrx queue [ 22.390250] woal_close: woal_disconnect failed [ 22.662577] FW wake up [ 22.666271] SDIO Trigger FW In-band Reset success [ 22.666304] SDIO: max_segs=128 max_seg_size=65535 [ 22.677190] rx_work=1 cpu_num=2 [ 22.681162] Enable moal_recv_amsdu_packet [ 22.686153] Attach mlan adapter operations.card_type is 0x109. [ 22.693545] wlan: Enable TX SG mode [ 22.697059] wlan: Enable RX SG mode [ 22.701957] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 23.067701] Wlan: FW download over, firmwarelen=1004248 downloaded 916048 [ 29.077402] Fail to poll firmware status: firmwarestat=0x0 [ 29.082928] FW failed to be active in time! [ 29.087135] wlan_dnld_fw fail ret=0xffffffff [ 29.091440] WLAN: Fail download FW with nowwait: 0 [ 29.096577] SDIO Func0 (0x0-0x9): 43 03 02 02 03 00 00 02 03 00 [ 29.103437] SDIO Func1 (0x10-0x17): 00 00 00 00 00 00 00 00 [ 29.109526] SDIO Func1: (0x8) 00 (0x58) 00 (0x5c) 0d (0x5d) 00 (0x60) 01 (0x61) 00 (0x62) 00 (0x64) 10 (0x65) 00 (0x66) 00 (0x68) 00 (0x69) 00 (0x6a) 00 [ 29.123829] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.235469] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.245502] woal_request_fw failed [ 29.248901] Firmware Init Failed [ 29.252479] SDIO Func0 (0x0-0x9): 43 03 02 02 03 00 00 02 03 00 [ 29.258736] SDIO Func1 (0x10-0x17): 00 00 00 00 00 00 00 00 [ 29.264745] SDIO Func1: (0x8) 00 (0x58) 00 (0x5c) 0d (0x5d) 00 (0x60) 01 (0x61) 00 (0x62) 00 (0x64) 10 (0x65) 00 (0x66) 00 (0x68) 00 (0x69) 00 (0x6a) 00 [ 29.279066] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.389834] SDIO Func1 (0xe8-0xff): 00 00 00 00 50 fa 0d 00 24 14 70 c8 ab 37 80 00 00 00 00 00 01 00 00 00 [ 29.489860] Free module params [ 29.492947] ========END IN-BAND RESET=========== OS LINUX Product: WiFi IW6XX Protocol: Wi-Fi Re: L6.6.3 iw612 load txpower_cfg fail Hello @shaun_wu  Thanks, after force change FW and driver to 6.6.23 fixed this issue. root@quilt-imx93-qsm:~# modprobe moal mod_para=nxp/wifi_mod_para_qsm.conf [ 22.253697] mlan: loading out-of-tree module taints kernel. [ 22.317581] wlan: Loading MWLAN driver [ 22.326493] wlan: Register to Bus Driver... [ 22.338429] vendor=0x0471 device=0x0205 class=0 function=1 [ 22.344079] Attach moal handle ops, card interface type: 0x109 [ 22.349968] rps set to 0 from module param [ 22.355413] SDIW612: init module param from usr cfg [ 22.360371] card_type: SDIW612, config block: 0 [ 22.364935] cfg80211_wext=0xf [ 22.367927] max_vir_bss=1 [ 22.370569] cal_data_cfg=none [ 22.373554] ps_mode = 1 [ 22.376013] auto_ds = 1 [ 22.378482] host_mlme=enable [ 22.381390] fw_name=nxp/sduart_nw61x_v1.bin.se [ 22.385857] txpwrlimit_cfg=nxp/txpower_US.bin [ 22.390616] SDIO: max_segs=128 max_seg_size=65535 [ 22.395338] rx_work=1 cpu_num=2 [ 22.398522] Enable moal_recv_amsdu_packet [ 22.402675] Attach mlan adapter operations.card_type is 0x109. [ 22.414743] wlan: Enable TX SG mode [ 22.418371] wlan: Enable RX SG mode [ 22.426370] Request firmware: nxp/sduart_nw61x_v1.bin.se [ 22.778840] Wlan: FW download over, firmwarelen=1038668 downloaded 936668 [ 23.181312] WLAN FW is active [ 23.184329] on_time is 22921111967 [ 23.187759] Download txpwrlimit_cfg=nxp/txpower_US.bin [ 23.221031] VDLL image: len=102000 [ 23.265041] fw_cap_info=0x487cff03, dev_cap_mask=0xffffffff [ 23.270673] uuid: 521d887a0a925da4a1fe6a6f39966212 [ 23.275483] max_p2p_conn = 8, max_sta_conn = 16 [ 23.410178] Register NXP 802.11 Adapter mlan0 [ 23.414909] wlan: uap%d set max_mtu 2000 [ 23.424961] Register NXP 802.11 Adapter uap0 [ 23.541433] Register NXP 802.11 Adapter wfd0 [ 23.547371] wlan: version = SDIW612---18.99.3.p10.1-MM6X18437.p21-GPL-(FP92) [ 23.584774] wlan: Register to Bus Driver Done [ 23.591295] wlan: Driver loaded successfully Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you try 6.6.23 on this problem? We have a similar fix on 6.6.23 release. Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  We are able to reproduce your issue, and we are internally tracking this problem. I'll update to you when we get progress. Thanks! Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hi @shaun_wu  Attached our Tx power file, system can't allow upload binary file. Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you share txpower_US.bin you used? Best Rergards Shaun Re: L6.6.3 iw612 load txpower_cfg fail It's only one place could to set tx power in wifi_mod_para.conf, and I upgrade nxp-wlan-sdk in L6.1.55 same initial command and txpower_US.bin without any problem. Re: L6.6.3 iw612 load txpower_cfg fail Platform is i.MX 9302A1 Base on imx-6.6.3-1.0.0 NXP-wlan-sdk SRCREV=:a84df583155bad2a396a937056805550bdf655ab" wlan: version = SDIW612---18.99.2.p66.17-MM6X18423.p6-GPL-(FP92) And wifi_mod_para.conf setting was. SDIW612 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 fw_name=nxp/sduart_nw61x_v1.bin.se txpwrlimit_cfg=nxp/txpower_US.bin } Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  The problem might be tx_pwr config already downloaded, you download again then error reported. You could try cut off power supply then reboot the system. Best Regards Shaun Re: L6.6.3 iw612 load txpower_cfg fail Hello @Chihyu_Lin  Could you sahre the version you get these error report? Best Regards Shaun

S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello I used S32K344 to test the RTC wake-up function. When setting the RTC timing time, I referred to the conversion method in the sample program as shown below: However, the time was deviated during the actual test. What is the reason? BestRegards, Simon Re: S32K344-How to convert the actual time to the RTCVAL value of the RTC Hello Simon, The internal SIRC is not precise: To get precise RTC, use the external SXOSC with 32.768Khz crystal. Regards, Daniel

Installing new SDK causes automation project migration I have S32 DS 3.5 and S32K344 micro. It was originally set with SDK/RTD V2.0.0 It became necessary to add SDK 4.0.0, so that one project would migrate to 4.0.0 and another project stays at 2.0.0 SDK 4.0.0 gets installed properly and both SDKs appear under project settings. I was expecting that by attaching/detaching SDK I can control which SDK current project would use. However those "attached/detached" check-boxes seems to have no effect. Regardless of that all projects would use 4.0.0 and it is was not possible to keep one project with 2.0.0 Is there a way to avoid that? Re: Installing new SDK causes automation project migration That works, thank you Re: Installing new SDK causes automation project migration Hi @sstelmak  S32DS 3.5 can keep one RTD version only (plus additional extensions packages/stacks). The solution is to install more S32DS instances. Just use different folder name of S32DS like: c:\NXP\S32DS.3.5_RTD_200\ c:\NXP\S32DS.3.5_RTD_400\ And install corresponding RTD package to those instances. Regards, Lukas

iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi, We have a customer is trying to build the smart-lock application for SLN-VIZN3D-IOTDG board. They followed the instructions in the reference manual:  SLN-VIZN3D-IOT SW Developer Guide (nxp.com) When building the smart_lock main application, they get the following errors: What is the resolutions for the above errors, Here are some old tickets related to same issue: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31: followup - NXP Community Re: RT1064: How to solve gcc linker error (.ARM.exidx+0x0): relocation truncated to fit: R_ARM_PREL31 - NXP Community Thanks. Ayman Sydhom Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi Kerry, The customer confirmed that the app builds fine after downgraded the MCUXpresso. Thanks. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   You are welcome!   I already test both two IDE versions, so, I am sure of this solution.    Yes, after your end customer also make it works, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, kerry Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Thanks Kerry. Will communicate the resolution to our customer and let you know if this solved the issue or not. Regards. Ayman Re: iMXRT117x: Linking errors during build smart_lock app for SLN-VIZN3D-IOTDG board Hi @asydhom ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. I know your failed issues reason, your used IDE version is high, as I also test it on my side, my MCUXpresso IDE is the v11.9.0, then same build result to you.   So, I download the older MCUXPresso IDE Version to : V11.4.1, as the get start also mentioned: You can download it from this linker: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE Download the previous version: Then, you need to download the SLN-VIZN3D-IOT SDK https://mcuxpresso.nxp.com/en/builder?hw=SLN-VIZN3D-IOT You need to add it to the MCUXPresso IDE  Now, build your project again, you will find it is OK to use: Please try my method on your side. If you still have question about it, please kindly let me know. If your question is solved, please help me to mark the correct answer, just to close this case, thanks. Any new issues, welcome to create the new case. Best Regards, Kerry

L6.6, sn65dsi83 Error: I'm trying to make sn65dsi84 dsi2lvds bridge working with Linux kernel 6.6.52 (Yocto scartgap). After fixing problems with attaching mipi-dsi to SN65DSI83 driver: IMX8MM-sn65dsi83-yocto-scarthgap-mipi-dsi-is-not-initialized  and correcting LVDS timing parameters in DT: Error-Cannot-find-any-crtc-or-sizes - facing another problem: seems that MIPI-DSI is not sending data: SN65DSI83driver cannot lock PLL because it has DSI source clock. [ 2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110 my devicetree is: /dts-v1/; #include "imx8mm.dtsi" / { panel: panel10inch { width-mm = <210>; height-mm = <157>; compatible = "panel-lvds"; backlight = <&bl_lcd>; data-mapping = "vesa-24"; status = "okay"; enable-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; panel-timing { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; /* */ hfront-porch = <40>; hsync-len = <60>; hback-porch = <220>; /* */ vfront-porch = <7>; vsync-len = <10>; vback-porch = <21>; /* */ vsync-active = <0>; hsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; panel_in: endpoint { remote-endpoint = <&bridge_out>; }; }; }; }; }; &i2c1 { dsi_lvds_bridge: sn65dsi84@2c { compatible = "ti,sn65dsi83"; reg = <0x2c>; enable-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dsi_bridge>; vcc-supply = <&reg_1V8>; status = "okay"; of-depends-on = <&panel>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; bridge_in: endpoint { remote-endpoint = <&mipi_dsi_out>; data-lanes = <1 2 3 4>; }; }; port@2 { reg = <2>; bridge_out: endpoint { remote-endpoint = <&panel_in>; }; }; }; }; }; &lcdif { status = "okay"; }; &mipi_dsi { status = "okay"; port@1 { mipi_dsi_out: endpoint { remote-endpoint = <&bridge_in>; data-lanes = <1 2 3 4>; /*lane-polarities = <1 0 0 0 0>;*/ attach-bridge; }; }; }; bootlog is attached. Re: L6.6, sn65dsi83 Error: Found strange thing: [    2.946302] sn65dsi83 0-002c: failed to lock PLL, ret=-110 [    2.948106] imx_sec_dsim_drv 32e10000.mipi_dsi: imx_sec_dsim_encoder_atomic_enable: Enter [    2.951027] sn65dsi83 0-002c: sn65dsi83_atomic_enable: Enter [    2.956980] sn65dsi83 0-002c: Unexpected link status 0x01 The sn65dsi83 probe function pries to lock PLL from MIPI-DSI before imx_sec_dsim_encoder_atomic_enable() function ensbles it. Moved piece of code that sets PLL to sn65dsi83_atomic_enable() function. Works now!

Port is not opening for enable communication using RPMSGs on i.MX93 Hi all,  Hope you are doing well. I am facing issue while trying to open the port of RPMSG by enabling tty driver. Please find below basic info. -> SDK: SDK_24_12_00_MCIMX93-EVK -> Project: rpmsg_lite_str_echo_rtos -> Development kit: Digi ConnectCore 91/93  The Procedure I followed: 1. boot up the Yocto Linux result: [ 0.022125] imx rpmsg driver is registered. 2. Compile the rpmsg_lite_str_echo_rtos in ubuntu and created .elf file 3. Transfer the elf file into /dev/firmware folder of i.MX93 4. enable the tty driver using modprobe imx_rpmsg_tty command on i.MX93 board 5. Load the firmware and run it using RemoteProc framework 6. I am getting data on LPUART4 as per below result on serial port: RPMSG String Echo FreeRTOS RTOS API Demo... 7. But it stuck on "rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK);" function Also, I am not getting the ttyRPMSG* serial port on /dev/ folder. Does anybody know how to solve it? and what are potential causes of this problem? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano i.MX2x i.MX50 i.MX51 i.MX53 i.MX6 All i.MX6DL i.MX6Dual i.MX6DualPlus | 6QuadPlus i.MX6Quad i.MX6S i.MX6SL i.MX6SoloX i.MX6UL i.MX7Dual i.MX7Solo i.MX7ULP i.MX8ULP i.MXRT Linux Yocto Project Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi @Zhiming_Liu ,  Thanks for the prompt response. I have few more questions about SDK: 1. When will the 25.06 SDK release? 2. How are the SDK versioning numbers spread out from 2.16 to 15.06 to 25.06? I want to understand this to select the SDK. Thanks Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, The SDK hub for 24.12 or 25.03 miss some configuration about rpmsg which cause the SDK generated from SDK hub can't use rpmsg feature. We will fix this issue in SDK 15.06 and please use SDK2.16 before SDK 25.06 release. Best Regards, Zhiming Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hey @Zhiming_Liu  I am able to download the SDK now. I compiled and executed the rpmsg_lite_str_echo_rtos_imxcm33 example and it was able to create the ttyRPMSG30 port and able to send test string from master (A55) to slave (M33) processor cores. Additionally, I tried to compare both the SDKs (2.16 and 24.12) to get to know if I am missing anything but unfortunately was not able to find anything as of now. I want to run RPMSG in SDK 24.12 as my project is based on that, so could you please provide me any information on how can I achieve that? I asked this in my first post but so far did not get any info on this so I will appreciate it. I also wanted to know why rpmsg example is not working on 24.12 or 25.03 either and when it would be fixed? Thanks. Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi  Thanks for reply. I couldn't be able to download the SDK version 2.16 or 2.15 as well. Please see the problem in the image. Now do you have other option to download it OR if you have 2.16 Version of SDK, could you provide me that along with its example directories? Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, You can select version here: Best Regards, Zhiming Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi  I am using "Dashboard | MCUXpresso SDK Builder" sdk and aould you tell me, how it differs with "https://github.com/nxp-mcuxpresso/mcux-sdk" sdk? The board I am using it is Digi ConnectCore 91/93. Also, I followed guideline from "https://docs.digi.com/resources/documentation/digidocs/embedded/dey/4.0/cc93/yocto-develop-cortex-apps_t_93.html" . Other than these, if you have any queries, please let me know. Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hi Zhiming_Liu, Thanks for reply. Can you tell me how to download the lower version of SDK as you suggested SDK2.16? Although, I tried to download it, but I couldn't find any option to change the SDK version from MCUXpresso SDK Dashboard website. Could you guide me to this? Re: Port is not opening for enable communication using RPMSGs on i.MX93 Hello, Please use SDK2.16 which can work. Best Regards, Zhiming

S32K358 hi sir： S32K358: How to do core 0 after the initialization clock is complete, then start core 2. I find that "MC_ME" has no kernel 2 related register. Re: S32K358 Hi nxpuser007: I already can debug core0 and core2 in the same time by s32ds, debug mode is OK. When I power off and power on the system, only core0 bootup and run, core2 don't do anything, do you have any experience about this problem? Thanks Br, BillWen Re: S32K358 When you step the code, where does it fail exactly? Re: S32K358 Why does starting kernel 2 and then initializing IPCF go to hardfault？ Re: S32K358 Hi @nxpuser007  take a look at this thread, there's an example how to start second core by software: https://community.nxp.com/t5/S32K/S32K324-seperate-core-code/td-p/1789569 Regards, Lukas

Modifying the ld file results in a compilation error due to overlapping sections Hi, developers, I encountered a compilation error with GCC when configuring DTCM as SRAM using S32K312. I haven't made any progress in finding the cause of the error. I referred to the community topic discussion, "How to modify the LD file to use ITCM and DTCM content," but following the manual and the discussion's LD file configuration led to a compilation error. Can anyone help me resolve this issue? I tried various versions of GCC, such as GCC9.2.0, GCC 10.2.0, GCC 10.3.1, GCC12.2.0。But all resulted in the same error. IDE: vscode cmake version: 3.28.1 GCC12.2.0 Erroe ScreenshootGCC12.2.0 Erroe Screenshoot GCC 10.2.0 Error ScreenShotGCC 10.2.0 Error ScreenShot Reference link for the topic discussion   https://community.nxp.com/t5/S32K/How-to-use-DTCM-1-memory-in-S32K314-controllers/m-p/1663024 https://community.nxp.com/t5/S32K/DTCM-ITCM-example/m-p/1606827#M21008 https://community.nxp.com/t5/S32K/Regarding-the-RAM-location-for-the-s32k312/m-p/1876369 https://community.nxp.com/t5/S32K/How-to-solve-the-RAM-resource-is-not-enough-on-S32K312/m-p/1538940#M18373 https://community.nxp.com/t5/i-MX-RT/uTasker-Compile-Error-in-MCUXpresso/m-p/1535822 @danielmartynek  @lukaszadrapa @davidtosenovjan Can you help me with this issue? Thank you. Regards, Ags  Re: Modifying the ld file results in a compilation error due to overlapping sections hi, @lukaszadrapa   thaks your response. i compare the link file you provided.  there wasn't  much difference.   I searched for a solution and found that the issue lies in the LD file configuration. The attribute "os_globle" was declared in the program but not configured in the LD file, leading to the error. In the LD.pdf documentation on overlapping, I identified this problem. Re: Modifying the ld file results in a compilation error due to overlapping sections Hi @DennyZhang  attached is linker file from RTD 4.0.0 which already contains definitions for DTCM. It's working on my side. Regards, Lukas 回复： Modifying the ld file results in a compilation error due to overlapping sections This discussion has a similar problem Re: How can I put my callback function into ITCM memory ? S32K344 - NXP Community

i.MX8 ULP Solo Emulation We want to evaluate whether the performance of i.MX8 ULP Solo/Single Core is acceptable to run latest NXP Android 14 release. Is there a u-boot or adb/debug console commands that we can run in real time to enable single core mode in i.MX8ULP Evaluation Kit (which has dual core)? Re: i.MX8 ULP Solo Emulation This save my time. Thanks for your info. Re: i.MX8 ULP Solo Emulation Thanks. It works!. evk_8ulp:/ $ cat /proc/cpuinfo processor : 0 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 evk_8ulp:/ Re: i.MX8 ULP Solo Emulation please try "setenv append_bootargs maxcpus=1 " Re: i.MX8 ULP Solo Emulation On Android 14, Here is the uboot printenv => printenv arch=arm baudrate=115200 board=imx8ulp_evk board_name=imx8ulp_evk bootcmd=boota mmc0 bootdelay=2 cpu=armv8 emmc_dev=0 ethaddr=00:04:9f:08:73:f6 ethprime=FEC fastboot_dev=mmc0 fdt_high=0xffffffffffffffff fdtcontroladdr=a3de8210 initrd_high=0xffffffffffffffff loadaddr=0x80400000 sd_dev=2 sec_boot=yes serial#=5fe72827b1363228 soc=imx8ulp soc_type=imx8ulp splashimage=0x90000000 splashpos=m,m vendor=freescale Environment size: 409/8188 bytes I try to "setenv maxcpus 1", and the android still boot up with 2 CPUs 130|evk_8ulp:/ $ cat /proc/cpuinfo processor : 0 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 processor : 1 BogoMIPS : 2.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd04 CPU revision : 0 The way that android set kernel parameters seems different from that of Linux. Please advise. Re: i.MX8 ULP Solo Emulation It should be the same as u-boot also is the bootloader in Android 14. Re: i.MX8 ULP Solo Emulation Thanks. That's for Linux. Does Android 14 has similar setting? Re: i.MX8 ULP Solo Emulation There is kernel parameter "maxcpus" which is maximum number of processors that kernel should use. For more information, you could refer to the Table 11 in the Release Notes below. i.MX Linux Release Notes (nxp.com)