S32G-VNP-RDB32 (SJA1110) 交换机中的寄存器访问 你好， 我想把值写进寄存器你能不能给我一个完整的地址来 读写地址 名称访问RESET描述 8Ch DYN_BE_LKP_ ENTRY0 R/W 0h (ffffFFe h) 8ch 之前的基址是什么？比如它会有 0x3fc0008c 所以在这个动态入口表中我们会有完整的地址你能不能给我 8Ch DYN_BE_LKP_ ENTRY0 R/W 0h (fffffF eh) 90h DYN_BE_LKP_ ENTRY1 R/W 0h 94h DYN_BE_LKP_ ENTRY2 R/W 0h 98h DYN_BE_LKP_ R/W 0h 98h DYN_BE_LKP_ ENTRY3 R/W 0h 9Ch DYN_BE_LKP_ ENTRY4 R/W 0h a0h a0h DYN_BE_LKP_ ENTRY5 R/W 0h A4H DYN_BE_LKP _CTRL R/W 0h (ff800000H) 你能不能给我提供在寄存器中配置动态条目的完整地址？ 以及需要在 SJA1110 Switch 中实现此功能的地方 Re: Register Access in S32G-VNP-RDB32 (SJA1110) Switch 你好@Atkinson、 我知道这乍看起来可能并不简单，但实际上这个概念非常简单。 最终的寄存器地址取决于访问方法--是通过 AHB 在内部访问 M7 内核，还是通过 SPI_AP 接口从外部访问。基本地址因接入点而异。 寄存器地址使用 UM11107 表 2 中提供的基地址计算。例如，对于交换机子系统，SPI_AP 访问的基地址为0x00000000 ，AHB 访问的基地址为0xFF000000 。 在这种情况下，通过 AHB 访问寄存器0x8C （DYN_BE_LKP_ENTRY0）时，寄存器会变成0xFF00008C 。 现在，可能会让人感到困惑的地方来了：SDK 驱动程序定义了以下内容： #define SJA1110_L2_ART_LE_ADDR(0x3fc00023) /**< l2ArtLockedEntry 寄存器的地址 *   SWITCH_DRV_Write 例程将地址左移 2 位 (<< 2)，用于内部 (AHB) 访问。对于 SPI 传输（级联开关设置中使用），不应用移位。因此，0x3fc00023 << 2 的结果是0xFF00008C。   我希望通过上面的解释，现在有感知了。   顺祝商祺！ 帕维尔

RPMsg-Lite rpmsg_lite_alloc_tx_buffer ブロック iodsfid2df4d1 こんにちは、 i.MX93 上の Cortex-M33 と Cortex-A55 間の RPMsg-Lite 通信で問題が発生しています。 A55 がサスペンド モードに入ると、M33 側での rpmsg_lite_alloc_tx_buffer() への呼び出しは、正確な状況に応じて無期限にブロックされるか、ハード エラーが発生します。関数 rpmsg_lite_is_link_up() は引き続き true を返すため、この状態が明確に検出されません。 グラフィックスとディスプレイ ハンズオン・トレーニング HW-Open-Source i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus

カスタムM7セカンダリブートローダー i.MX RT1176 こんにちは、現在、m7 と m4 の両方のコア FW は QSPI フラッシュ FlexSPI1 0x30000000 に格納されています。最初に M7 が起動し、次に QPSI から ID のエイリアスにイメージをコピーしてコア M4 を起動します0x20200000。すべて正常に機能しています。 次に、特定の検証に基づいてM7コアを起動し、M7がm4を起動するカスタムブートローダーを追加したいと思います。また、M7 / M4または両方のファームウェアのOTAも処理されます。 標準のセカンダリブートローダーコードはありますか?参考までにシェアしてください。 ありがとうございます

如何恢复 HCS12X 中的应用程序？ 你好 有没有办法在HCS12X系列芯片的引导加载程序运行期间恢复应用程序？ 例子： - 引导加载程序中闪存擦除期间发生意外中断 - 重置后应用程序正常运行 - 假设应用程序已经加载 我似乎无法在 AN4258 中找到代码。 回复：如何在 HCS12X 中恢复应用程序？ 最后好像只有双库方法了。 谢谢

CLRC66301B Power-Down Mode Still Consumes 2 mA Instead of nA Hello NXP Community  I’m using the CLRC66301B NFC reader IC and trying to activate Power-down mode by driving the PDOWN pin high (3.3 V), as specified in the datasheet. However, the current draw remains at 2 mA, while the datasheet indicates it should be between 8 nA and 40 nA in power-down. Setup Details: PDOWN pin: 3.3 V (constant high) VDDs: VDD(TX), VDD(AUX), VDD(MCU) all at 3.3 V Interface: I²C (idle during test) XTAL: 27.12 MHz crystal connected No communication or activity during current measurement Measured current: ~2 mA Questions: 1. Are any register configurations required before asserting PDOWN? 2. Could IRQ, XTAL, IFSEL, or other GPIOs prevent entry into true power-down mode? 3. Does PDOWN require additional timing or sequencing with VDD or reset? Any insights or suggestions would be appreciated. Thanks, Umasankar NFC Controller Solutions Re: CLRC66301B Power-Down Mode Still Consumes 2 mA Instead of nA Hi, When you mention that current consumption is reduced when SDA and SCL are physically disconnected, does it mean that you are removing all connections on this pin (removing both Host MCU and pull-up resistors), or is it that those lines are only disconnected from the Host MCU? Also, could you please describe the method, equipment and test point you are using for the measurement? Regards, Eduardo. Re: CLRC66301B Power-Down Mode Still Consumes 2 mA Instead of nA Dear NXP Team, I conducted power-down current testing using the official CLEV6630ARD board with the CLRC66303B chip. The current reaches ~40 nA only when SDA and SCL are physically disconnected before any I²C communication. If I²C is used even once, current remains above 2 mA, even after asserting PDOWN high. Could you please clarify what should be done with the I²C lines before entering PDOWN? Specifically: Should the MCU set SDA and SCL to high-impedance (input, no pull) before asserting PDOWN? Does any prior I²C communication prevent the chip from entering true hard power-down? Thank you. Follow-Up: CLRC66303 – High Current in Hard Power-Down Mode (CLEV6630ARD-Based Design) Dear NXP Team, I previously raised a query regarding hard power-down current with the CLRC66301HN, and your response recommended migrating to the CLRC663 Plus family (CLRC66303). I have since switched to CLRC66303B, using a custom board based on the CLEV6630ARD reference design, and I would like to follow up with updated test results. Your earlier reply focused on LPCD behavior and AN11783, but this issue concerns only hard power-down via the PDOWN pin, with no RF field or LPCD active. Power-Down Current Measurements (CLRC66303B): >When PDOWN is LOW (chip active, RF field on): ~100 mA >When PDOWN is HIGH and I²C pull-ups are present: ~1.2 mA >When PDOWN is HIGH and I²C lines are driven LOW: ~6.6 mA >When PDOWN is HIGH and I²C lines are physically disconnected before any use: ~40 nA  Only when SDA and SCL are physically disconnected before any I²C communication does the chip draw ~40 nA in PDOWN. If I²C is used even once, current remains high even after PDOWN is asserted HIGH. Hardware Setup Summary: Chip: CLRC66303B, I²C mode. MCU: TI CC2652R7, 100 kHz I²C Voltage: 3.3 V regulated Pull-ups: 4.7 kΩ to 3.3 V on SDA/SCL Unused pins: Pulled as per datasheet No RF or LPCD features enabled Schematic design: Based on CLEV6630ARD (attached) Questions for Clarification: 1. Are SDA/SCL internally biased during PDOWN mode? 2. Does any prior I²C activity prevent true power-down, even if PDOWN is later set HIGH? 3. Is it necessary to set MCU I²C pins to Hi-Z (input, no pull) before asserting PDOWN? 4. Is there an NXP-recommended method to reliably achieve <100 nA in hard PDOWN mode without physically disconnecting I²C lines? We aim to ensure battery longevity and must achieve the datasheet-stated low-power behavior. Any guidance or documentation specifically about PDOWN behavior and I²C leakage would be greatly appreciated. Schematic is attached for reference. Best regards, Umasankar C Re: CLRC66301B Power-Down Mode Still Consumes 2 mA Instead of nA Hello @Umasankarc Hope you are doing well.  I understand you are using a custom board based on CLRC66301HN (non-plus), is this correct? If so, please consider that we recommend using the CLRC663 plus family (CLRC66303) instead. HIGH level on pin PDOWN should enable a hard power-down. Power-down current (Ipd) stated in the Data Sheet corresponds to the sum of all supply currents in CLRC663 chip; however, additional power might be consumed by external components embedded in the board. Some recommendations for a low power design are described in AN11783 CLRC663 plus Low Power Card Detection, Section 3.4. Regards, Eduardo.

PCA9539 RESET 问题取决于 I²C 连接状态 你好 我正在使用 PCA9539 I/O 扩展器，遇到了意外的 RESET 问题，这似乎取决于 I2C 连接状态。 问题如下： 我通过 I²C 通信将 PCA9539 的所有输出端口配置为高电平。 输出引脚按预期保持高电平。 但是，当我移除 SDA/SCL 探头（用于监控 I2C 总线）时，PCA9539 似乎 RESET 了——输出引脚恢复到默认状态。 在此过程中，VCC 保持稳定，持续供电，RESET 引脚通过上拉电阻器保持高电平。 MCU 没有故意发出 RESET 信号或电源重启 其他说明： 在相同的测试条件下，PCA9538 没有出现这个问题。 存在 I2C 上拉电阻。 电源稳定，可与电容解耦。 RESET 引脚在事件期间未显示异常活动。 我怀疑，断开探测器连接时出现故障或启动/停止状态不完整可能会导致 PCA9539 的内部 I2C 状态机进入故障状态，从而导致类似RESET的行为。但是，我没有找到任何文件可以确认 PCA9539 是否可以在不明确 RESET 或重新通电的情况下清除其输出寄存器。 据我所知，就 I2C I/O 扩展器而言，只要有电源供应，无论是否连接了 I2C 探头，它都应保持其配置。您能确认这种理解是否正确吗？ 问题 在任何情况下，PCA9539 可以在没有 RESET 引脚断言或电源循环的情况下 RESET 其输出寄存器或 I2C 逻辑？ 拆除探头期间 SDA/SCL 出现的故障是否会导致设备进入故障状态并丢失其配置的输出？ 既然 PCA9539 和 PCA9538 的功能相似，为什么 PCA9539 会出现这种行为，而 PCA9538 却不会？ 不管 I²C 总线连接如何，只要有电源，I2C I/O 扩展器都应保持其配置，这是否正确？ 如果您对此行为有任何见解或官方文件，我们将不胜感激。 谢谢！

i.MX8MPカーネルブートロゴとyoctoプロジェクトのスプラッシュイメージを独自のカスタムロゴと画像に変更する方法 NXPサポートチーム様 U-Boot の最初から表示されるロゴや画像をすべて変更したいと思います。 HDMI モニターをボードに接続すると、4 匹のペンギンと、進行状況バー付きの Yocto プロジェクト イメージが表示されます。 それらの画像を自分のカスタム画像に変更したいと思います。 どのように変更すればよいか教えてください。 私は Yocto Linux imx を初めて使用するので、可能であれば詳しく説明してください。 よろしくお願いします。 Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i こんにちは、 @Rita_Wan 8MP_LVDS_patchに基づいて、U-Boot でディスプレイを正常に動作させることができました。しかし、カーネル部分を追加すると、U-Boot とカーネル表示間のシームレスな遷移が実現できませんでした。カーネル側では異常な動作 (画面のちらつき) が見られますが、U-Boot の表示はまったく正常です。 これについて何か提案をいただけませんか?問題の原因は何でしょうか? Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i こんにちは@bych 、 試すのに簡単な方法を見つけました: Linuxカーネルロゴ netpbm ツールを使用して、png 画像を ppm 画像に変換します。 $ pngtopnm linux_logo.png > linux_logo.pnm $ pnmquant 224 linux_logo.pnm > linux_logo_clut224.pnm $ pnmtoplainpnm linux_logo_clut224.pnm > logo_linux_clut224.ppm   変換した ppm ファイルをカーネルのドライバ/video/logo/ ディレクトリに配置し、logo_linux_clut224.ppm ファイルを置き換えます。 カーネルを再コンパイルすると、ロゴが新しい画像に置き換えられます。 お試しになることができます。 良い一日をお過ごしください Bset よろしく リタ Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i 私は i.MX8M Plus プロセッサをベースにした独自のカスタム ボードを持っていますが、このカスタム ボードは i.MX8M Plus EVK ボードと同じように設計されています。 ボードの起動に成功し、HDMI 経由のディスプレイも正常に表示されます。 しかし、私はブート ロゴ (4 つのペンギン) とスプラッシュ スクリーン (進行状況バー付きの Yocto プロジェクト ロゴ) を独自のカスタム ロゴに変更したいだけです。 パッチを提供してもらいましたが、そのパッチを u-boot またはカーネルに適用する方法がわかりません。 これらのパッチの使用方法と適用方法を教えてください。 ありがとう。 Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i あなたの手にあるボードは何ですか？nxp ボード、または自分でデザインしたボードでは、すでにボードを起動して表示していますか? Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i これらのパッチをどのように適用すればよいか教えていただけますか?これまでパッチを適用したことがありません... Re: How to change i.MX8MP kernel boot logo and yocto project splashimage to my own custom logo and i LVDS で実現されている u-boot およびカーネルのパッチを参照できます。方法はほぼ同じです。 U-Boot とカーネル間の i.MX 8MP LVDS シームレス ディスプレイ (连续显示) - NXPコミュニティ

S32G 无法通过串行端口编程的问题 S32G3 你好，根据问题，我再次使用 S32G399A 芯片。正常启动后，我连接串行端口，然后使用闪存工具进行刻录。错误报告界面如下所示，电流可下降约 30mA（12V 电源）。请您帮我找出原因，并确定我应该从哪个方向进行调查。谢谢。 Re: The issue of S32G failing to be programmed through the serial port 此问题已解决，谢谢回复。 Re: The issue of S32G failing to be programmed through the serial port 您好，从您更新的信息来看，问题有可能与您的时钟设计有关。 目前而言，在 S32 Flash 工具中，没有支持S32G3 custom board+Oscillator的功能，我并没有看到有目前可用的相关二进制文件来支持您的情况。 给您带来的不便很抱歉。 BR Chenyin Re: The issue of S32G failing to be programmed through the serial port 你好， 1、我现在根据S32G-VNP-RDB3设计的自己主板。 2，Flash Tool ：Version: 2.3.2,如下图。 3、我自己的主板，Flash型号是：MX25UW51245GXDQ00。 我现在遇到的这个问题，是否是因为时钟的问题引起? 我的时钟现在使用的是单端时钟。部分原理图如下。 然后，我下午把我的BOOTMOD[1:0]改为1:0后，可以烧录到SRAM中，并且串口也能打印出“hello world”，但是仍不能烧录到Flash。帮忙分析下原因。谢谢。 Re: The issue of S32G failing to be programmed through the serial port 你好，@龙岗素 谢谢您的帖子。 我知道你愿意刷新 S32G 板的 QSPI。 1。我能知道你是否在使用定制板吗？还是恩智浦的 RDB3/EVB3？ 2.使用的是哪个版本的闪存工具？ 3.如果是定制板，QSPI 的部件号是多少，它是你在 Flash 工具中选择的吗？ BR 切宁

使用 HSE 导入 RSA 中间证书的问题 您好， 我们目前在使用 HSE API 导入和验证 RSA 中间证书时遇到一个问题。 在进行必要的修改以支持 RSA 证书后，我们尝试导入中间 RSA 证书，并使用相应的根公钥对其进行验证。然而，尽管尝试了证书结构中 tbsOffset、tbsLen 和 signOffset 值的各种组合，HSE 始终返回响应代码：hse_srv_rsp_verify_failed 我们已经验证了证书和使用的密钥数据，根公钥的配置似乎是正确的。在不同的偏移配置和证书中，问题依然存在。 能否请您帮助我们找出可能出错的地方，或指导我们如何正确理解 RSA 证书结构中的偏移量（尤其是 rsaModulusOffset、rsaExponentOffset、tbsOffset、tbsLen 和 signOffset）？此外，HSE 内部是否有任何具体要求或检查可能导致核查失败？ 我们采用的方法与 hse_certificate.c 中演示的 ECC 证书导入方法（通过 HSE_ImportECCCert）相同。文件，该文件在 HSE FW 版本 HSE_DEMOAPP_S32G3XX_0_2_64_0 中共享。为了供您参考，我们附上了此文件和我们的请求。 如有需要，我们很乐意提供更多详细信息，如证书内容、根公钥和服务描述符配置。 期待您的支持。 Re: Issue with RSA Intermediate Certificate Import using HSE 你好，@Anup97 谢谢您的帖子。 我已经提到它也被张贴在私人文件夹中，让我直接在那里回复你，因为共享文件更方便。 感谢您的理解。 BR 切宁

uboot 跳转到内核会影响 llce_lin 的输出 你好，恩智浦 我们使用引导加载程序启动 M 核心 + A 内核，M 内核配置了 llce_lin 输出； s32g u-boot 跳转到内核，llce_lin 输出损坏，查询具体代码后找到； u-boot 代码：bootm.c-> announce_and_cleanup ()->cleanup_before_linux (void)-> board_cleanup_before_linux ();-> scmi_reset_agent ()； 我们发现， 由于调用 scmi_reset_agent 函数导致，M 内核配置 lce_lin 停止发送；由于 scmi（系统控制和管理接口）系统控制和管理接口 (SCMI) 是 启动 中的较低级别函数，内核，控制时钟、电源、io、RESET等，其中涉及 s32g 的底层控制逻辑；如何修改或配置为 解决导致 llce_lin 停止的 A-core 初始化问题？ 致以最诚挚的问候 Re: uboot jump to kernel affects llce_lin output 你好，@马松 感谢您的回复。 注释掉相应的行只是一种测试，并不是建议的解决问题的方法，因为这可能会影响到多个部分，从而导致像你发现的那样的问题。 我认为还需要进一步分析和测试，为了方便讨论和资源共享，请让我帮助创建一个支持案例来继续提供支持，我会直接通过邮件回复您。 很抱歉给您带来不便。 BR 切宁 Re: uboot jump to kernel affects llce_lin output 嗨，chenyin 我现在有一些关于 S32G 时钟的问题，基本上和图片中的问题类似； 1. tf-a 初始化时钟后 tf-a 不会退出吗？ 2. u-启动 和内核如何初始化或使用时钟，需要与 tf-a 通信？ 3. 你能详细解释一下在 tf-a、u-启动 和内核中是如何使用 clk 的吗？ https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-Bootloader-Customzition/tac-p/1771379/emcs_t/S2h8ZW1haWx8bWVudGlvbl9zdWJzY3JpcHRpb258TFBXQUozUkFGRzZFRjl8MTc3MTM3OXxBVF9NRU5USU9OU3xoSw BR. Re: uboot jump to kernel affects llce_lin output 嗨，chenyin 感谢您的回复， 我测试了评论过的 scmi_reset_agent 函数，并确认在 u-启动-> 内核跳转期间 llce_lin 输出正常。 但是，我发现内核启动后有异常，比如无法访问eth0 ping，因为我不确定是否还有其他问题，所以我没有按照这条线索进行调查； 你建议我做这样的调查吗？ BR. Re: uboot jump to kernel affects llce_lin output 从U-Boot到Linux内核的过渡确实会影响外围设备的输出，包括与LLCE-LIN（低延迟通信引擎——本地互连网络）相关的外围设备的输出，尤其是在恩智浦S32G等复杂的嵌入式系统中。 这主要是由于 U-Boot 和 猴子型 Linux 内核管理和初始化硬件资源 的方式不同 。 我们使用引导加载程序启动 M 核心 + A 内核，M 内核配置了 llce_lin 输出；s32g u-boot 跳转到内核，llce_lin 输出损坏，查询... 但是，它们的用途不同，管理方式也大不相同。-> U-boot 设备树用于配置和初始化启动过程中所需的硬件元器件，而 Linux 内核则使用设备树来描述内核启动后的硬件配置 Re: uboot jump to kernel affects llce_lin output 你好，@马松 感谢您的回复。 据我了解，U-boot 不会设置时钟，tfa 会在启动期间设置时钟。 对于当前的问题，您是否介意在测试时注释掉源代码中的 scmi_reset_agent，以检查您的测试是否仍然存在问题？ BR 切宁 Re: uboot jump to kernel affects llce_lin output 嗨，nxp 我继续在 u-boot 中追踪代码后发现了以下内容： 调用链：scmi_reset_agent (void)-> devm_scmi_process_msg (dev，& scmi_msg)-> scmi_smccc_process_msg (struct udevice *dev, struct scmi_msg *msg)-> arm_smccc_smc (chan-> func_id, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &res);-> SMCCC smc 对程序集进行了最后的调用，我不知道相关的细节，那么这部分代码是做什么的？它对 M 核心的运行有何影响，如何才能跳过代码执行的这一部分。 BR. Re: uboot jump to kernel affects llce_lin output 你好，chenyin 请提出一个问题，我们现在按如下方式启动流程 bootloader (M7)-> tf-a (A53)-> u-boot (A53)-> 内核 (A53) 我们已经在引导加载程序中配置了 uart 时钟，tf-a 中没有配置 uart 时钟，也没有在 u-boot 中进行任何修改； u-启动 中会重新配置 uart 模块和时钟吗？ BR. Re: uboot jump to kernel affects llce_lin output 你好，@马松 感谢您的回复。 我建议首先尝试检查 TFA 中的 UART 时钟及其来源。 BR 切宁 Re: uboot jump to kernel affects llce_lin output 你好，切尼 我知道现在就是这样运行的。 你还有其他发现吗？ BR. Re: uboot jump to kernel affects llce_lin output 你好，@马松 感谢您的回复。 既然你的 tf-a、u-boot 中只保存 ddr、xbar_2x 时钟，你的意思是说 UART 和外围设备 PLL3 的时钟也被禁用并在启动加载程序中设置，而不是在 TF-A 中设置？（在 TFA/uBoot 中，TFA/uBoot 只能从启动加载程序继承时钟设置来驱动 UART？） BR 切宁 Re: uboot jump to kernel affects llce_lin output 你好，陈怡 u-启动 中的 clk 转储如下所示： => clk dump Rate Usecnt Name ------------------------------------------ 40000000 0 |-- fxosc@40050000 51000000 0 |-- firc 32000 0 |-- sirc 20000000 0 |--ftm0_ext 20000000 0 |-- ftm1_ext 125000000 0 |-- gmac0_ext_rx 125000000 0 |-- gmac0_ext_tx 50000000 0 |-- gmac0_rmii_ref 200000000 0 |-- gmac0_ext_ts 100000000 0 |-- serdes_100_ext 125000000 0 |-- serdes_125_ext 125000000 0 |-- serdes0_lane0_ext_cdr 125000000 0 |-- serdes0_lane0_ext_tx 125000000 0 |--serdes0_lane1_ext_cdr 125000000 0 |-- serdes0_lane1_ext_tx 125000000 0 |-- serdes1_lane0_ext_cdr 125000000 0 |-- serdes1_lane0_ext_tx 125000000 0 |-- serdes1_lane1_ext_cdr 125000000 0 |-- serdes1_lane1_ext_tx 1 0 |-- pfe_mac0_rmii 1 0 |-- pfe_mac1_rmii 1 0 |-- pfe_mac2_rmii 1000000000 0 |-- a53 400000000 1 |-- serdes_axi 51000000 1 |-- serdes_aux 133333333 1 |-- serdes_apb 100000000 1 |-- serdes_ref 80000000 0 |-- ftm0_sys 0 0 |-- ftm0_ext 80000000 0 |-- ftm1_sys 0 0 |-- ftm1_ext 133333333 0 |-- flexcan_reg 133333333 0 |-- flexcan_sys 40000000 0 |-- flexcan_can 200000000 0 |-- flexcan_ts 62500000 0 |-- linflex_xbar 125000000 1 |--linflex_lin 0 0 |-- gmac0_ts 125000000 0 |-- gmac0_rx_sgmii 125000000 0 |-- gmac0_tx_sgmii 125000000 1 |-- gmac0_rx_rgmii 125000000 1 |-- gmac0_tx_rgmii 0 0 |-- gmac0_rx_rmii 0 0 |-- gmac0_tx_rmii 0 0 |-- gmac0_rx_mii 0 0 |-- gmac0_tx_mii 400000000 1 |-- gmac0_axi 0 0 |-- spi_reg 0 0 |-- spi_module 133333333 0 |-- qspi_reg 133333333 0 |-- qspi_ahb 266666666 0 |-- qspi_flash2x 133333333 0 |--qspi_flash1x 400000000 0 |-- usdhc_ahb 133333333 0 |-- usdhc_module 400000000 1 |-- usdhc_core 32000 0 |-- usdhc_mod32k 133333333 0 |-- ddr_reg 800000000 0 |-- ddr_pll_ref 800000000 0 |-- ddr_axi 400000000 0 |-- sram_axi 133333333 0 |-- sram_reg 133333333 0 |-- i2c_reg 133333333 0 |-- i2c_module 66666666 0 |--siul2_reg 51000000 0 |-- siul2_filter 133333333 0 |-- crc_reg 133333333 0 |-- crc_module 100000000 0 |-- eim0_reg 100000000 0 |-- eim0_module 66666666 0 |-- eim123_reg 66666666 0 |-- eim123_module 66666666 0 |-- eim_reg 66666666 0 |-- eim_module 66666666 0 |-- fccu_module 51000000 0 |-- fccu_safe 66666666 0 |-- rtc_reg 32000 0 |-- rtc_sirc 51000000 0 |-- rtc_firc 133333333 0 |-- swt_module 51000000 0 |-- swt_counter 133333333 0 |-- stm_module 133333333 0 |-- stm_reg 133333333 0 |-- pit_module 133333333 0 |-- pit_reg 400000000 0 |-- edma_module 400000000 0 |-- edma_ahb 80000000 1 |-- sar_adc_bus 666666660 |-- cmu_module 66666666 0 |-- cmu_reg 133333333 0 |-- tmu_module 133333333 0 |-- tmu_reg 133333333 0 |-- flexray_reg 0 0 |-- flexray_pe 66666666 0 |--wkpu_module 66666666 0 |-- wkpu_reg 66666666 0 |-- src_module 66666666 0 |-- src_reg 66666666 0 |-- src_top_module 66666666 0 |-- src_top_reg 133333333 0 |-- ctu_module 80000000 0 |-- ctu_ctu 200000000 0 |-- dbg_sys4 400000000 0 |-- dbg_sys2 400000000 0 |-- m7 133333333 0 |-- dmamux_module 133333333 0 |-- dmamux_reg 500000000 0 | -- gic_module 133333333 0 | -- mscm_module 133333333 0 | -- mscm_reg 133333333 0 | -- sema42_module 133333333 0 |-- sema42_reg 66666666 0 |-- xrdc_module 66666666 0 |-- xrdc_reg 0 0 |-- clkout0 0 0 |-- clkout1 100000000 0 |-- usb_mem 32000 0 |-- usb_low 0 0 |--pfe0_rx_sgmii 0 0 ||-- pfe0_tx_sgmii 0 0 |-- pfe0_rx_rgmii 0 0 |-- pfe0_tx_rgmii 0 0 |-- pfe0_rx_rmii 0 0 |-- pfe0_tx_rmii 0 0 |-- pfe0_rx_mii 0 0 |--pfe0_tx_mii 0 0 ||-- pfe1_rx_sgmii 0 0 |-- pfe1_tx_sgmii 0 0 |-- pfe1_rx_rgmii 0 0 |-- pfe1_tx_rgmii 0 0 |-- pfe1_rx_rmii 0 0 |-- pfe1_tx_rmii 0 0 |--pfe1_rx_mii 0 0 |-- pfe1_tx_mii 0 0 |-- pfe2_rx_sgmii 0 0 |-- pfe2_tx_sgmii 0 0 |-- pfe2_rx_rgmii 0 0 |-- pfe2_tx_rgmii 0 0 |-- pfe2_rx_rmii 0 0 |-- pfe2_tx_rmii 0 0 |-- pfe2_rx_mii 0 0 |-- pfe2_tx_mii 300000000 0 |-- pfe_axi 300000000 0 |-- pfe_apb 600000000 0 |-- pfe_pe 0 0 |-- pfe_ts 40000000 0 |-- llce_can_pe 200000000 0 |-- llce_sys 80000000 0 `-- llce_per 1000000000 0 |-- a53 400000000 1 |-- serdes_axi 51000000 1 |-- serdes_aux 133333333 1 |-- serdes_apb 100000000 1 |-- serdes_ref 80000000 0 |-- ftm0_sys 0 0 |-- ftm0_ext 80000000 0 |-- ftm1_sys 0 0 |-- ftm1_ext 133333333 0 |--flexcan_reg 133333333 0 |-- flexcan_sys 40000000 0 |-- flexcan_can 200000000 0 |-- flexcan_ts 62500000 0 |-- linflex_xbar 125000000 1 |-- linflex_lin 0 0 |--gmac0_ts 125000000 0 |-- gmac0_rx_sgmii 125000000 0 |-- gmac0_tx_sgmii 125000000 1 |-- gmac0_rx_rgmii 125000000 1 |-- gmac0_tx_rgmii 0 0 |--gmac0_rx_rmii 0 0 |-- gmac0_tx_rmii 0 0 |-- gmac0_rx_mii 0 0 |-- gmac0_tx_mii 400000000 1 |-- gmac0_axi 0 0 |-- spi_reg 0 0 |-- spi_module 133333333 0 |--qspi_reg 133333333 0 |-- qspi_ahb 266666666 0 |-- qspi_flash2x 133333333 0 |-- qspi_flash1x 400000000 0 |-- usdhc_ahb 133333333 0 |-- usdhc_module 400000000 1 |-- usdhc_core 32000 0 |-- usdhc_mod32k 133333333 0 |-- ddr_reg 800000000 0 |-- ddr_pll_ref 800000000 0 |-- ddr_axi 400000000 0 |-- sram_axi 133333333 0 |-- sram_reg 133333333 0 |-- i2c_reg 133333333 0 |-- i2c_module 66666666 0 |-- siul2_reg 51000000 0 |-- siul2_filter 13333333333 0 |--crc_reg 133333333 0 |-- crc_module 100000000 0 |-- eim0_reg 100000000 0 |-- eim0_module 66666666 0 |-- eim123_reg 66666666 0 |-- eim123_module 66666666 0 |--eim_reg 66666666 0 |-- eim_module 66666666 0 |-- fccu_module 51000000 0 |-- fccu_safe 66666666 0 |-- rtc_reg 32000 0 |-- rtc_sirc 51000000 0 |--rtc_firc 133333333 0 |-- swt_module 51000000 0 |-- swt_counter 133333333 0 |-- stm_module 133333333 0 |-- stm_reg 13333333333 0 |-- pit_module 13333333333 0 |--pit_reg 400000000 0 |-- edma_module 400000000 0 |-- edma_ahb 80000000 1 |-- sar_adc_bus 66666666 0 |-- cmu_module 66666666 0 |-- cmu_reg 133333333 0 |-- tmu_module 133333333 0 |-- tmu_reg 133333333 0 |-- flexray_reg 0 0 |-- flexray_pe 66666666 0 |-- wkpu_module 66666666 0 |-- wkpu_reg 66666666 0 |--src_module 66666666 0 |-- src_reg 66666666 0 |-- src_top_module 66666666 0 |-- src_top_reg 133333333 0 |-- ctu_module 80000000 0 |-- ctu_ctu 200000000 0 |-- dbg_sys4 400000000 0 |-- dbg_sys2 400000000 0 |-- m7 133333333 0 |-- dmamux_module 133333333 0 |-- dmamux_reg 500000000 0 |-- gic_module 133333333 0 |-- mscm_module 133333333 0 |-- mscm_reg 133333333 0 |-- sema42_module 133333333 0 |-- sema42_reg 66666666 0 |--xrdc_module 66666666 0 |-- xrdc_reg 0 0 |-- clkout0 0 0 |-- clkout1 100000000 0 |-- usb_mem 32000 0 |-- usb_low 0 0 |-- pfe0_rx_sgmii 0 0 |-- pfe0_tx_sgmii 0 0 |-- pfe0_rx_rgmii 0 0 |-- pfe0_tx_rgmii 0 0 |-- pfe0_rx_rmii 0 0 |-- pfe0_tx_rmii 0 0 |-- pfe0_rx_mii 0 0 |-- pfe0_tx_mii 0 0 |-- pfe1_rx_sgmii 0 0 |-- pfe1_tx_sgmii 0 0 |--pfe1_rx_rgmii 0 0 ||-- pfe1_tx_rgmii 0 0 ||-- pfe1_rx_rmii 0 0 |-- pfe1_tx_rmii 0 0 |-- pfe1_rx_mii 0 0 |-- pfe1_tx_mii 0 0 |-- pfe2_rx_sgmii 0 0 ||-- pfe2_tx_sgmii 0 0 ||-- pfe2_rx_rgmii 0 0 |-- pfe2_tx_rgmii 0 0 |-- pfe2_rx_rmii 0 0 |-- pfe2_tx_rmii 0 0 |-- pfe2_rx_mii 0 0 |-- pfe2_tx_mii 300000000 0 |-- pfe_axi 300000000 0 |-- pfe_apb 600000000 0 |-- pfe_pe 0 0 |-- pfe_ts 40000000 0 |-- llce_can_pe 200000000 0 |-- llce_sys 80000000 0 |-- llce_per Re: uboot jump to kernel affects llce_lin output 嗨，chenyin 1. Lin 时钟在引导加载程序中配置； 2. 我们使用 bsp42，在 tf-a、u-boot 中只保存 ddr、xbar_2x 时钟，所有其他配置都处于关闭状态，具体取决于启动加载程序的配置； BR. Re: uboot jump to kernel affects llce_lin output 你好，@马松 谢谢您的帖子。 1.我想知道 LIN 时钟是在引导加载程序中配置的，还是在 M7 内核上运行的 LIN 应用程序中配置的？ 2。您的测试设置中使用的是哪个版本的电路板支持包？对时钟设置有任何修改吗？你介意分享你的 u-启动 中的时钟转储吗？ BR 切宁

SDK1.9 でL2sw_binアプリケーションを変更する <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> NXP T1040およびT1020 SoCには、デバイスに8ポートのギガビットイーサネットスイッチが統合されています。 QorIQ SDKには、L2スイッチ・ユーザー・スペース・ドライバと、スイッチ・ドライバが提供するAPIを使用する小規模なデモ・アプリケーションが含まれています。L2Switch デモ アプリケーションは、T1040 でスイッチを設定するのに役立ちます。 添付ドキュメントには、SDK1.9でソースコードを変更し、スイッチレジスタに読み取りまたは書き込みアクセスするコマンドを追加する手順が含まれています。これを行う前に、SDK1.9をインストールして使用できるようにする必要があります。SDKのマニュアルには、SDKのインストール方法、ホスト環境の準備方法、特定のターゲットに対するpokyの設定方法などが記載されています。

NXP：蓝牙与信道探测天线 这些幻灯片是为马德里卡洛斯三世大学的欧洲天线学校准备的。内容： - 关于NXP和无线控制器 - 关于信道探测和NXP解决方案 - CS天线设计及功能测试 - CS天线阵列与CS定位

<video> L10 : S32G2 FOTA demo introduction L10 - S32G2 FOTA demo instroduction, by Ross(EN)/Xuewei(CHN) ref info for this session: Uptane Specification – here AUTOSAR Update and Configuration Management - here AN12978 – S32G2 Support for Firmware Over-The-Air (FOTA) updates Airbiquity Video Demonstration – here part 1 - FOTA recap (function() { var wrapper = document.getElementById('lia-vid-6255277370001w200h113r216'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) part 2 - S32G2 FOTA demo quick view (function() { var wrapper = document.getElementById('lia-vid-6255277091001w200h113r418'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) part 3 - S32G2 FOTA demo user guide walkthrough (function() { var wrapper = document.getElementById('lia-vid-6255275326001w200h113r928'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) part 4 - S32G2 FOTA demo explained (function() { var wrapper = document.getElementById('lia-vid-6255277306001w200h113r24'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) part 5 - S32G2 FOTA demo additional infomation (function() { var wrapper = document.getElementById('lia-vid-6255277390001w200h113r150'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) part 6 - S32G2 FOTA demo live (function() { var wrapper = document.getElementById('lia-vid-6255277227001w200h113r763'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) S32G

HMB-N1937 接続デバイス用のAndroidベースのBrillio OSの紹介 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Brilloは、Androidをベースにした軽量OSで、オープンで拡張性があり、安全な小さなフットプリントを備えたコネクテッドデバイス向けです。Brilloは、Androidプラットフォームを接続されているすべてのデバイスに拡張するため、セットアップが簡単で、相互に連携したり、スマートフォンとシームレスに連携したりできます。Googleの通信API「Weave」が付属しており、Brilloデバイスが相互に通信して交換したり、データをクラウドに保存したりするのを簡単に行うことができます。このクラスでは、Brillo と、NXP が Google と協力して Brillo を i.MX 6UltraLite プロセッサやその他のプラットフォームに導入した方法を紹介します。 ビデオプレゼンテーションを見る <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Brilloは、Androidをベースにした軽量OSで、オープンで拡張性があり、安全な小さなフットプリントを備えたコネクテッドデバイス向けです。Brilloは、Androidプラットフォームを接続されているすべてのデバイスに拡張するため、セットアップが簡単で、相互に連携したり、スマートフォンとシームレスに連携したりできます。Googleの通信API「Weave」が付属しており、Brilloデバイスが相互に通信して交換したり、データをクラウドに保存したりするのを簡単に行うことができます。このクラスでは、Brillo と、NXP が Google と協力して Brillo を i.MX 6UltraLite プロセッサやその他のプラットフォームに導入した方法を紹介します。 ビデオプレゼンテーションを見る スマートホーム&ビル

LPCXpresso IDE - Latest Release : v8.2.2 To download installers for all platforms, please visit: http://www.nxp.com/lpcxpresso   For installation and migration hints and tips, please visit: Migrating to a new version of LPCXpresso IDE   Current release: LPCXpresso 8.2.2 (build 650) September 2016   Changes in this release include: Upgraded GNU tools to ARM launchpad GCC 5 update 2 Fixed issues with debugging FreeRTOS applications Fixed issue with startup code generated by the New Project Wizard for LPC177x_8x family Latest LP18xx/43xx LPCOpen packages included in Examples : https://community.nxp.com/community/lpc/blog/2016/09/02/lpc43xx-lpcopen-updates-are-here  New LPC8xx series "code bundles" added to Examples : LPC8xx family code example bundles  Previous releases: LPCXpresso 8.2.0 (build 647) July 2016   Changes in this release include: Upgraded GNU tools to ARM launchpad GCC 5 update 1 Updated supported C/C++ dialects in IDE preferences and wizards Fixed issue with optimization level of CM4/HardABI Redlib C library build Fixed issue with Redlib strncasecmp() function incorrectly matching for some input strings Corrected size of third RAM bank from 32KB to 16KB on LPC1820, LPC1810 and LPC18S10 Fixed issue causing some peripheral registers not to be displayed debugging LPC5411x MCUs Target CPU automatically selected if possible when debugging multicore MCUs, based on project's CPU settings New "Resume all" and "Pause all" buttons for multicore debug sessions Enabled disassembly view to show opcodes by making GDB alway return opcodes when CDT requests disassembly information. Fixed backtrace issue when debugging inside interrupt handlers Fixed issue with IDE failing to use selected GDB when debug launch configuration modified to use different executable Resolved Mac OS X specific issue with USB reenumeration which could cause a Linkserver crash Fixed issue where flash driver could start with incorrect XPSR and improved error reporting Added support for additional devices in SPIFI flash drivers Added SPIFI flash driver for use with LPC40xx family (see FAQ: LPC40xx SPIFI Flash Driver ) Updated LPC-Link2 CMSIS-DAP firmware to allow SWO Trace and power measurement to run at the same time. Also to provide an alternative firmware variant that provides higher priority for serial-VCOM data Fixed issue with SWO Trace which could trigger IDE crash if trace collected for long period of time Improved SWO Performance Counters view Fixed a Power measurement buffering issue which could result in upto 20 samples per 3k being overwritten with newer data.   LPCXpresso 8.1.4 (build 606) Mid March 2016   Changes in this release include: Fixed issue with some debugger writes to memory silently failing LPCXpresso 8.1.2 (build 603) March 2016   Changes in this release include: Fixed issue with IDE failing to boot debug Linkserver on certain non-English Windows variants Fixed issue triggering GDB to occasionally crash when debugging interrupt handlers Upgraded Eclipse to Mars SR2 (4.5.2) and CDT 8.8.1   LPCXpresso 8.1.0 (build 597) February 2016   Changes in this release include: Upgraded GNU tools to ARM launchpad GCC 5 Added support for LPC5411x devices Updated LPC-Link2 CMSIS-DAP firmware, providing probe serial number support and additional power measurement functionality Support for debugging via multiple LPC-Link2 probes concurrently using the latest CMSIS-DAP probe firmware All Cortex-M debug connections are now made via Redlink LinkServer Project wizard mechanism updated to add -fno-common compiler option and -print-memory-usage linker option to new projects IDE no longer compares Freemarker linker script with a linker script created by the pre-LPCXpresso IDE v7.90 linker script generator Makefile projects now correctly save MCU settings, including memory configuration and flash drivers (required for debugging) "Average Power" view added to compliment existing "Power Measurement Tool" view (for use with latest CMSIS-DAP firmware on LPCXpressoV3 boards) Fixed issue with GUI / command-line flash programmer when programming images with certain complex layouts Fixed issue when connecting in attach mode to LPC18xx/LPC43xx projects that use the Generic SPIFI flash driver Old SPIFI flash drivers for LPC18xx/LPC43xx removed and replaced by copies of the Generic SPIFI driver Documentation restructured, splitting the old User Guide up into several manuals Resolved issues with LPC-Link1 booting on Mac OS X 10.11 El Capitan.The use of Mac OS X 10.11.3 or later is recommended LPC-Link2 Redlink firmware is no longer provided or supported. Use the default CMSIS-DAP firmware instead "Red Trace" (SWO Trace via Red Probe+) is no longer supported. Use SWO Trace via LPC-Link2 instead   LPCXpresso 8.0.0 (build 526) November 2015   Changes in this release include: Upgraded Eclipse to Mars SR1 / CDT 8.8 (plus Java 1.8) Upgraded GNU tools to ARM launchpad GCC 4.9 update 3 Support for multiple flash drivers within a single project Generic SPIFI flash driver source project debug build fixed so that it will execute on parts with internal flash (and less RAM) SWO ITM Trace Console View added to provide printf support via ITM Stimulus Port 0 Fixed an issue triggering error dialogs when the "Terminate All" option was used for non-multicore debug sessions Updated Redlink server/CMSIS-DAP LPC-Link2 firmware to support ISP reset of target MCU (requires target hardware support) Restart button now enabled on Mac OS X by default Note: Restart workaround on Mac OS X (due to an issue with GDB) may leave an unknown "thread" in the debug view - hit terminate again to remove this. Last release to support LPC-Link2 Redlink firmware. Use the default CMSIS-DAP firmware instead Last release to support "Red Trace" (SWO Trace via Red Probe+). Use SWO Trace via LPC-Link2 instead   LPCXpresso 7.9.2 (build 493) September 2015   Changes in this release include: Various fixes and improvements for  Freemarker linker script templates: Fixed link templates for LPC29xx and LPC3xxx Added '__base...' symbols for each memory region Fixed reporting of template errors in headless builds Corrected base address of SRAM2 block for LPC1517/47 Fixed issue with multicore symbols being defined by the IDE for non-multicore parts in some circumstances Improved handling of debug termination to allow target to clean up Instruction trace and SWO trace updated to avoid conflicts when both are trying to use DWT comparators SCT code generation updated to support latest LPCOpen register names Fixed rare issue with creating activation serial number on Linux hosts The use of LPC-Link2 Redlink firmware is now deprecated, and support will be removed in a future LPCXpresso IDE release. Use the (now default) CMSIS-DAP firmware instead The use of "Red Trace" (SWO Trace via Red Probe+) is now deprecated, and support will be removed in a future LPCXpresso IDE release. Use SWO Trace via LPC-Link2 instead   LPCXpresso 7.9.0 (build 455) July 2015   Changes in this release include: Initial support for Windows 10 Upgraded GNU tools to ARM launchpad GCC 4.9 update 2 New Generic SPIFI flash driver mechanism, which will autoconfigure based on SPIFI device detected in target system Enhanced managed linker script template mechanism Known as Freemarker linker script templates Simplifies projects which relocate code from Flash to RAM Support for generating LPC MCU vector table checksums directly in the image, using the startup file and linker script "Active Config" is now the default for the indexer Fixes to Multicore projects Fixed data sections placement Slave image now has bss and noinit sections removed, as they are not required Fixed an issue that was preventing MTB trace with LPC82x parts Extended CMSIS-DAP JTAG support (for Cortex-M parts) to include Keil ULINK2/ULINK-ME probes   LPCXpresso 7.8.0 (build 426) June 2015   Changes in this release include: New SWO Interrupt Trace Graph and Table views (Pro Edition only) LPC-Link2 will now soft-boot with CMSIS-DAP rather than Redlink firmware by default Improved selection of JTAG vs SWD connections - requires launch configurations to be recreated Fixed an issue with flash programming occasionally failing to initialize or complete Fixed an issue with debugging of LPC11A parts through LPC-Link2 Fixed a problem with semihosting output for C++ projects Fixed an issue with reading and displaying unaligned data from the target Fixed an issue with making an attach-only debug connection Fixed an IDE hang if resuming a debug session mid-way through editing a peripheral register Performance improvements when displaying registers Optimized display of Peripherals when editing fields or registers It is now possible to add miscellaneous command-line options to the GUI flash programming dialog Fixed an issue with the reset target option not working when flash programming an AXF file Added path when disambiguating Launch Configurations Wizards now generate liblinks.xml 'smart update' file in library projects, which will still work after a project is renamed Code generated by LPCOpen project wizards now calls SystemCoreClockUpdate() in all cases, not just when linking to a board library For multicore-capable systems an LPCOpen project wizard-generated main.c now only calls Board_Init() for a master core and not for slaves. LPC43xx wizards now generate code using new-style multicore defines Fixed an issue with SymbolViewer not being able to display source for C++ symbols De-cluttered the toolbar by removing the duplicate quickstart toolbar (this can be re-enabled using the User Interface Enablement preferences)   LPCXpresso 7.7.2 (build 379) March 2015   Changes in this release include: Added support for LPC18Sxx and LPC43Sxx parts Upgraded Eclipse to Luna SR2 (4.4.2) and CDT 8.6 Added Technology Preview of SWO Trace support with LPC-Link2 (Redlink) Further major improvements to Flash Download performance Added "Terminate, Build and Debug" Quickstart button SPIFI flash drivers now check for recognised parts CMSIS-DAP support extended to allow multi-core and JTAG debug connections (where supported by probe implementation) Fixed issue with managed linker script for multi-core projects which caused misalignment of slave data section Added support for M4 multi-core projects to use HardABI floating point variant Redlib realloc() fixed to handle heap memory becoming exhausted The LPCXpresso54102 board Power measurement tool is now included   LPCXpresso 7.6.2 (build 326) February 2015   Changes in this release include: Fixed managed linker scripts for GCC 4.9 NewlibNano library names Stopped tracking project selection in Symbol Viewer Added toolbar button for hide/show Red Trace views. Note that a restart of LPCXpresso is required after showing these views before Red Trace can be used. Fixed problem with MCU settings not being saved if changed by using the Quickstart Panel's Edit project settings button Display target chip and core type alongside executable name in Debug View   LPCXpresso 7.6.0 (build 321) January 2015   Changes in this release include: Upgraded GNU tools to ARM launchpad GCC 4.9 Significantly improved flash programming performance across all Cortex-M targets and debug probes Support for additional SPIFI flash parts based on latest LPCSPIFI Library v1.03 Added new Symbol Viewer feature to display the symbols in an object/library/executable Redlink firmware enhanced to improve performance and provide bridging capabilities similar to latest CMSIS-DAP Managed linker scripts now contain start and end symbols for all data and bss sections Improved highlighting of changed registers when single stepping Change colors of stub console messages - dark yellow for warnings and green for information Added support for m0 small-multiplier Redlib now implements single precision fmodf() in math.h Redlib free() will now coalesce with any consecutive free blocks Fixed problem with assembler -D option when selecting No library headers Fixed issue with Memory Configuration Editor when merging memory blocks during import Fixed issue with semihosting SEEK operation (affecting Redlib and Newlib fseek()) always resetting to the start of the file Fixed linker script generation for Internal builder Fixed display of second core index for LPC5410x part (from 16->1) Fixed Build All Projects if no project selected Fixed target connection sequence to avoid timeout when downloading very large applications   LPCXpresso 7.5.0 (build 254) November 2014   Changes in this release include: Upgraded Eclipse to 4.4.1 ('Luna SR1') and CDT to v8.5.0. Upgraded GNU tools to ARM launchpad GCC 4.8 update 3. Added support for LPC5410x devices. Default optimisation level reverted to -O0 (rather than -Og) for Debug builds. LPC18/43 project wizards now provide access to Memory Configuration Editor. Add ability to Merge memory configurations and join contiguous memory blocks in Memory Configuration Editor. Enhanced link-time-optimisation (LTO) options. Disable "Set library type" on projects where it is not applicable. Added a default workspace location for Linux. Redlib string.h functions extended to include implementations of (non-ANSI-standard) strcasecmp() and strncasecmp(). Fixed very rare cause of hard fault in Redlib malloc(). Prevented changing Peripheral registers while target is running. Fixed a problem preventing debug display of arrays within a structure within a union. Fixed issue with viewing of byte-sized peripheral registers, such as CM3/CM4 NVIC priority registers. Fixed issue with writing to byte-sized variables/registers. LPCXpresso 7.4.0 (build 229) September 2014   Changes in this release include: Support for LPC82x family. Upgraded to latest Eclipse release (4.4 'Luna') and CDT 8.4. This fixes a number of display problems with complex datastructure variables. Several improvements have been made to the Opcode display in the disassembly view. Opcodes can be displayed by right-clicking in the disassembly view margin and selecting 'Show Opcodes'. Eclipse Luna requires Java 7, which is installed on all platforms in the 'jre' subdirectory. This is independent of the 'System' Java installation, which is not affected. Disabled inline editing of the Pre/Post build steps and forced editing via a dialog. Peripherals displayed in Memory View now display hexadecimal, decimal, and binary in hover for 'numeric' values. Tidied up the toolbar to remove little-used buttons (which are still available in the Quickstart panel). Added new preprocessor defines for multicore projects. LPCOpen Project wizards will now prepopulate the chip library name where possible. Cleaned up inconsistencies in various Redlib header files. Redlib memcpy and related functions now avoid use of unaligned LDR/STR instructions on Cortex-M3/M4. Fixed various single-precision Redlib math.h functions. Fixed a peripheral problem with LPC11U6x/11E6x GPIO word registers. LPCOpen code bundles are now shipped inside the Examples subdirectory, though users are recommended to check LPCware.com for the latest versions. Absolute rather than relative paths are now used in the debugger for breakpoints by default for new workspaces. The default make command is now 'make -r', which should reduce build times, particularly on Windows. Added new Quick Settings menu for changing a project's FP type. Fixed a flash programming issue for LPC15x7 parts. Fixed a flash programming issue for certain LPC21xx/22xx parts. Updated SPIFI flash drivers based on LPCOpen 'LPCSPIFI' library to use v0.07, adding drivers for more SPIFI devices Improved support for the 'Dark' Theme. Now possible to modify the start address of the heap without modifying linker scripts/templates Mac OS X 10.7 (Lion) is no longer an officially supported platform. LPCXpresso may continue to work on Mac OS X 10.7, but this can no longer be guaranteed. LPCXpresso is no longer tested on Mac OS X 10.7.   LPCXpresso 7.3.0 (build 186) July 2014   Changes in this release include: Upgraded GNU tools to ARM launchpad GCC 4.8 update 2 Run->Debug As... now works correctly for MCU targets Fix problem that caused CMSIS-DAP to not be available for some targets Correctly terminate Redlink Server after using the Flash Utility Updated LPC15xx startup code generated by new project wizards to match interrupt handler names used by LPCOpen. LPC43xx M0 startup code no longer references systick (which is only implemented on M4 cpu in LPC43xx MCUs, not M0 cpus). Fixed issue with LPC43xx (Cortex-M0 basic) wizards failing to create startup file. Quickstart Debug button now respects the build setting in the launch configuration Additional LPC18/43 SPIFI flash drivers supplied, based on LPCOpen lpcspifilib. C Library memory allocator no longer checks new heap end against current stack pointer. New "boot_link1" and "boot_link2" scripts available on all platforms for downloading probe firmware from command line. Peripheral rendering "Refresh" option now forces re-read from target. Peripheral register fix for LPC15xx GPIO port word pin registers.   LPCXpresso 7.2.0 (build 153) May 2014   Changes in this release include: Improvements to reliability of Redlink server connections Add __MULTICORE_type pre-processor symbol to compiler for multicore projects Project wizards now place default main() into projname.c rather than main.c On Mac OS X, prevent occasional hang during Debug Probe discovery On Windows, the debug drivers are now built with Visual Studio 2013 to increase compatibility with latest version of Windows. Remove crt_directory.xml to build parts database dynamically at runtime     LPCXpresso 7.1.1 (build 125) April 2014   This is a bug fix release that solves a problem found in the initial release of v7.1.0. Fixed in this release are: Fix problem affecting LPC-Link2 debug connections to Cortex-M0+ cores Fix regression preventing debugging with CMSIS-DAP Fix for a Red State UI regression which prevented users from graphically adding an output pin to a signal     LPCXpresso 7.1.0 (build 122) April 2014   Changes in this release include: Upgraded IDE to Kepler SR2 and CDT 8.3 Upgraded GNU tools to ARM launchpad GCC 4.8 update 1 Fixed problem with C/C++ indexer being disabled on startup Further reliability improvements with LPC-Link2 connections Default optimisation level is now -Og for Debug builds Improvements to Create Binary option to allow multiple commands (for example checksum the created binary) Improved NVIC/SCB peripheral displays Added preference to display peripheral registers with leading zeroes Added preference for the array "chunk" size in variable and expression views Fixed issue with instruction trace when restart carried out Redlib limits.h updated for when compiler configured to treat unspecified chars as signed (instead of default of unsigned) Redlib now implements integer only version of vprintf() as well as floating point compatible version The wrench overlay icon is now correctly displayed on a file/folder with local build settings Prevent a Redlink Server debug session on a target that is already being debugged Updated RAMFUNC definitions provided by cr_section_macros.h Note: Due to the imminent discontinuation of support by Microsoft, Windows XP is no longer an officially supported platform. LPCXpresso may continue to work on Windows XP but this can no longer be guaranteed. LPCXpresso is no longer tested on Windows XP.   LPCXpresso 7.0.2 (build 102) March 2014   Note - there is a know issue with the indexer in v7.0.2. This can be fixed by a simple change to a configuration file. For details see here.   Changes in this release include: Fixed problem with setting breakpoints on Windows with source paths containing spaces Fixed problem with Memory Configuration editor losing changes Debugging of LPC12xx and LPC11A02/LPC11A04 are now supported with LPC-Link2 mproved reliability of LPC-Link2 when downloading large images SCT code generator version updated to 2.6: switched from using register names that are undocumented on some parts, e.g. CAP_L[0] to CAP[0].L. Users should regenerate their SCT code Managed linker script support for placing specific functions into RAM Fixed display of memory if first displayed when target is executing   LPCXpresso 7.0.0 (build 92) February 2014   Major new release with features including: Support for latest NXP MCUs (including LPC1500) New release of the GNU compilers – v4.8.3. Includes new ‘general’ optimization level, -Og. This new optimization level, aims at providing fast compilation, a superior debugging experience and reasonable runtime performance. Adds Link Time Optimization (LTO). This allows all the different compilation units that make up a single executable to be optimized as a single module (not suitable for debugging). Inclusion of a new small-footprint variant of the Newlib C and C++ library, known as NewlibNano. Use of this library can result in significantly smaller code size, especially of C++ applications. Note that further details on the use of these new options can be found in the compiler documentation that is provided in the IDE help system.] New release of the base Eclipse IDE – Kepler (v4.3). The Managed Linker script mechanism has been extended to support the features of new GNU compiler. 'New project' wizards can now invoke import wizards directly to allow importing of library projects required in creating of new project. gdbserver debug connections enabled -> Enables use of Segger J-Link.   LPCXpresso 6.1.4 (build 194) January 2014 Changes in this release include: Added support for LPC11U6x. Fixed profile and interrupt trace on LPC13xx (12-bit ADC) parts Fixed regression introduced in 6.1.2 where a wizard-generated dual-core slave startup file failed to compile Removed display of CRP option in the wizard for creating dual-core slave apps Fixed various file resource leaks in the IDE; ensure temporary files are cleaned up on exit Fixed linker script generation for LPC1102/1104 Startup files fixed for various parts to prevent name mangling issues in C++ projects Corrected flash driver references for certain LPC11A, LPC11E, LPC11xxLV parts Redlink connections now display correct debug protocol in debug log In project wizards, LPCOpen wizards are listed first if available LPCOpen project wizards for LPC13xx, LPC175x_6x, LPC177x_8x, LPC407x_8x now provided LPCOpen packages can now be browsed from the Import Project page CGU related updates to LPC18/43 CMSIS driver libraries (Windows) Rebuilt version of make provided (Linux) Added new udev rules for CMSIS-DAP probes   LPCXpresso 6.1.2 (build 177) December 2013 Changes in this release include: Added support for LPC11x37H parts including support for IOHandler. Added LPCOpen V2 project wizards for LPC18 and LPC43 families Fixed issue where not all slaves were displayed in the linker properties of a MultiCore project Added missing breakpoint/watchpoint menu items while debugging in the Develop perspective Fixed issue where Watchpoints not trapping with Redlink Fixed issue where Hard fault not trapped / VectPC updated with Redlink Fixed issue with Cycle count registers broken on LPC43xx using an LPC-Link2 Fixed failure of LPC12 project wizards to set "__DISABLE_WATCHDOG" symbol On Windows 8, use the LPC-Link1 WinUSB driver instead of HID   LPCXpresso 6.1.0 (build 164) Late October 2013 Changes in this release include: Introduced Red Trace SWV support for Red Probe+ Fixed issue connecting to a third core when debugging LPC4370 Extended range of prebuilt LPC18/43 SPIFI flash drivers Fixed problem with Watchpoints not being cleared Corrected debug startup with Red Probe+ when more than one FTDI-based device is present Fixed possible null pointer exception after editing memory configuration Fixed lost highlight when using keyboard to scroll through MCU selection Windows) Updated dfu-util/libusb to support additional USB3 hubs   LPCXpresso 6.0.4 (build 159) Early October 2013 Changes in this release include: Added support for ULink-2 CMSIS-DAP interface Fixed display of C++ global variables in Expression view Prevents use of JTAG for CMSIS-DAP connections (it is not currently supported) Added missing launch shortcut preventing display of correct launch config in Run/Debug Settings dialog Stopped display of debug probes when deleting JTAG configuration Fixed display of multiple debug probes reported by Redlink Server "Quickstart->Build all" now works when no projects are selected Fixed problem with memory configurations not being stored correctly Fixed Redlib problem with free() of null pointer Added c++0x and gnu++0x C++ compiler dialect options   LPCXpresso 6.0.2 (build 151) September 2013 LPCXpresso Forum

An Overview on QorIQ Trust Features for Securing Embedded Systems EUF-NET-T1742 - This session provides an overview on the security technologies NXP offers to secure a system through two complementary technologies: 1) the Trust Architecture already present in QorIQ P- and T-series including Secure Boot and 2) the TrustZone® technology introduced in the ARM®-based QorIQ LS series processors. We will outline the motivations for offering these technologies in embedded processors and show how they can be complementary for making a final system “Trustable” in the sense it does what its users and suppliers expect it to do. EUF-NET-T1742 - This session provides an overview on the security technologies NXP offers to secure a system through two complementary technologies: 1) the Trust Architecture already present in QorIQ P- and T-series including Secure Boot and 2) the TrustZone® technology introduced in the ARM®-based QorIQ LS series processors. We will outline the motivations for offering these technologies in embedded processors and show how they can be complementary for making a final system “Trustable” in the sense it does what its users and suppliers expect it to do.

ESC技术报告.pdf <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 飞思卡尔杯技术报告 韩国ESC团队 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 飞思卡尔杯技术报告 韩国ESC团队

一种检测不精确硬故障源的方法 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 本文档与Dragos Musoiu合作创建 尝试调试基于 ARM Cortex M4 的微控制器 MKW24D512 上的硬故障，我们没有找到太多关于处理不精确硬故障的文档。我们从 Erich Styger 的帖子“调试 ARM Cortex-M 上的硬故障”开始调查。基于此，我们使用Erich的代码来查找硬故障源，但无法找到导致硬故障的指令，因为围绕保存的PC执行的指令看起来是正确的。 之后，我们检查了硬故障状态寄存器，从 ARM Cortex M4 处理器的系统控制块中，我们发现 FORCED 位被设置了。ARM Cortex M4 文档提到，该位表示强制硬故障，由可配置优先级的故障升级产生，由于优先级或被禁用而无法处理。当该位设置为 1 时，HardFault 处理程序必须读取其他故障状态寄存器来查找故障原因。我们检查了其他故障寄存器，发现 ARM Cortex M4 处理器的系统控制块中的可配置故障状态寄存器（总线故障状态寄存器）中的 IMPRECISERR 位被设置。根据 ARM Cortex M4 文档，如果设置了此位，则发生数据总线错误，但堆栈帧中的返回地址与导致错误的指令无关。当处理器将此位设置为 1 时，它不会将故障地址写入 BFAR。所以这就解释了为什么我们没有按照 Erich 的指示找到导致硬故障的指令。此外，这是一个异步错误。因此，如果检测到当前进程的优先级高于 BusFault 优先级，则 BusFault 变为待处理状态，并且只有当处理器从所有更高优先级的进程返回时才会变为活动状态。 Cortex M4 处理器具有写入缓冲区功能，当对可缓冲内存区域进行写入时，处理器可以在传输完成之前继续执行下一条指令。这对于性能来说非常好，但可能会导致调试不精确的总线故障时出现一些复杂性。 通过更好地研究文档，我们发现 ARM Cortex M4 辅助控制寄存器中的 DISDEFWBUF 位在设置为 1 时会禁用默认内存映射访问期间的写入缓冲区使用。这会导致所有 BusFault 都成为精确的 BusFault，但会降低性能，因为任何存储到内存的操作都必须在处理器执行下一条指令之前完成。这样，处理器将不会继续执行下一条指令，直到写入操作完成，因此启用该位并使用 Erich 的代码，保存的 PC 指向导致硬故障的指令。 在其他情况下，如果总线故障是由中断处理程序中执行的指令触发的，且其优先级高于总线故障处理程序，则设置 DISDEFWBUF 在调试过程中很有用，因为即使出现精确错误，BFAR 寄存器值仍然有效。

DwF MCUおよびオートモーティブソリューション - Tianan - 2015-03-19 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 自動車およびコネクテッドカー 車載用マイクロコントローラの概要 : KinetisおよびS12 MagniVミックスド・シグナル・マイクロコントローラを含む BCCおよび高圧センサを搭載した車載用アナログおよびセンサの概要 インサイトとイノベーション Kinetisマイクロコントローラの概要 - Kinetisの性能上の利点とアプリケーション 設計、ソフトウェア、サービス フリースケールMQX™ RTOSの概要 ARM®プロセッサ キネティスCortex®-Mマイクロコントローラー センサ ソフトウェアとツール

汽车模拟和传感器概述，包括 BCC 和高压传感器 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Eric Wu 主讲 2015 年 3 月 19 日，天安 MCU 和汽车解决方案大会 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Eric Wu 主讲 2015 年 3 月 19 日，天安 MCU 和汽车解决方案大会 传感器