KW45 硬件设计建议 亲爱的恩智浦团队， 我想知道，如果我不将下图中给出的外部迹线从 CDD_CORE / VOUT_CORE 连接到 VDD_CORE，会出现什么问题。 我以为是一样的，所以没有从外部电路连接。会有问题吗？ 我遇到了一个奇怪的问题，能告诉我是什么原因吗？ 当电压从 3.1V 降到 3V 时，射频下降。 MCU 似乎能正常工作，因为我们实现了 LED 闪烁。 在某些情况下，如低于 2.5V 时，MCU 可以工作，但射频输出是错误的。 在某些情况下，例如电压低于 2.5V 时，MCU 会完全停止发送数据，我们可以看到大约 7/8/9/12mA 的持续功耗。 我无法理解，因为当我们降低电压或低电压时，总是会出现这种情况。 KW45B41Z-EVK KW45 BLE-NFC   如果两个引脚都是内部连接的，会有问题吗？ Kinetis K系列MCU Re: KW45 HW Design Recommendation 你好 希望你一切顺利。 您在设计中使用的电源配置是什么？您是如何为 VDD_RF 供电的？ 有关最常见的电源配置和注意事项，请参阅 AN13831 KW45/K32W148-电源管理单元硬件第 3 节 " KW45/K32W148 电源配置 "。 请注意，您的应用程序要求的任何电源配置都必须符合每个功率域的直流电压要求，该要求在第 2.2 节 " 电源域速率 " 中规定 内部稳压器输出由 VDD_CORE/VOUT_CORE 提供，稳压器输入由 VDD_CORE 提供。强烈建议在外部连接引脚以及适当的去耦电容，以提供反馈路径并保持电压稳定性。 您可以在这篇文章中找到我们的最低物料清单演示文稿，了解推荐的电容值和其他硬件建议：使用 KW 45（汽车）或 K32W1/MCXW71（物联网/工业）首次版本 PCB 的最佳方式 您还可以根据我们的 KW45-EVK 原理图来 确认您的 原理图 设计。 顺祝商祺！ 安娜-索菲亚

PF5030はすべての出力が失われた状態でI2Cを読み取ります こんにちは。致命的なエラーが発生すると、入力電源は維持されますが、PF5030 のすべての出力が失われます。I2C 経由で詳細な障害情報を取得する方法はありますか? VDDIO は出力の 1 つから供給されます。この状況では、VDDIO が失われ、I2C インターフェースが機能しない可能性があります。しかし、致命的なエラーが発生した後に外部 VDDIO を提供するとどうなるでしょうか? エラー メッセージは保持されたままになりますか、それともすでに失われていますか?エラーが発生した後に外部 VDDIO を供給し、I2C 通信を試行することで、エラーの原因をCANますか? Re: PF5030 read I2C while all output lost こんにちは、ポニーさん 致命的なエラー (ウォッチドッグ障害、監視対象レールの過電圧、障害カウンタのオーバーフローなど) が発生すると、PF5030 は DEEP-FS 状態に移行します。 DEEP-FS では、すべてのレギュレータがオフになります。 フェイルセーフロジックはVINから内部的に電源供給されている I²C インターフェースはフェイルセーフ ドメインにあり、VDDIO (1.71 V ～ 5.25 V の範囲) が存在すると再び機能するようになります。 VIN が POR しきい値を上回っており、デバイスの電源がオフ/オンされていない限り、フェイルセーフ レジスタ (例: FS_GRL_FLAGS 、 FS_OVUVREG_STATUS1 、 FS_DIAG_SAFETY 、 FS_STATES ) には次の内容が含まれます。 どの電圧モニターがトリガーされたか（OV/UVフラグ） ウォッチドッグエラーフラグ 障害カウンターとステートマシンのステータス これらのレジスタはPORまたは明示的な書き込みによってのみクリアされ、DEEP-FSに入ることによってはクリアされません。 FS_GRL_FLAGS （一般的な障害の概要） FS_OVUVREG_STATUS1 （VMONがトリガー） FS_DIAG_SAFETY (ウォッチドッグ、CRC、BIST ステータス) FS_STATES （現在のフェイルセーフ状態） VIN が失われていない限り、VDDIO に外部電源を供給して致命的なエラーが発生した後に詳細な障害情報を回復 CAN。VIN が POR を下回ると、すべての揮発性レジスタがクリアされます。 敬具、 ヨゼフ

GD3162 新しい回路図デザインで GD3162 ゲート ドライバを使用する予定です。NXP のサイトで短いデータシートを見つけました。完全なデータシートはありますか? Re: GD3162 この製品に関して要求されたドキュメントは管理リリース下にあり、NDA (秘密保持契約) に基づいてセキュア ファイル経由でアクセスできます。 アクセスをリクエストするには、こちらをクリックしてください: https://www.nxp.com/webapp-signup/docstoreReg  フォームの送信時に、有効な NDA のコピーをアップロードするよう求められることにご注意ください。NXPについてにまだNDAがない場合は、まずNDAのフォームにご記入ください。 https://www.nxp.com/webapp-signup/ndaReqForm NDA の準備ができたら、安全なファイルへのアクセスをリクエストできます。 プロセスを理解するには、以下のリンク/FAQを確認してください。 https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS https://www.nxp.com/support/support/secure-access-rights/secure-access-rights-faqs:SEC-ACCESS-FAQS

如何在定制 MIMXRT1176AVM8A 板 上运行恩智浦 SDK 示例 我有一块带有 MIMXRT1176AVM8A 处理器的定制板（与 MIMXRT1170-EVK 不同）。我想运行 SDK 示例，但在必要的修改方面需要指导。 我的硬件设置 微控制器：MIMXRT1176AVM8A（与 EVK 不同）。 外部闪存：S25FL128L（QSPI，16 MB）（与 EVK 的 W25Q512NWEIQ 不同）。 同步动态随机存取存储器(SDRAM)：W9812G6KB-6J (32 MB) *（与 EVK 的 W9825G6KH-5I 不同）。 其他更改：用于 LED 和 UART 引脚等的不同 GPIO 我需要什么帮助？ Flex-SPI NOR 闪存设置： 既然我使用的是 S25FL128L（不是华邦），我该如何更新 flex SPI 或配置 C 文件才能正常启动？ 同步动态随机存取存储器(SDRAM) 初始化： EVK 使用不同的同步动态随机存取存储器(SDRAM) 芯片。我应该如何调整 DCD 设置？ 调试技巧 将 SDK 示例移植到自定义板时常见的陷阱有哪些？ 请求： 谁能分享一下： 改编 SDK 示例的分步说明？ 自定义 Flex SPI/同步动态随机存取存储器(SDRAM) 设置的示例配置？ 提前感谢！ Re: How to Run NXP SDK Examples on Custom MIMXRT1176AVM8A Board 只要频率不超过 800MHz，就没有问题。 BR, Omar Re: How to Run NXP SDK Examples on Custom MIMXRT1176AVM8A Board MIMXRT1176AVM8A 的 Cortex-M7 内核工作频率为 800 MHz。MIMXRT1176DVMAA（EVK 的处理器）的主频为 1 GHz。 Re: How to Run NXP SDK Examples on Custom MIMXRT1176AVM8A Board 不，它是相同的元器件，但包装不同。 BR, Omar Re: How to Run NXP SDK Examples on Custom MIMXRT1176AVM8A Board 由于 EVK 使用的是 MIMXRT1176DVMAA 处理器，如果我使用 MIMXRT1176AVM8A 处理器的 EVK 示例，会有问题吗？ Re: How to Run NXP SDK Examples on Custom MIMXRT1176AVM8A Board 请参阅此文档：如何为 FLEXSPI 或非 闪存启用调试\ 本文件包含使用其他闪存时可进行调试的指南。 更详细的文档可能对您有所帮助：i.MX RT FLEXSPI 启动指南-恩智浦社区 关于同步动态随机存取存储器(SDRAM)，建议参考 SDK 示例来配置内存，DCD 使用相同的同步动态随机存取存储器(SDRAM)配置，因此它是在启动时加载的。这里有一些关于如何配置同步动态随机存取存储器(SDRAM) 参数的示例：已解决：双 16 位同步动态随机存取存储器(SDRAM) (W9812G6KH) 的 MIMXRT1176 SEMC 配置-恩智浦社区 致以最崇高的敬意， Omar

FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同時マルチスレッド (SMT) は、独立した実行スレッドがスーパースカラー CPU パイプライン編成をより効果的に利用できるようにする高度なプロセッサ マイクロアーキテクチャ機能です。2ウェイ・スーパースカラー・パイプラインでのSMT実装は、動的消費電力の増加が比較的少ないデュアル・スレッドの同時実行性を最大化します。このセッションでは、次世代のPower Architecture e200z9プロセッサ・コアに含まれるSMT機能と、このマイクロアーキテクチャによって達成可能なパフォーマンス/パワー・メトリックの向上に焦点を当てます。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同時マルチスレッド (SMT) は、独立した実行スレッドがスーパースカラー CPU パイプライン編成をより効果的に利用できるようにする高度なプロセッサ マイクロアーキテクチャ機能です。2ウェイ・スーパースカラー・パイプラインでのSMT実装は、動的消費電力の増加が比較的少ないデュアル・スレッドの同時実行性を最大化します。このセッションでは、次世代のPower Architecture e200z9プロセッサ・コアに含まれるSMT機能と、このマイクロアーキテクチャによって達成可能なパフォーマンス/パワー・メトリックの向上に焦点を当てます。 日時:FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 新しいe200z9はいつ発売されますか?

FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同步多线程 (SMT) 是一种先进的处理器微架构功能，它允许独立执行线程更有效地利用超标量 CPU 管道组织。双向超标量流水线中的 SMT 实现以相对较小的增量动态功耗最大化双线程并发性。本次会议重点关注下一代 Power Architecture e200z9 处理器核心中包含的 SMT 功能，以及通过该微架构可实现的改进的性能/功率指标。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同步多线程 (SMT) 是一种先进的处理器微架构功能，它允许独立执行线程更有效地利用超标量 CPU 管道组织。双向超标量流水线中的 SMT 实现以相对较小的增量动态功耗最大化双线程并发性。本次会议重点关注下一代 Power Architecture e200z9 处理器核心中包含的 SMT 功能，以及通过该微架构可实现的改进的性能/功率指标。 回复：FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 新款e200z9什么时候上市？

Watch The Freescale Cup EMEA Finals LIVE A Livecast has been set up for you to enjoy The Freescale Cup EMEA Finals on 28-29 April that are hosted at the Politecnico of Torino. Connect on Freescale Cup 2015 live streaming - SeLM - Politecnico di Torino Freescale Cup Content

eIQ Time Series Studio 命令行界面 eIQ Time Series Studio包含一个命令行界面 (CLI)，允许您通过命令行生成时间序列模型，就像在图形用户界面中一样。有关该功能的完整文档可在eIQ TSS 文档 中找到，还提供了包含基本按键命令的快速入门。 在 TSS 版本 1.5.5 中，有一些命令行界面问题需要注意，这些问题将在下一版 TSS 中得到解决。同时，这里有一些变通办法和说明： 库编译错误 使用库编译选项生成 TSS 库可能并非在所有情况下都有效，可能会返回"Not Found" 错误。 解决方法：将在下一版 TSS 中修复此问题。   Windows 工作区权限 在 Windows PC 上，启动 TSS CLI 服务器时指定工作区位置。由于权限问题，Windows 上的默认工作区可能无法正常工作，从而导致以下错误：[PYI-12556:ERROR]由于未处理异常，执行脚本 "server "失败！ 解决方法：使用 tss_c li 引擎启动--workspace 参数指定 TS S 具有读/写访问权限的工作空间目录位置   不要同时运行 CLI 和图形用户界面 TSS CLI 和 TSS GUI 不应同时运行。此外，如果 TSS 数据库位于共享服务器上，则一次只能有一个用户与 TSS CLI 交互，以避免 TSS 数据库出现竞赛情况。   引擎启动语法更正 TSS CLI 文档使用 t ss_cli 引擎启动 —engine ，但 正确的语法是： tss_cli engine -exe_path   Windows 命令提示符分隔符 使用 Windows 命令提示符和信号导入命令导入传感器数据时，请使用双引号 (" " ) 指定分隔符（即本例中的空格），而不是单引号 (' ')   术语澄清 "文档中的优化" 指的是训练时间序列模型的过程。   在培训过程中查找优化 ID 使用tss_cli optimization list --project_name cli_test_project查看优化列表，可以找到 my-opt-id 值。   查找标签名称 使用tss_cli signal list --project_name cli_test_project查看信号名称，可以找到仿真命令使用的标签名称值。   布尔参数 训练过程中的快速搜索等参数都是布尔值，在作为命令行参数的一部分加入时会自动启用。例如，使用-qs而不是-qs true。 下面是使用 eIQ Time Series Studio 命令行界面的示例： #Assumes the following items： #1) tss_cli 位于可执行路径（C:\Program Files\NXPe\IQ_TimeSeriesStudio-1.5.5） #2）数据集在 C:\tss\dataset 中 #3）将在 C:\tss\workspace 中设置一个工作区 #4) 许可证密钥已经从 TSS GUI 中获取 #5) TSS GUI 没有同时运行 #安装许可证密钥 tss_cli.exe license activate --key #Start TSS CLI t ss_cli 引擎启动-e " C:\Program Files\ NXP\ eiq_TimeseriesStudio-1.5.5\ tss_engine\ tss_engine.exe " —port 18000 —workspace " C:\tss\workspace " #Install license key tss_cli license activate --key #Create FRDM-MCXN947 tss_cli 项目的分类项目 创建--project_name cli_fan_project--algo_type cls--device FRDM-MCXN947--channels 3--label_target_num 4 # 列出工作区中的所有项目，并查看新生成的 cli_fan_project 的详细信息 tss_cli project list tss_cli project query --project_name cli_fan_project #Add training data tss_cli signal list --project_name cli_fan_project tss_cli signal import --project_name cli_fan_project --signal_name ON --file_path C:\tss\data\fan_state_monitoring_3channel\train\train_on.csv --label_id 1 --delimiter" " tss_cli signal import --project_name cli_fan_project --signal_name OFF --file_path C:\tss\data\fan_state_monitoring_3channel\train\train_off.csv --label_id 2 --delimiter" " tss_cli signal import --project_name cli_fan_project --signal_name FRICTION --file_path C:\tss\data\fan_state_monitoring_3channel\train\train_friction.csv --label_id 3 --delimiter" " tss_cli signal import --project_name cli_fan_project --signal_name CLOG --file_path C:\tss\data\fan_state_monitoring_3channel\train\train_clog.csv --label_id 4 --delimiter" " #Check training data tss_cli signal query --project_name cli_fan_project --signal_id 1 #开始训练模型。它将打印出一个 opt_ID 号，第一次运行时将是"1" 。 tss_cli optimization start --project_name cli_fan_project -qs --opt_name cli_fan_opt --signals 1 2 3 4 #Get opt_id number while training is running tss_cli optimization list --project_name cli_fan_project # 检查训练进度，获取模型排名，以选择 result_ids tss_cli optimization progress --project_name cli_fan_project --opt_id 1   #Can stop training if feel like have enough results tss_cli optimization stop --project_name cli_fan_project --opt_id 1 #Get the result_ids of the best result.在检查上述进度时，它也将是最高的 ID。本例中将使用 48 tss_cli optimization results --project_name cli_fan_project --opt_id 1 #Get Execution Time estimate for that model tss_cli library time_estimate --project_name cli_fan_project --opt_id 1 --result_id 48 #获取标签名称 tss_cli signal list --project_name cli_fan_project #Emulate 测试数据库 ts_cli 仿真启动--project_name cli_fan_project--opt_id 1--result_ids 48--test_file_info " 1 " C:\tss\data\fan_state_monitoring_3channel\test\test_on.csv " "--test_file_info " 2 " C:\tss\data\fan_state_monitoring_3channel\test\test_off.csv ""--test_file_info " 3 " C:\tss\data\fan_state_monitoring_3channel\test\test_friction.csv " "--test_file_info " 4 " C:\tss\data\fan_state_monitoring_3channel\test\test_clog.csv " " #Create a TSS library tss_cli library compile --project_name cli_fan_project --opt_id 1 --result_id 48 --save_path"C. \tss\ --arch cortex-m33 --toolchain GCC #Createa TSS library \tss\" --arch"cortex-m33" --toolchain"GCC" #创建 TSS 示例项目 tss_cli library sample_project --project_name cli_fan_project --opt_id 1 --result_id 48 --save_path"C:\tss" --arch"cortex-m33" --toolchain"GCC" NPU|ML

Motor synchronous control demonstration using EtherCAT with i.MX RT1180 (Japanese blog) We will demonstrate an integrated EtherCAT and motor control system, and introduce the high-performance microcontroller i.MX RT1180 that makes this possible. This demonstration showcases the synchronization capabilities of EtherCAT and the high-precision motor control that accompanies it. Motor synchronous control demonstration using EtherCAT Explanation of how the demo works The board configuration consists of three boards: one EtherCAT master board and two EtherCAT slave boards, which together achieve EtherCAT synchronization. The slave boards are equipped with motor drivers, and each slave board controls two motors, for a total of four motors. The two motors at each end are controlled by slave board 1 and slave board 2 respectively, which adjust the left-right position of the two motors in the center. The two motors in the center are also controlled by slave board 1 and slave board 2 respectively, and are responsible for meshing the gears together . Initially, the two central motors rotate synchronously with their gears meshed together, and then gradually separate to disengage. After the deactivation, the two central motors rotate at different speeds and approach each other again. The moment the gears mesh again, the two motors rapidly synchronize, achieving precise gear engagement. At the same time, the motors on both sides adjust the position of the two central motors to prevent them from colliding. After that, the separation, approach, and interlocking process is repeated. Now, let me explain why such advanced control is possible with the RT1180 microcontroller. i.MX RT1180 behavior First, within the i.MX RT1180 microcontroller, each core has a specific role. The M33 core (300MHz) is responsible for EtherCAT communication, and the M7 core (800MHz) is responsible for motor control. The M33 core runs on an EtherCAT stack, achieving faster read/write speeds, lower costs, energy efficiency, and higher communication and response speeds compared to external devices. The M7 core performs motor calculations (PWM) within 1.4 μs. This completes the update + ADC sample + closed loop vector control. The dual-core cooperative operation of the M33 and M7 ensures superior point control performance and guarantees the operation of high-performance motors. Furthermore, the generous 1.5MB of RAM memory improves work efficiency and leaves room for further customization by the user.   summary Based on these points, we believe the i.MX RT1180 is an optimal choice for those considering servo applications. The source code for this demo is available on NXP's Application Code Hub. Please see the link below for details. How to set up the motion control reference design on iMX.RT1180 =========================​ We are currently unable to respond to comments left in the " Comment " section of this post . We apologize for the inconvenience, but please refer to " Technical Questions to NXP - How to Contact Us( Japanese Blog) " when making inquiries.(If you are already an NXP distributor or have a relationship with NXP, you may ask your representative directly.) We will demonstrate an integrated EtherCAT and motor control system, and introduce the high-performance microcontroller i.MX RT1180 that makes this possible. This demonstration showcases the synchronization capabilities of EtherCAT and the high-precision motor control that accompanies it. (Reading time: 10 minutes) i.MX RT Processors MCUXpresso Motor Control Technology Focus Japanese Blog

EB tresos activation failed Hi Team, I was trying to download and activate a copy of EB Tresos by using EB Client License Administrator V1.5.1 with the following activation code: 6A94-974F-C73A-28C1 (valid until 03/31/2026) as reported on the NXP website. Anyway the activation fails repeatedly, with the following error messages: ERROR: flxActAppActivationSend (50040,41147,10248) The quantity specified exceeds maximum quantity allowed (0). Connection to FlexNet Operations Server failed. Could you please help me on this? Thanks & Regards, Sai Re: EB tresos activation failed Hi friend, I have same problem.  I think NXP team have not refreshed the license.  And I think the responsible team is on Lunar New Year holiday. Let’s wait and see. Log : Activating NodeLocked License 6A94-974F-C73A-28C1, Number Of Licenses: 1 Status: 4, Creating request Status: 5, Request created Status: 6, Context created Status: 7, Connected to remote server Status: 8, Request Sent Status: 9, Polling for response Status: 11, Done ERROR: flxActAppActivationSend (50040,41147,10248) The quantity specified exceeds maximum quantity allowed (0). Connection to FlexNet Operations Server failed. Re: EB tresos activation failed The code is refreshed. Let's check. I activated it successfully. Re: EB tresos activation failed Hello, It means that maximum amount of activation with this license key has been depleted. I have notified admin to update the code with one one if possible. Best regards, Peter

rw612 config The configuration tool is too annoying. I am using the RW612. In addition, the SDK is getting worse in newer versions. The configuration tool should generate the correct files in the root directory; although the .mex file exists, it is sometimes generated in a different folder. Overall, all of your tools and SDKs are horrible. Re: rw612 config Hello @gtecaskari, hope you are doing well. I'm sorry to read that you have encountered with some issues. To better analyze your issue could you please share your environment setup? Including your IDE (MCUXpresso IDE or MCUXpresso for VS Code), SDK version, RTOS, and the specific example that you are testing. Re: rw612 config Hi. thanks for your answer. I have tried all version, 25.6 -25.9 - 25.12 25.12 is getting worse . you can just compare it to stm32cubemx and can understand how awful is it. Re: rw612 config Hi @gtecaskari. Feel free to correct me if I'm wrong, but if you are using MCUXpresso for VS Code with Config Tools support, could you please confirm that you have followed the recommended workflow stated at the following page: Working with MCUXpresso Config Tools? Additionally, it would be very helpful if you share with me the steps that you are following in order to reproduce your issue.

Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, I am trying to execute basic ethernet testing from custom project on custom board. As a part of this project (which integrates different modules like SD card, CAN ,GPIO,ADC, Ethernet and EEPROM) basic ethernet send and receive is to be verified. But I am facing "freed buffer out of range error" before ping send. I have done all the basic initializations and configurations related to ethernet. I see the error is observed because of line  LWIP_ASSERT("Freed buffer out of range", ((idx >= 0) && (idx < ENET_RXBUFF_NUM))); in function "ethernetif_rx_free" (enet_ethernetif_kinetis.c) where the idx value I am getting it in negative. This complete functionality is working on EVK kit. What could be missing? Kindly suggest. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, All The issue happens to me too on my RT1024 customer board, it is likely to happen when i put a breakpoint somewhere and it stops here, and then resume to normal running is more likely  ends up this error. Regards! Ping Re: Freed Buffer out of Range Issue in Ethernet for RT1170 If the example project is working fine in your custom board, seems the problem is on SW side. You are not using FreeRTOS right? Seems there is something interfering with the behavior of the example, probably some configurations are missing or just the example flow is being affected due the rest of the application. I would recommend you to try to use the latest SDK release which is 2.15.000. If your issue still occurs with this release, then I’m afraid there is something wrong with the flow of your application. Regards, Daniel. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, Yes, the issue appears when implementing the merged source code in custom board. But, the individual source of Ethernet_ping,which was not merged with remaining interfaces is working fine in Custom board. Problem arises when the individual source of Ethernet is merged with remaining interfaces. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 If I am understanding correctly, when you run the SDK example it works. But when you add your custom application, the issue appears. Can you confirm? Regards, Daniel. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, Actually the individual source code of Ethernet is working fine in Custom board. When I'm trying to integrate the code then Ethernet is not working. I observed that EIR register's 25th (RXF), 26th (TXB), and 27th (TXF) bits are set to 0, and the RDAR register's 24th bit is updated to 0. But in working code of Ethernet this registers are set to '1'.  I suspect that these register updates are handled by interrupts, but I am unable to locate the specific handler responsible for these updates in my custom project codebase. Kindly help me. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Could you please double check if there are any peripheral changes (i.e. peripheral instances) needed in your project in order to make the EVK example work in your custom hardware? In case you already verified this, seems the problem is on the HW side. By any chance have you already verified your design with the HDG? Regards, Daniel. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, I am using SDK version 11.6.1. I'm trying to test lwip_ping_bm_cm7 example. It is working fine in EVK. But it is not working in custom board when tried to interface all the source codes with Ethernet. What might be the issue if we are facing "Freed Buffer out of range" occurs. Please help me with this. Re: Freed Buffer out of Range Issue in Ethernet for RT1170 Hi, What SDK version are you using? What is the SDK example you are using to test this? If I understood correctly, the application works fine in an EVK, am I right? Regards, Daniel.

IMX8M PLUS LPDDR4 2G compatibility We try to implement an ISSI IS43LQ32512A-046BLI 2GB RAM. After Calibration the RAM fails during the  memcpy SSN armv8_x32 test with 2000MHz configured. If I configure the RAM to 1500MHz it pass all the tests. Has anybody implement this LPDDR4 RAM? Is it in general compatible with IMX8M PLUS? i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Are you using DDR config tool run the Calibration? If yes,. please share your configuration page and fail log file. B.R Re: IMX8M PLUS LPDDR4 2G compatibility The IS43LQ32512A-046BLI (ISSI 2GB LPDDR4X SDRAM) is generally compatible with the NXP i.MX 8M Plus processor, as long as it adheres to JEDEC standards for LPDDR4/LPDDR4X memory. However, your issue with the memcpy SSN armv8_x32 test failing at 2000MHz (but passing at 1500MHz) is not uncommon and likely stems from configuration, board design, or calibration challenges rather than fundamental incompatibility. Compatibility Confirmation The i.MX 8M Plus supports LPDDR4/LPDDR4X memory up to 4266 MT/s (2133MHz clock), and the IS43LQ32512A-046BLI operates at up to 2133MHz (4266 MT/s data rate), which aligns with NXP's specifications. NXP's community forums confirm that similar ISSI LPDDR4X parts (e.g., IS46LQ32512A-046BLA2, which is an automotive variant of your model) are compatible with the i.MX 8M Plus, provided they follow JEDEC specs. Users have successfully implemented them without issues when properly configured. Potential Reasons for Your Test Failure at 2000MHz Based on similar reports in NXP and embedded forums: Timing/Configuration Mismatch: The i.MX 8M Plus DDR controller requires precise timing parameters (e.g., CAS latency, tRCD, tRP) from the RAM's SPD/ datasheet. At 2000MHz, your calibration might not fully optimize for the ISSI part's specs (e.g., CL=32, RL=14 at higher speeds). Lowering to 1500MHz reduces stress and passes, but this indicates suboptimal tuning. Board Design Issues: Signal integrity problems like trace length mismatch, impedance errors, or insufficient power decoupling can cause failures at higher speeds. Check for reflections or noise on DQ/DQS lines using an oscilloscope. Calibration Limitations: The i.MX 8M Plus uses NXP's DDR Tool for calibration. If your script or settings are based on Micron/ Samsung references (common in EVKs), they may not match ISSI's characteristics. Re-run calibration with ISSI-specific parameters. Power/Temperature: At 2000MHz, higher current draw could cause voltage droop or overheating, failing memcpy tests (which stress sequential reads/writes). Has Anyone Implemented This RAM? Yes, there are documented implementations: In NXP community threads, users have integrated similar ISSI LPDDR4X (e.g., IS46LQ series) on custom i.MX 8M Plus boards for industrial applications, achieving stable operation up to 2133MHz after fine-tuning. Embedded Linux/BSP developers report success with ISSI parts in Yocto-based builds, but often with custom DDR init scripts to handle the 512M x 32 organization (16Gbit density). Recommendations to Fix Your Issue Verify Datasheet Alignment: Download the ISSI datasheet (IS43/46LQ32512A series) and compare timing params with NXP's i.MX 8M Plus RM (Reference Manual, Section 13.5 DDR Controller). Key specs for your RAM: 2133MHz max clock, LVSTL interface, 1G x 16 organization (dual-channel x32 total). Re-Run Calibration: Use NXP's DDR Test Tool or SCFW DDR Config Tool with ISSI-specific stress tests. Start at 1600MHz, gradually increase to 2000MHz while monitoring eye diagrams. If using U-Boot/Linux, update the device tree (.dtb) with correct timings (e.g., mx8mp-ddrc-devfreq.dtsi). Board-Level Checks: Ensure VDDQ = 1.1V, VDD2 = 0.6V, with clean decoupling (capacitors close to pins). Use a signal integrity simulator (e.g., HyperLynx) to verify traces. Test with lower temperatures or better cooling to rule out thermal throttling. If Still Fails: Contact NXP support via their community or ticket system — provide your calibration logs and board schematics. Consider switching to validated RAM like Micron MT53E512M32D2NP (NXP EVK default) for comparison. Overall, the RAM is compatible, but your 2000MHz failure is likely a setup issue. If you share more details (e.g., calibration logs or board schematic snippets), I can help troubleshoot further! I suggest contacting +8526583 (7594) via the messaging app; obtain the EOL document from him and then make a recommendation. He can help you Re: IMX8M PLUS LPDDR4 2G compatibility On the used board we have sucsesslully runing 3GB (MT53E768M32D2ZW-046 WTC) and 4GB (MT53E1G32D2FW-046 AAT:B) Micron LPDDR4 on 2000MHz. Re: IMX8M PLUS LPDDR4 2G compatibility Thanks for your support. In Attachments i send you the configuration .xls and the test log. Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , Same result with the config Tool V 13.1. Maybe our configuration is wrong for the IS43LQ32512A-046BLI? Can you provide the correct configuration (*.ds file)? Our hardware desing is a 1:1 copy of the eval board regarding the LPDDR4 interface.  Kind Regards Tobias Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye Please use the below link download our DDR Config Tool and run the ddr test wIth configure 2GB dram.  https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX B.R Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Please use below setting run the DDR test. B.R Re: IMX8M PLUS LPDDR4 2G compatibility Thanks for your Config Exaple. Its the same I already tryed with this RAM and still get the error. Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  It's strange. Please share your DDR Config Tool v25.12 fail log B.R Re: IMX8M PLUS LPDDR4 2G compatibility hHi @pengyong_zhang  for stresstest we use the Mscale DDR Tool 3.31. I will do it with the other config tool Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , here is the log of the stresstest. We have the same Problem wirth an 4GB ISSI IS43LQ32K01S2A-046BLI.  Re: IMX8M PLUS LPDDR4 2G compatibility Hi @TMpieye  Did you run the stress test with our DDR Config Tool? From your log file, it seems not from the Config Tool output. Also use out latest tool version v25.12. B.R Re: IMX8M PLUS LPDDR4 2G compatibility Hello @pengyong_zhang , I run the tes in the config tool and and its passed. So it seems to be a tool problem with the MSCALER tool. Many thanks for your great support!

eIQ and MCUXpresso SDK 26.03 with VSCode There are some items to be aware of when using eIQ projects in VSCode with MCUXpresso SDK 26.03 Debugger hangs when debugging eIQ examples on i.MX RT700 in VSCode There are two work-arounds available: 1) Use a JLink to debug the project instead of the default CMSIS-DAP interface. To do this: Install LinkServer Put a jumper on JP20 on the i.MX RT700 EVK, Update the MCULink firmware to use JLink by running C:\NXP\LinkServer_25.12.83\MCU-LINK_installer\scripts\program_JLINK.cmd Take off the jumper on JP20.  2) Alternatively update the linker file in the eIQ project:  Open the MIMXRT798Sxxxx_cm33_core0_flash.ld linker file in Repository->mcusdk->examples->_boards->mimxrt700evk->eiq_examples->tflm_label_image->cm33_core0->gcc  (use the path based on the eIQ project name that you are trying to use) In that linker file go to line 198 to 203 and replace the .ncache section with the code below:   .npu_ncache (NOLOAD) :   {       KEEP(*(.npu_ncache_data))       KEEP(*(.npu_ncache_data*))   } > m_ncache   ASSERT(. < 0x20580000, "Error: .npu_ncache cannot go beyond SRAM P18")   .ncache (NOLOAD) :   {     *(NonCacheable)     . = ALIGN(4);     __noncachedata_end__ = .;     /* define a global symbol at ncache data end */   } > m_ncache i.MX RT700 eIQ HiFi4 and HiFi1 projects cannot be imported or compiled in VSCode or command line GCC. In VSCode use the "Repository" import option. To compile the projects you must install Xtensa Xplorer, the RT700 license, and RT700 NewLib DSP Configuration file. Then add the following environmental variables: XCC_DIR=/ /XtDevTools/install/tools/RI-2023.11-win32/XtensaTools XTENSA_CORE=rt700_hifi4_RI23_11_nlib The project can then be compiled with command-line GCC with: west build -p always --sysbuild examples/eiq_examples/tflm_cifar10_hifi4/cm --toolchain armgcc --config flash_debug -b mimxrt700evk -Dcore_id=cm33_core0 Note that if using HiFi1 projects then XTENSA_CORE should be set to rt700_hifi1_RI23_11_nlib Also an additional compile option called -mlongcalls needs to be used to avoid issues when adding additional operators the ops list. Inside \mcuxsdk\examples\_boards\mimxrt700evk\eiq_examples\tflm_cifar10_hifi4\hifi4 edit the reconfig.cmake file in the mcux_add_xtensa_configuration options: mcux_add_xtensa_configuration( CC "-DXOS_CLOCK_FREQ=237500000 -std=c99 -mlongcalls" CX "-stdlib=libc++ \ -mlongcalls \ -std=c++17" ) A warning message comes up in eIQ Neutron SDK 3.1.2 If using eIQ Neutron SDK 3.1.2 then the follow warning will appear on the serial terminal during the model initialization: Unable to save model handle, call neutronModelUnprepare() when done This warning is not relevant for Neutron C devices like RT700 and MCX N and can be ignored as it does not impact inference time or accuracy. It will be fixed in the next eIQ Neutron SDK release. Some eIQ files that are commonly modified are shared among all eIQ examples For example, the Neutron libraries are shared among all eIQ examples. This can cause version compatibility issues with the default eIQ examples if the eIQ Neutron libraries are updated with eIQ Neutron SDK. This is because the eIQ projects in MCUXPresso SDK were converted using Neutron Converter 3.0.0 and the Neutron libraries in the SDK are shared among all eIQ projects.  To work around this, either revert the Neutron libraries back to version 3.0.0 or else download a separate repository to use the default eIQ examples. 

RT1170 MIPI-CSI カメラ - YUV422 (8 ビット) サポート こんにちは、 i.MX RT1170 MIPI-CSI インターフェースを使用して YUV422 (8 ビット) を出力するカメラ モジュールの使用方法を示すリファレンス デザイン、アプリケーション ノート、またはサンプル プロジェクトはありますか? RT1170 エラッタ ( https://www.nxp.com/docs/en/errata/IMXRT1170ACE.pdf ) を確認し、YUV422 10 ビット形式はサポートされていないことを理解しましたが、YUV422 8 ビット操作を具体的に示す公開例や確認は見つかりませんでした。 あらゆるガイダンス、動作が確認されている構成、またはカメラ モジュールの例があれば、大変助かります。 Re: RT1170 MIPI-CSI Camera - YUV422 (8 bit) support こんにちは@mtreloarさん、 NXP MIMXRTシリーズにご興味をお持ちいただきありがとうございます。 RT1170 MIPI-CSI は YUV422 (YUYV 8 ビット) 形式をサポートします。SDK のこのサンプル プロジェクトを参照できます。 よろしくお願いします、 ギャビン

以太网驱动程序读取 PHY 地址（LAN 9646） 大家好 我尝试用Eth_43_GMAC_ReadMii 函数读取 LAN 9646 的 PHY 地址，但返回的结果出乎意料。我只想问，这个功能是否适合用于读取 PHY 地址。感谢您的阅读。 Re: Read PHY address (LAN 9646) by Ethernet driver 您好， 是的，Eth_43_GMAC_ReadMii 是使用第 22 条通过 MDIO 读取 PHY 寄存器的函数。 不清楚您在函数中使用了哪些参数，以及得到了什么读数。确保使用设备数据表中指定的正确的 PHY 和寄存器地址进行标准 MIIM 寄存器（直接）访问。 还要确保选择了 MIIM 接口，根据设备 DS，它不是默认接口，而是通过捆绑选项配置的。   BR, Petr

S32N55：充当 GM 时 gPTP 桥接设备中的序列 ID 队员们好 我正在测试gpTP示例中的网桥设备行为。我使用的是 GrayVIP_1_0_22_0。 根据《用户手册》，如果网桥在 启动超时则应开始作为 GM 运行。但我观察到，在这种情况下，同步和同步跟进帧中的序列 ID 都保持在 1024，不会增加。 检查相关代码后，我发现当网桥转换到 GM 模式时，用于生成同步信息的序列 ID 取自 prSyncMachines[prDomain->u8SlaveMachineId].u16SequenceId 从端口的序列号。 如果从端口没有收到任何同步报文，则该值永不更新，这将导致主端口发送的同步报文中的序列 ID 保持不变。 这种行为表明，在这种机制下，桥梁无法正常发挥全球机制的作用。 能否请您解释一下，为什么大桥的设计会出现这种情况？ BR, Bridget GPTP_STACK Re: S32N55: sequence ID in gPTP bridge device when acting as a GM 你好，@Bridget、 我们的团队已经受理了一个案件，并将尽快提供答复 ，致以最崇高的敬意， Radu Re: S32N55: sequence ID in gPTP bridge device when acting as a GM 嗨，@Bridget、 我们正在努力重现该问题，并将在团队中讨论进一步的步骤。我会再联系你的。 谢谢， Lukas Re: S32N55: sequence ID in gPTP bridge device when acting as a GM @Bridget、 事实证明，gPTP 网桥的这种行为是有意为之，符合 802.1as 标准。 网桥应转发主端口上接收到的序列 ID。如果Grand Master丢失，序列ID确实会停止更新——这是下游设备能够分辨GM何时丢失的方式之一。 对于本来就没有总经理的桥梁，序列 ID 按标准是随机的。我们对 "随机"的解释是，序列 ID 的任何内容都不能保证，也不应假设。硬编码的 1024 被认为符合这一要求（可以是任何其他数字）。 序列 ID 是否会导致应用程序出现问题？正如您所观察到的，无论序列 ID 如何，端点都完全能够与网桥同步。 抱歉花了这么长时间。如果有不清楚的地方，请告诉我。 BR, Lukas

ADC Self-Test (Square Check) Support for S32K314 Hello,  In the UM Square Check documentation that an ADC self-test mechanism is mentioned. However, when reviewing the Safety Mechanisms, the ADC self-test is marked as NONE, and we are also unable to find this option in the Square Check (SCheck) configuration for the S32K314 package. Please advise how this feature can be enabled or configured? Priority: HIGH Safety_SW Re: ADC Self-Test (Square Check) Support for S32K314 Hello Team, Is there any update? Thanks Re: ADC Self-Test (Square Check) Support for S32K314 Hello Team, Is there any update? Thanks Re: ADC Self-Test (Square Check) Support for S32K314 Hello Radoslav, What is the different between S32K3E and S32Kxx? It seems both of them are the group of S32K396, S32K394, S32K376, S32K374, S32K366 and S32K364? Can you please point out where to find the S32K3E specific RM and HW Safety Manual ? Thanks Re: ADC Self-Test (Square Check) Support for S32K314 Hello @JasonTsengSG , my understanding is that these are new K3 derivatives with higher performance and some additional support for traction inverters and motor control (eTPU): S32K3E_SW_Architecture.docx You can find RM and SM via intranet e.g. here (sometimes instead K3E you can use just specific K396 derivative name to address this K3 sub-group): Zebra - Documents - S32K396 - All Documents Automotive Safety Software - Release_1.0.6 - All Documents Kind Regards, Radoslav Re: ADC Self-Test (Square Check) Support for S32K314 Thank you, Radoslav, for the clear explanation.

S32 Design Studio 3.6.5 Release Announcement Product Release Announcement Analog & Automotive Embedded Systems S32 Design Studio 3.6.5 The Analog & Automotive Embedded Systems (AAES) - Software Development Tools Engineering Team at NXP Semiconductors is pleased to announce the release of the S32 Design Studio 3.6.5 with support for: AMCU AP RAS APN S32K3 Family S32G Family S32R41 Family S32J Family S32K1 Family S32ZE Family S32R45 Family   S32M2 Family S32N Family S32R47 Family       SAF8xxx Family   Major Features for S32 Design Studio 3.6.5 Installer S32 Design Studio 3.6.5 is delivered with all public NPI's in a single 2.63GB installer to improve first time user experience. Additional packages for alpha customers are available based on Flexera entitlement and can be installed on top of S32 Design Studio 3.6.5 using Extension and Updates.   Installer will require admin rights only when the user chooses to install components which need elevation (Visual Studio Redistributable or debugger drivers). If a user chooses a custom installation only with S32DS IDE and its components (no drivers) the installation will finish without admin rights. Platform IDE and UI Integrated Cody, the open-source Eclipse plugin from Sourcegraph, into S32 Design Studio. This plugin is installed by default, allowing users with a valid Cody license to log in directly within S32DS and access Generative AI features. Note: Users must agree to the Sourcegraph Terms of Service before using Cody. Enabled integration with the NXP Application Code Hub, allowing users to browse available examples and import them directly from the hub page into S32 Design Studio. Note: the application examples will be published soon on the Application Code Hub URL. Note: This image is taken from internal sources. The illustrated examples are currently under development and will be available soon. Extended the Quick Fix mechanism for the missing NPI and Real Time Drivers packages. Basically, an error message displays in the Problems view whenever the IDE identifies a missing package (build tool, NPI, RTD) associated with the current project. The Quick Fix automatically installs the missing package if it is available in the configured Update Sites. Note: not all scenarios are covered, there may be cases where the tool cannot determine if a package is missing. A new Recent tab has been added in S32DS Extensions and Updates to display the latest installed packages, providing a clear history of user actions related to package installations. In addition, the default sorting was changed in All tab to bring greater visibility to NXP packages. Added support for drag-and-drop of S32 Design Studio p2 update sites / installable packages into the S32DS Extensions & Updates window. Users can now simply drag the ZIP file into the window, and the package will be automatically inserted and selected, requiring only a click on Next to complete the installation. Significant improvements to Secure Debugging:  Added a dedicated Debug Card view that allows users to generate debug card binaries based on custom input. Implemented Challenge & Response functionality for Linux environment.  Enabled Secure Registry Key view for managing secure registry keys on Linux.  UI is aligned to the secure debugging functionality latest changes introduced by HSE2. Extended the S32 Debugger OS awareness support with FreeRTOS. OS threads are now visible in S32 Design Studio and user will be able to individually debug them. Extended the command line support to display OS threads and objects. Enable debug in low power mode with S32 Debugger for S32K3xx devices:  The debug session will recover after core exits low power or standby mode, allowing the user to continue application debugging. Debugging from the first instruction after low power exit is now possible by using this configuration command when starting the debug session: monitor template config :ccs:S32K3XX:SoC#0 6 1 Expanded the S32Trace debug-info parser to fully support DWARF-5, adding compatibility with projects using GCC 11.4 and newer. Major Features for NPIs S32N Family S32Flash Programmer improvements for erase and verify write operations on S32N5. S32G2/G3, S32J100, and SAF8xxx Families S32J100 development package is now public and delivered inside S32DS installer. Enabled debugging support for S32G2 devices on VDK R10. S32Flash Programmer enhancements for erase and verify write operations. Various bug fixes and improvements for arm cores and accelerators. This release is available for download on: S32 Design Studio 3.6.5 can be found on  nxp.com  Flexera catalogue S32 Design Studio for S32 Platform v.3.6 Target Audience: S32 Design Studio 3.6.5 and bundled NPIs releases are targeted for public audience. The Installation Procedure for Packages: Download S32 Design Studio v3.6.5, available on nxp.com and in Flexera catalogue S32 Design Studio for S32 Platform v.3.6. If you have any local admin restrictions(ex. Admin by Request) the installer will request elevation, alternatively you can use “Run as Administrator” to run the installer. Download any additional packages if it’s required. Start S32 Design Studio v3.6.5 and install the desired package. Go to  Help > S32DS Extensions and Updates. For additional packages, in the S32DS Extensions and Updates dialog box, drag the ZIP file into the window, and the package will be automatically inserted and selected, requiring only a click on Next to complete the installation, or click Add Update Sites. Navigate to the directory with the downloaded ZIP file. Choose it and click Open, then click OK. You will get back to S32DS Extensions and Updates and can use this dialog to select desired packages.​​ Technical Support: Please use the public community for general questions: https://community.nxp.com/community/s32/s32ds For internal packages please use INTERNAL S32DS NXP Community space:https://community.nxp.com/groups/internals32ds

ADV7535：显示屏上无图像输出 嗨，团队、 我们正在基于 Verdin Yavia IMX8M Plus 的定制载板上开发 DSI 转 HDMI 变流器 ( ADV7535)。 我们已经替换了 ADV7535 而不是 LT8912B MIPI DSI 转 HDMI 桥接器 ，后者自带 Toradex 载板。我们使用 I2C 通道 2 与 ADV7535 DSI 转 HDMI 桥接器进行 通信，这与使用不同的 I2C 通道的 Yavia 载板不同。因此，我们对设备树进行了以下更新以反映这一变化： 设备树变更 1. verdin-imx8mp_dsi-to-hdmi_overlay.dts 删除现有 hdmi_lontium_lt8912 节点。 在 I2C2 节点下新增 hdmi_adv7535 节点。 2. imx8mp-verdin.dtsi 删除了 hdmi_lontium_lt8912 节点。 从 hdmi_connector 节点中删除了 Lontium 引脚连接细节。 已添加 hdmi_adv7535 作为 I2C2 下的子节点。   更改后的观察结果 成功读写 ADV7535 的内部寄存器。 能够转储 I2C 数据： torizon@verdin-imx8mp-15404184:~$ i2cdump -y -f 1 0x39 No size specified (using byte-data access) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: 14 00 00 00 00 00 00 00 00 00 41 0e bc 18 01 13 ?.........A????? 10: 25 37 00 00 00 00 38 00 46 62 04 a8 00 00 1c 84 %7....8.Fb??..?? 20: 1c bf 04 a8 1e 70 02 1e 00 00 04 a8 08 12 1b ac ?????p??..?????? 30: 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 b0 ...........?...? 40: 00 50 f0 76 10 68 68 68 68 00 80 00 00 00 00 00 .P?v?hhhh.?..... 50: 00 00 02 0d 6d 02 00 00 00 00 00 00 00 00 00 00 ..??m?.......... 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 70: 01 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ??.............. 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 90: 00 00 00 00 c0 00 40 00 03 02 e0 18 30 61 00 00 ....?.@.????0a.. a0: 00 00 a4 a4 08 04 00 00 00 00 00 40 00 00 40 14 ..????.....@..@? b0: 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 ..........?..... c0: 00 00 00 00 00 00 06 00 00 03 00 00 02 00 01 04 ......?..?..?.?? d0: 0c ff 80 80 80 00 00 00 00 00 00 00 00 00 88 01 ?.???.........?? e0: d0 70 01 00 00 00 fd 00 00 00 52 46 00 00 00 00 ?p?...?...RF.... f0: 95 04 ff 00 00 00 00 00 00 00 7d aa 1c 00 b0 00 ??........}??.?. 检测 HDMI 显示器，并在 i.MX8MP 上检索 EDID 数据。HDMI-A -1 是 DSI 转 HDMI 端口，HDMI-A-2 是原生 HDMI 端口。 root@verdin-imx8mp-15288064:/home/torizon# cat /sys/class/drm/card0-HDMI-A-1/edid | edid-decode edid-decode (hex): 00 ff ff ff ff ff ff 00 30 ae 86 10 01 01 01 01 22 15 01 03 80 29 1a 78 ee e5 b5 a3 55 49 99 27 13 50 54 af ef 00 61 40 81 c0 81 80 81 8a 81 90 95 00 95 0f 01 01 64 19 00 40 41 00 26 30 18 88 36 00 a0 1d 00 00 00 18 00 00 00 fc 00 4c 45 4e 20 4c 31 39 35 30 77 44 0a 20 00 00 00 fd 00 32 4c 1e 51 0e 00 0a 20 20 20 20 20 20 00 00 00 ff 00 42 33 34 33 32 38 34 35 0a 20 20 20 20 01 0b 02 03 21 71 4e 06 07 02 03 15 96 11 12 13 04 14 05 1f 90 23 09 07 07 83 01 00 00 65 03 0c 00 10 00 8c 0a d0 90 20 40 31 20 0c 40 55 00 b9 88 21 00 00 18 01 1d 80 18 71 1c 16 20 58 2c 25 00 b9 88 21 00 00 9e 01 1d 80 d0 72 1c 16 20 10 2c 25 80 b9 88 21 00 00 9e 01 1d 00 bc 52 d0 1e 20 b8 28 55 40 b9 88 21 00 00 1e 02 3a 80 d0 72 38 2d 40 10 2c 45 80 b9 88 21 00 00 1e 00 00 00 00 d0   遇到的问题 连接的 HDMI 显示器上没有图像输出 。 dmesg 日志错误：   imx_sec_dsim_drv 32e60000.mipi_dsi: failed to get pmsk for: fin = 12000, fout = 0   故障排除尝试 我们尝试修改设备树中的 MIPI DSI 控制器时钟设置，如下所示： mipi_dsi: mipi_dsi@32e60000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-mipi-dsim"; reg = <0x32e60000 0x10000>; clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK>, <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF>; clock-names = "cfg", "pll-ref"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <11000000>; interrupts = 18 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&mipi_phy1_pd>; status = "disabled"; port@0 { dsim_from_lcdif: endpoint { remote-endpoint = <&lcdif_to_dsim>; }; }; }; 不过，在 dmesg 日志中，默认频率仍显示为 12 MHz 。   要求澄清 我们希望您能就以下几点提供指导： 如何正确更新 fin 和 fout 的值，以解决 pmsk 错误？ 要通过 ADV7535 实现正确的图像输出，是否需要对设备树进行任何其他更改？ 期待您的见解和建议。 请参阅随附的 dmesg 日志，该话题中的设备树叠加层。 谢谢& ， Rupesh Kathar imx8mplus#adv7535 #dsi #hdmi #mipi #i2c #i2s i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: ADV7535: No image output on display 如果您使用的是 5.15，只需将分支更改为 5.15，因为您的源代码是第三方公司的，我不清楚您的驱动程序如何，但请参考 nxp adv7535 驱动程序 linux-imx/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c at lf-5.15.y - nxp-imx/linux-imx - GitHub 并不是所有的分辨率都能支持，有效时钟如下，如果需要新时钟，必须在时钟驱动程序中添加新时钟。 静态常量 int valid_clocks[] = { 148500, 135000, 132000, 108000, 78750, 74250, 65000, 49500, 40000, 31500, }; Re: ADV7535: No image output on display 您好@joanxie, 感谢您对恩智浦内核源代码的指导。 我们已经使我们的设备树与恩智浦内核5.15y（不是你共享的6.12）的imx8mp-evk.dts保持一致，我们的显示器适用于某些分辨率，但不适用于我们的目标分辨率，即1024x768。 除了 adv7535 的设备树外，我们没有做任何其他更改。使用 Toradex 内核 5.15.2.x。 下面的表格列出了哪些方法有效，哪些方法无效。 分辨率 宽高比 标准 常见刷新率 Realtek 显示器 戴尔显示器 640×480 4:3 双向 60 赫兹 工作 工作 800×600 4:3 VESA 60-75 赫兹 工作 工作 1024×768 4:3 VESA 60-75 赫兹 空白/闪烁时 禁用 内部定时发生器 无输出 1280×768 5:3 VESA 60 赫兹 无输出 无输出 1280×720 16:9 双向 24/25/30/50/60 赫兹 工作 工作 1366×768 16:9 VESA 60 赫兹 无输出 无输出 1920×1080p 16:9 双向 24/25/30/50/60 赫兹 工作 工作 只有 1024x768 不工作的可能原因是什么？其他分辨率只需插入 HDMI 即可正常工作。 Re: ADV7535: No image output on display 我之前已经分享过 imx8mp dts 文件，首先，您需要在 dts 中正确设置该桥接器，然后 adv7535 驱动程序就会 https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c Re: ADV7535: No image output on display 嗨 @joanxie， FYR，我们正在使用类似于 Toradex 的 Yavia 载板的定制板。唯一的变化是用 ADV7535 取代了 lontium DSI 转 HDMI 适配器。我们选用 ADV7535，因为恩智浦也在其部分产品中使用该器件。 因此，我们在 Toradex 为 Yavia-WiFi dts 提供的设备树及其父设备树源的基础上进行了设备树修改。 问题中的设备树节点是 1。MIPI-DSI-这里没有修改任何内容（与之前的文章不同，改回了默认值）。其他恩智浦设备也必须使用它。 2。ADV7535 特定的节点和叠加层，我们在上一篇文章中提供了。 驱动程序为sec_mipi_dsim-imx.c，sec-dsim.c,adv7511_drv.c,adv7533.c. 现在，在调整了设备树叠加层之后。我们不再收到 fin、fout 错误。 以下是上述驱动程序的 dev_dbg 日志。 torizon@verdin-imx8mp-15404184:~$ dmesg | grep drm [ 0.000000] Kernel command line: root=LABEL=otaroot rootfstype=ext4 quiet logo.nologo vt.global_cursor_defau lt=0 plymouth.ignore-serial-consoles splash fbcon=map:3 ostree=/ostree/boot.1/torizon/7b778d635701b4e0bbc49652c 421a587ae63ff3c6cbfc07d964084a23df7631d/0 [ 2.771129] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops) [ 2.771181] imx-drm display-subsystem: bound imx-lcdifv3-crtc.1 (ops lcdifv3_crtc_ops) [ 2.772099] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops [sec_mipi_dsim_imx]) [ 2.772141] imx-drm display-subsystem: bound 32fd8000.hdmi (ops dw_hdmi_imx_ops) [ 2.772468] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0 [ 2.869610] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device [ 5.099098] systemd[1]: Starting Load Kernel Module drm... [ 5.188031] systemd[1]: modprobe@drm.service: Deactivated successfully. [ 5.188992] systemd[1]: Finished Load Kernel Module drm. [ 5.262319] [drm] Initialized vivante 1.0.0 20170808 for 40000000.mix_gpu_ml on minor 1 torizon@verdin-imx8mp-15404184:~$ dmesg | grep dsim [ 0.000000] Kernel command line: root=LABEL=otaroot rootfstype=ext4 quiet logo.nologo vt.global_cursor_defau lt=0 plymouth.ignore-serial-consoles splash fbcon=map:3 ostree=/ostree/boot.1/torizon/7b778d635701b4e0bbc49652c 421a587ae63ff3c6cbfc07d964084a23df7631d/0 dy [ 2.759952] Kernel module loaded from ramdisk: sec_dsim - result: 0 [ 2.771246] imx_sec_dsim_drv 32e60000.mipi_dsi: sec-dsim bridge bind begin [ 2.771290] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200 [ 2.772085] imx_sec_dsim_drv 32e60000.mipi_dsi: sec-dsim bridge bind end [ 2.772099] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops [sec_mipi_dsim_imx]) [ 2.916294] Kernel module loaded from ramdisk: sec_mipi_dsim_imx - result: 0 [ 3.259164] imx_sec_dsim_drv 32e60000.mipi_dsi: p: min = 1, max = 6, m: min = 88, max = 1023, s: min = 0, ma x = 5 [ 3.259252] imx_sec_dsim_drv 32e60000.mipi_dsi: fout = 390000, fin = 12000, m = 130, p = 1, s = 2, best_delt a = 0 [ 3.259262] imx_sec_dsim_drv 32e60000.mipi_dsi: no pre-exist hpar can be used [ 18.521539] imx_sec_dsim_drv 32e60000.mipi_dsi: p: min = 1, max = 6, m: min = 88, max = 1023, s: min = 0, ma x = 5 [ 18.521629] imx_sec_dsim_drv 32e60000.mipi_dsi: fout = 390000, fin = 12000, m = 130, p = 1, s = 2, best_delt a = 0 [ 18.521640] imx_sec_dsim_drv 32e60000.mipi_dsi: no pre-exist hpar can be used torizon@verdin-imx8mp-15404184:~$ dmesg | grep adv [ 0.000000] Kernel command line: root=LABEL=otaroot rootfstype=ext4 quiet logo.nologo vt.global_cursor_default=0 plymouth.ignore-serial-consoles splash fbcon=map:3 ostree=/ostree/boot.1/torizon/7b778d635701b4e0bbc49652c421a587ae63ff3c6cbfc07d964084a23df7631d/0 [ 1.052362] adv7511 1-0039: Rev. 20 [ 4.325789] systemd[1]: System time before build time, advancing clock. torizon@verdin-imx8mp-15404184:~$ 有了它，我们还能通过使用 i2cset 直接在 ADV7535 上设置寄存器来生成测试色条图案，这意味着 ADV7535 至 HDMI Sink 显示器的工作正常。问题出在 iMX8MP 与 ADV7535 的通信方式上。 显示屏上仍然没有任何输出。 我们希望了解，恩智浦在其产品中实现 ADV7535 的方式与我们在软件和硬件方法上实现 ADV7535 的方式是否存在差异。 Re: ADV7535: No image output on display 看来这个错误信息是你自己的驱动程序造成的，我在 nxp 驱动程序源代码中没有找到这个信息，而且这个设置也不正确，你无法获得你想要的任何时钟，时钟父频是 24Mhz，如果你设置了 11Mhz，你只能获得 24/2=12Mhz 的时钟、 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <11000000>; 你可以参考恩智浦源代码作为参考，检查你关于 lcdif、mipi dsi 和 adv7535 的设置是否正确 linux-imx/arch/arm64/启动/dts/freescale/imx8mp-evk.dts 位于 lf-6.12.y · nxp-imx/linux-imx · GitHub linux-imx/arch/arm64/启动/dts/freescale/imx8mp.dtsi 位于 lf-6.12.y · nxp-imx/linux-imx · GitHub 参考日志，似乎 pll 设置不正确，pll 驱动程序在 linux-imx/drivers/gpu/drm/imx/sec_mipi_pll_1432x.h at lf-6.12.y - nxp-imx/linux-imx - GitHub 您可以仔细检查