DMA MUX Currently I am using, S32 Platform 3.4 programming environment, RTD is 2.0.0 During my use of DMA I found that the RM module I created does not have a Dma Mux, how to solve this situation. Re: DMA MUX Thank you. Re: DMA MUX Hi @xuanming  The example was implemented using a newer RTD version than the one you are currently working with; therefore, changes were introduced to the driver implementation. As you are working with RTD 2.0.0, you should refer to the Dma_Ip driver. Starting from RTD 3.0.0, the DMAMux Source configuration was moved to the RM module at the MCAL layer, which explains the difference you are observing. Additionally, we recommend updating to the latest RTD version whenever possible. This helps avoid known issues and ensures you benefit from the most recent fixes, enhancements, and improvements. BR, VaneB

i.MX93 M33 Core: How to get System Uptime (sec/nsec) for micro-ROS on Custom Board? Hi everyone, I am currently porting micro-ROS to the Cortex-M33 core of an i.MX93 (MIMX9352) using a custom SOM and the MCUXpresso SDK (v25.06.00).  have successfully established a UART transport and connected to the micro-ROS agent. My nodes and topics are created, but published data appears empty/invalid. After debugging, I’ve realized I need to provide high-resolution timestamps (seconds and nanoseconds) to the micro-ROS client to synchronize with the ROS 2 ecosystem. Screenshots, Debug terminal output, Codes are attached below. Micro-ros agent connection Micro-ros agent connectionMicro-ros agent connectionMicro-ros agent connection ROS Topic listing (Topic is emtpy (data not publishing)) ROS Topic listing (But topic is empty)ROS Topic listing (But topic is empty)ROS Topic listing (But topic is empty) Debug terminal output: Debug Console Init done Past lpuart init and custom trnsport open Past rclc support,node,publisher init Past rclc timer init Past rclc executor init, add_timer Inside while loop RCSOFTCHECK Failed: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 after executor spin Inside while loop RCSOFTCHECK Failed: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 after executor spin Inside while loop RCSOFTCHECK Failed: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 after executor spin The Problem: I am struggling to find a reliable "System Uptime" or "Tick" function in the SDK that provides the precision required for rmw_publisher_publish. I tried using the lptmr driver examples, but the code hangs during LPTMR_Init() My Questions: Is there a recommended SDK API for getting a high-resolution (nsec) monotonic timestamp since boot on the i.MX93 M33? For those who have implemented micro-ROS on i.MX9 series: Did you use a dedicated hardware timer, or is there a standard CMSIS/SDK "GetTime" function I should be using instead? Environment Details: Hardware: Custom i.MX93 SOM + EVB Baseboard Core: Cortex-M331 SDK: 25.06.00 Toolchain: MCUXpresso IDE / VS Code Extension2 Any insights or code snippets for a 64-bit nanosecond counter implementation on this platform would be greatly appreciated! Regards, Anandhu Re: i.MX93 M33 Core: How to get System Uptime (sec/nsec) for micro-ROS on Custom Board? Hi, I have tried the tstmr.c demo program in the SDK example. It's not working as expected, tried in two different boards one custom board and avnet osm93, both of them doesn't gave any output in the terminal. Upon debugging it's the TSTMR related functions are not working, the program's not going past "TSTMR_ReadTimeStamp()". SDK Used : MCUXpresso SDK (v25.06.00).

CSEc Error 我在使用S32K144的CSEc，在BOOT_DEFINE时，何时会返回KEY_INVAILD错误呢？ 希望得到解答，祝每天开心! Re: CSEc Error 你好@小智 我看不出在调用 BOOT_DEFINE 函数时出现这种错误的原因。即使尚未配置 BOOT_MAC_KEY，也可以调用此函数，因此它不需要密钥。 此致， Lukas

S32K3XX的drivers配置 您好，我想请教一下，S32K3XX系列芯片新建设工程，在使用drivers时，每一个driver（1所对应位置的每一种driver类型）对应的配置界面中每一项配置（3所示位置），有没有文档或者教程说明？ 在实际工程应用中，我可以依据哪些资料来进行配置，我每次设置都是看设置项名称猜测其功能，并决定是配置成什么，感觉缺乏官方依据，让我觉得我的每一个设置很没有确定性和依据。 Re: S32K3XX的drivers配置 Hi@Aaron_LL AN13435下面的章节中有各组件的一些描述 并且在官网中有很多外设的配置培训教程，你可以在官网找到这些外设的培训教程。 https://www.nxp.com/products/S32K3

verify serial download port through USB2 on i.MX95-A1 EVK with DDR tool in i.MX config-tools Tested on i.MX95-19x19 EVK wit MX95 A1 version, since MX95 A1 has both USB1 and USB2 enabled as SDP. MX95 B0 will only enable one USB port as SDP, and SDP on USB1 and USB2 will be in different part-number. Need to test with config-tools version 25.03, since 25.06 and above only support MX95-B0.   Requirement: 1. USB2.0 cable with type-A male to type-A male. 2. rework on MX95 EVK: Remove R288 on base board, to disable VBUS output on USB2.(MX95 USB2 act as USB device in SDP mode, PC is USB host)     Connect USB cable from PC to MX95-EVk USB2 and power up MX95-EVK. On PC/laptop, in Window Device Manager, should be able to see new HID device popped up. change the configuration of config-tools, by default MX95 USB1 PID is set(0x015D), modify it to the PID of MX95 USB2(0x015C): =================================== Maybe customer could change the files for their USB2 ID 1. C:\\nxp\\i.MX_CFG_25.03\\bin\\python3\\spsdk\\data\\devices\\mimx9596\\database.yaml vid: 0x1FC9 pid: 0x015D 2. C:\\nxp\\i.MX_CFG_25.03\\bin\\python3\\memtool\\common\\sdp_interface.py "MIMX95": (0x1FC9, 0x015D) =================================== without modifying PID, you will see the following error when running DDR Tools: the test procedure shall also work on MX95-B0 with USB2 as SDP. On MX95, need to modify the configuration of the Config-Tools to run DDR test if the SDP is through USB2. MX95 A1(engineering version, not for production) has both USB1 and USB2 enabled as SDP. MX95 B0 will only enable one USB port as SDP, and SDP on USB1 and USB2 will be in different part-number. i.MX Processors

LPC5536 和 Hyperram 你好 我在 LPC5536JBD100 上配置 FLEXSPI 外设时遇到了难题；hyperram 芯片是 S27KS0642GABHV020。该系统位于自定义板上，我们已经成功地在其中集成了其他功能。 我受到 AN12239 的启发，它适用于不同的处理器，但以一种与我正在使用的芯片非常相似的芯片为例：在我看来，主要区别在于 S27KS0642 的新节点技术，它比应用程序节点中使用的 S27KS0641 更快，但时序图（因此虚拟周期）和命令是相同的。 另一个灵感来源是这篇文章 https://community.nxp.com/t5/MCX-Microcontrollers-Knowledge/MCX-N947-FlexSPI-Connecting-to-HyperRAM-Analysis-and/ta-p/1988799 这与我使用的处理器不同，但解释了配置数据结构中某些字段的含义。 我还看了示例 lpcxpresso55s36_flexspi_octal_polling_transfer 来比较 FlexSPI 配置（知道必须进行某些更改，因为它针对的是闪存设备）。 我的症状是，当我尝试读取供应商 ID 时，函数不返回 kStatus_Success（返回值为 7001）。 我检查了时钟是否已连接： CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 0U, true); /*!< Reset FLEXSPICLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 2U, false); /*!< Set FLEXSPICLKDIV divider to value 2 */ CLOCK_AttachClk(kPLL0_to_FLEXSPI); /*!< Switch FLEXSPI to PLL0 */ 并通过图形用户界面配置了引脚 周波的配置方式为 int config_hr(void) { flexspi_config_t config; uint32_t tempCustomLUT[ARRAY_SIZE(customLUT)] = {0U}; /* Copy LUT information from flash region into RAM region, because flash will be reset and back to single mode; In lately time, LUT table assignment maybe failed after flash reset due to LUT read entry is application's required mode(such as octal DDR mode) and flash is being in single SDR mode, they don't matched. */ memcpy(tempCustomLUT, customLUT, sizeof(tempCustomLUT)); /* Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); /* Init FLEXSPI. */ config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;//kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;//kFLEXSPI_ReadSampleClkExternalInputFromDqsPad; //config.enableSckBDiffOpt = true; //config.enableCombination = true; config.ahbConfig.enableAHBPrefetch = true; config.ahbConfig.enableAHBBufferable = true; config.ahbConfig.enableAHBCachable = true; // config.enableDoze = false; FLEXSPI_Init(EXAMPLE_FLEXSPI, &config); /* Configure RAM settings according to serial RAM feature. */ FLEXSPI_SetFlashConfig(EXAMPLE_FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); /* Update LUT table. */ FLEXSPI_UpdateLUT(EXAMPLE_FLEXSPI, 0, tempCustomLUT, ARRAY_SIZE(customLUT)); /* Do software reset. */ FLEXSPI_SoftwareReset(EXAMPLE_FLEXSPI); return 0; } 我检查过了，即使在读取供应商 ID 的函数中，我们使用的也是 A1 端口 status_t flexspi_hyper_ram_get_id(FLEXSPI_Type *base, uint32_t *vendorId) { flexspi_transfer_t flashXfer; status_t status; uint32_t id; /* Write data */ flashXfer.deviceAddress = 0x0U; flashXfer.port = kFLEXSPI_PortA1; flashXfer.cmdType = kFLEXSPI_Read; flashXfer.SeqNumber = 1; flashXfer.seqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_READREG; flashXfer.data = &id; flashXfer.dataSize = 4; status = FLEXSPI_TransferBlocking(base, &flashXfer); *vendorId = id & 0xffffU; return status; } flexspi_device_config_t 结构的初始化过程如下 flexspi_device_config_t deviceconfig = { .flexspiRootClk = 75000000, /* 75MHZ SPI serial clock */ .isSck2Enabled = false, .flashSize = FLASH_SIZE, .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, .CSInterval = 2, .CSHoldTime = 1, .CSSetupTime = 1, .dataValidTime = 1, .columnspace = 3, .enableWordAddress = true, .AWRSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA, .AWRSeqNumber = 1, .ARDSeqIndex =HYPERRAM_CMD_LUT_SEQ_IDX_READDATA, .ARDSeqNumber = 0, .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 0, .enableWriteMask = true, }; LUT 值为 #define LATENCY (0x04) uint32_t customLUT[20] = { /* Read Data */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READDATA + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* Write Data */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* Read Register */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* Write Register */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, LATENCY), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), }; 这对我来说很有感知，因为我总共使用了 48 个地址位，8 个键盘上有 DDR 模式，命令是正确的。 我是不是漏掉了什么？ Re: LPC5536 and Hyperram 你好 谢谢。 不，我配置了更多引脚，但截图拍得很差：我猜有 8 个数据引脚，一个 RWDS、一个 CS_n 和一对差分时钟引脚。 Re: LPC5536 and Hyperram 你好@img_gabrigob 关于引脚配置 您是否只配置了 5 个数据引脚？ S27KS0642GABHV020 需要 8 个数据引脚。 BR 哈利 Re: LPC5536 and Hyperram 你好 谢谢。我给你回复了，但我想我做错了什么（第一次使用这个社区），回复直接转到了我的原帖。 Re: LPC5536 and Hyperram 你好@img_gabrigob 首先，我认为您可以检查硬件。 探测物理信号（示波器）： 确认 CK 按您预期的速率切换，交易的 CS# 脉冲，当您触发信号 Read-ID 序列时，DQ [7:0]/RWDS 会显示活动。 并将 FlexSPI 串行时钟降低到较低的安全频率（例如20-25 MHz），同时进行调试。 那么我认为您可以参考这个 LUT。 /* Read Register */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_READREG + 2] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), /* Write Register */ [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 1] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06), [4 * HYPERRAM_CMD_LUT_SEQ_IDX_WRITEREG + 2] = FLEXSPI_LUT_SEQ( kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), RT1064 HyperRAM 支持 S27KS0641 和 S27KS0642 - NXP Community BR 哈利 Re: LPC5536 and Hyperram 你好，@Harry_Zhang、 谢谢您！ 我试着查看我的 LUT 与您链接的另一篇文章中用户使用的 LUT 之间是否存在任何差异，但即使在尝试调整延迟等待状态下的假人数量后，我还是遇到了同样的问题。 我不知道我是否在安装 IDE 时配置错误，但在 LPC5536 上，我似乎无法通过 flexspi_config_t 数据结构设置差分时钟（字段 enableSckBDiffOpt 位于禁用的 ifdef 中）。 我们在董事会采取了一些措施。CSN 和 CLK 信号处于激活状态。 我们使用两种压摆率（标准和高）来捕获时钟 时钟频率比我预想的要慢（我想我把它设置为 75MHz，这里是 75/2，而不是 150/2）。 数据和 RWDS 信号稳定在 0V。我们只是在数据信号上看到一个小故障（5 毫微秒）。 我还附上了从图形用户界面输出的 pin_mux 和 clock_config 文件。 请问您还有其他建议吗？ 顺祝商祺！ Re: LPC5536 and Hyperram 您好！ 感谢您的回复 我再次检查了电路图，...我意识到 RESN 不受 FLEXspi 控制，因此我更改了软件，使其上升。 现在控制器可以工作了，我们还将 MCU 上的引脚配置为快速转换速率选项。 例如，这是 RWDS 与 CLK 的对比。 因此，问题在于 LUT 中的延迟值（使用您的链接进行更正）和 RESET。 我还有一些不明白的地方，即使这对这个项目并不重要，但可能对未来的应用有用：从时钟树中的配置来看，我期望 CLK 频率为 75MHz，但我测量的频率为 37.5MHz。 还有其他我错过的时钟分频器吗？ 谢谢！ 顺祝商祺！ 加布里埃尔 Re: LPC5536 and Hyperram 你好@img_gabrigob 您能分享与 HyperRAM 的连接原理图吗？ BR 哈利 Re: LPC5536 and Hyperram 你好@img_gabrigob 根据 LPC55S36 数据表。 时钟频率最高为 50M（DDR 模式）。 /* Flexspi frequency 150MHz / 3 = 50MHz */ CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 0U, true); /*!< Reset FLEXSPICLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivFlexSpiClk, 3U, false); /*!< Set FLEXSPICLKDIV divider to value 3 */ CLOCK_AttachClk(kPLL0_to_FLEXSPI); /*!< Switch FLEXSPI to PLL0 */ BR 哈利

FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同步多线程 (SMT) 是一种先进的处理器微架构功能，它允许独立执行线程更有效地利用超标量 CPU 管道组织。双向超标量流水线中的 SMT 实现以相对较小的增量动态功耗最大化双线程并发性。本次会议重点关注下一代 Power Architecture e200z9 处理器核心中包含的 SMT 功能，以及通过该微架构可实现的改进的性能/功率指标。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 同步多线程 (SMT) 是一种先进的处理器微架构功能，它允许独立执行线程更有效地利用超标量 CPU 管道组织。双向超标量流水线中的 SMT 实现以相对较小的增量动态功耗最大化双线程并发性。本次会议重点关注下一代 Power Architecture e200z9 处理器核心中包含的 SMT 功能，以及通过该微架构可实现的改进的性能/功率指标。 回复：FTF-ACC-F1259 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 新款e200z9什么时候上市？

恩智浦技术日 - 特拉维夫 - 2016年3月22日 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 确保嵌入式系统安全的QorIQ可信功能的概述 Layerscape多核通信处理器的ARM® v8虚拟化 逻辑抽象和资源管理以及Layerscape管理复合体 家庭自动化的低功耗无线连接解决方案 NFC Everywhere - 为您的客户提供新的 NFC 用例 面向新虚拟网络的强大QorIQ多核处理器 面向工业-航空电子-军事-烹饪-蜂窝市场的射频功率解决方案 (L Gauthier) 可扩展多核QorIQ Layerscape处理器 基于 64 位软件环境的可扩展多核 QorIQ Layerscape 处理器，适用于企业、家庭和工业应用 (H Cohen) 可穿戴设备市场解决方案 面向未来网络的QorIQ Layerscape LS2085/88多核通信处理器 QorIQ LS2系列：AIOP、WRIOP、DPAA2 - 高性能数据路径和网络外设接口 VORTIQA智能虚拟化加速软件（IVAS）

FTF-INS-F1277 Automotive integrated circuits are requiring high temperature and high voltage application environments. High temperature and high voltage impose severe constraints on the design of IC interconnect and the materials used in the assembly and packaging processes. The use of fine gauge copper wire bonding has been growing very rapidly in consumer, portable, and industrial electronics. Freescale has made significant inroads in introducing and accelerating the adoption of fine gauge copper wire in the high reliability automotive space. The molding compounds were studied and reformulated to accommodate high voltage up to 65V. This presentation will discuss key learnings in copper wire bonding process and molding compound formulation development, and present an exciting update on Freescale strategy on gold to copper wire conversion. Automotive integrated circuits are requiring high temperature and high voltage application environments. High temperature and high voltage impose severe constraints on the design of IC interconnect and the materials used in the assembly and packaging processes. The use of fine gauge copper wire bonding has been growing very rapidly in consumer, portable, and industrial electronics. Freescale has made significant inroads in introducing and accelerating the adoption of fine gauge copper wire in the high reliability automotive space. The molding compounds were studied and reformulated to accommodate high voltage up to 65V. This presentation will discuss key learnings in copper wire bonding process and molding compound formulation development, and present an exciting update on Freescale strategy on gold to copper wire conversion.

DwFシリコンバレー - 2015-03-26 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> オープニングセッション IoT エンド ノードの概念 設計、ソフトウェア、サービス スマートインダストリー " modifiedtitle="true" title="モータ制御のための効率的な熱管理 ヘルスケア&ウェアラブル " modifiedtitle="true" title="ウェアラブルを市場に投入する:プロトタイプから製品化まで スマートシティ " modifiedtitle="true" title="フリースケール・ワイヤレス・コネクティビティ・ポートフォリオの概要 スマートホームとスマートビルディング i.MX 6シリーズ用のビデオおよび画像コーデックとデータパイプライン 次世代 i.MX アプリケーションプロセッサ上のヘテロジニアスマルチプロセッシング(ARM® Cortex-A® + Cortex-M)の概要 Yocto プロジェクト™と i.MX アプリケーション プロセッサ向けの Linux® ソフトウェア開発 スマートネットワーク QorIQ LS1024A Consumer Network Attached Storage(cNAS)ソリューションによるパーソナル・クラウドの起動 デジタル・ネットワーキングのセキュリティ 101: QorIQ Communications Platform、QorlQ Qonverge Platform、C29x Crypto Coprocessor Family、Layerscape Architecture セキュリティ・エンジンとそのソフトウェア・イネーブルメントの概要 QorIQ T4240通信プロセッサの詳細 QorIQ LSシリーズ・プロセッサを使用した電力効率の設計方法 QorIQ Platformのトラスト・アーキテクチャの概要: ネットワーク・システムおよびネットワーキング・システムへのトラストの追加 Power Architecture®とARM®テクノロジのプログラム・モデルの違い QorIQプロセッシング・プラットフォームにおけるDDRの基礎 Sneak Peak: QorIQプロセッサの新機能 QorIQ通信プラットフォームおよびC29x暗号化コプロセッサ・ファミリ上のOpenSSL QorIQ T102xおよびLS10xxプロセッサを搭載した次世代IEEE® 802.11ac WLANシステム設計 ソフトウェア・デファインド・ネットワーキングとモノのインターネット(IoT)

SynGas OBD 节油器是否合法？真实的深度 SynGas 评论 2026 SynGas 评论：SynGas OBD Fuel Saver 是否合法？这是我在亲自测试之前的第一个问题。2026 年的油价依然居高不下，很多驾驶员都在寻找提高燃油效率的现实方法，而不需要昂贵的汽车改装或复杂的改装系统。 SynGas是一款简单的即插即用设备，可连接到车辆的OBD2端口，并声称通过根据实际驾驶习惯使用汽车的ECU来优化燃油消耗。它的有趣之处在于，它并不承诺立竿见影的神奇效果。取而代之的是，该设备在最初的 150 英里内会经历一个学习阶段，以便更好地了解加速、制动和整体驾驶模式，然后才能更有效地调整燃油优化。 点击此处查看 SynGas 的最新详情和官方信息 2026 年，节油技术已成为一个热门话题，因为人们正在积极寻找经济实惠的方法来降低交通成本。SynGas通过提供即插即用的方法来直接利用这一趋势，而不是昂贵的ECU调整或持续购买燃料添加剂。 那么，SynGas OBD 节油器是否合法？ 根据研究、用户反馈和500英里后的真实驾驶观察，它似乎是真正的OBD2燃料优化设备，而不是另一个随机的互联网花招。然而，现实的期望很重要。这并不神奇，每辆车或每位驾驶员的结果也不尽相同。最大的价值似乎来自于长期的日常使用，尤其是对于通勤者和长时间在路上行驶的驾驶员来说。 点击此处查看 SynGas OBD 节油器的工作原理和当前供应情况：     Re: Is SynGas OBD Fuel Saver Legit? An Honest Depth SynGas Reviews 2026 您的问题似乎与恩智浦 QorIQ 系列（数字网络）处理器无关。 请在正确的社区区块中提交您的问题。

S32K148锁死 S32K148 MCU用J-LINK错刷Flash,再用J-LINK链接发生如下错误，JLINK unsecured已没用,怎么解决？ Connecting ... - Connecting via USB to probe/ programmer device 0 - Probe/ Programmer firmware: J-Link V9 compiled Dec 13 2022 11:14:50 - Probe/ Programmer S/N: 25994751 - Device "S32K148" selected. - Target interface speed: 50 kHz (Fixed) - VTarget = 3.301V - ConfigTargetSettings() start - ConfigTargetSettings() end - Took 305us - InitTarget() start - SWD selected. Executing JTAG -> SWD switching sequence. - Protection bytes in flash at addr. 0x400 - 0x40F indicate that readout protection is set. For debugger connection the device needs to be unsecured. Note: Unsecuring will trigger a mass erase of the internal flash. - Executing default behavior previously saved in the registry. - Device will be unsecured now. - Timeout while unsecuring device. Erase never stops. - InitTarget() end - Took 2.17s - Found SW-DP with ID 0x2BA01477 - DPv0 detected - CoreSight SoC-400 or earlier - Scanning AP map to find all available APs - AP[2]: Stopped AP scan as end of AP map has been reached - AP[0]: AHB-AP (IDR: 0x24770011, ADDR: 0x00000000) - AP[1]: JTAG-AP (IDR: 0x001C0000, ADDR: 0x01000000) - Iterating through AP map to find AHB-AP to use - AP[0]: Skipped. Could not read CPUID register - AP[1]: Skipped. Not an AHB-AP - Attach to CPU failed. Executing connect under reset. Re: S32K148锁死 Hi@dongkuili 首先不见得保证能恢复，因为加密段被你写入了错误持续值，可能并不支持mass erase擦除 可以阅读该文档6. S32K1xx系列MCU芯片锁死(lockup)现象 https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw==&mid=2247485716&idx=1&sn=979631aa2385a4e3c7651ee75ee252b4&chksm=e9124d92de65c484f1cfec7de451958cfd5cf818c46a4f71a7d3dd8a522af229c5a18aad58ff&scene=21#wechat_redirect Re: S32K148锁死 Hi@dongkuili 这和你使用什么软件没关系，按照文章中说的，直接去测试reset管脚的波形来判断是否可能被恢复，不能的话就不要再浪费你的时间了。 Re: S32K148锁死 谢谢回复 仔细看了链接文档和芯片手册，多次尝试还是无法通过mass erase恢复，想用S32FlashTool_v2.3.4，但不支持S32K148,有支持S32K148的S32FlashTool吗？

i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello, I am trying to debug firmware for the Cortex-M33 on an i.MX93 using a Segger J-Link and gdb. I established an SWD connection using the patch from NXP for the J-Link software and can halt the processor, read the registers and memory and so on. My problem is, that resetting the processor does not work. The content of the registers does not change so I assume the reset is ignored: (gdb) monitor regs R0 = 40D000C0, R1 = 2001EFE3, R2 = 40D000C0, R3 = 00000000 R4 = 00000000, R5 = 00000000, R6 = FFFFFFFF, R7 = 2001EEE8 R8 = FFFFFFFF, R9 = FFFFFFFF, R10= 2000F000, R11= 00000000 R12= FFFFFFFF, R13= 2001EEE8, MSP= 2001EEE8, PSP= 00000000 R14(LR) = 0FFE219D, R15(PC) = 0FFE2248 XPSR 49000003, APSR 48000000, EPSR 01000000, IPSR 00000003 CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00 Security extension regs: MSP_S = 2001EEE8, MSPLIM_S = 00000000 PSP_S = 00000000, PSPLIM_S = 00000000 MSP_NS = 00000000, MSPLIM_NS = 00000000 PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000 CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00 CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00 (gdb) monitor reset Resetting target (gdb) monitor regs R0 = 40D000C0, R1 = 2001EFE3, R2 = 40D000C0, R3 = 00000000 R4 = 00000000, R5 = 00000000, R6 = FFFFFFFF, R7 = 2001EEE8 R8 = FFFFFFFF, R9 = FFFFFFFF, R10= 2000F000, R11= 00000000 R12= FFFFFFFF, R13= 2001EEE8, MSP= 2001EEE8, PSP= 00000000 R14(LR) = 0FFE219D, R15(PC) = 0FFE2248 XPSR 49000003, APSR 48000000, EPSR 01000000, IPSR 00000003 CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00 Security extension regs: MSP_S = 2001EEE8, MSPLIM_S = 00000000 PSP_S = 00000000, PSPLIM_S = 00000000 MSP_NS = 00000000, MSPLIM_NS = 00000000 PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000 CONTROL_S 00, FAULTMASK_S 00, BASEPRI_S 00, PRIMASK_S 00 CONTROL_NS 00, FAULTMASK_NS 00, BASEPRI_NS 00, PRIMASK_NS 00 The reset strategy from the J-Link is using SYSRESETREQ and not the reset signal since only the Cortex-M33 core is supposed to be reset. Is it possible that the debug controller does not have the necessary security privileges to write the SYSRESETREQ bit? What is the correct way to perform a reset of the Cortex-M33 using a J-Link? Regards, Malte Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello, Can you also share the details on [email protected]? More than a yer already from this topic, and still same issue. Thanks. Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working It worked in the sense I never lost again the processor, but the execution time was heavily affected, which I don't understand why. Each operation took 10x more the time. Does it make sense to perform a cold reset but have by default some code in the ROM (contrary on what is suggested by NXP to have no SD card) and attach the debugger to what is ongoing and overwrite ram? Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello, Is it possible to use this JLink script? https://kb.segger.com/images/8/86/Example_Reset_CortexM_Normal.JLinkScript It is a standard strategy for CortexM. Kind Regards Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello, Can you please share your solution? I am currently facing the same situation. Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello Krzysztof, as stated above, I did manage to work out a way to reset the Cortex-M33 in an i.MX93 using a J-Link. If that is what you are looking for, I will gladly share the details with you. Just tell me your e-mail address or another way of contacting you directly. Regards, Malte Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hi, I just found this topic and was wondering if someone was finally able to find some reliable solution for working with M33 in separation from A55. Recently I have started creating development environment for upcoming project and pretty quickly got into the same trouble with triggering software reset. It's been some time since the thread was opened, SEGGER now (v8.10) provides software with builtin IMX targets, although still seems not capable of performing single core reset. I did some experiments with SCB (SYSRESETREQ) and SCR registers but just can't achieve anything stable. I had also quickly tested MCUXpresso plugin for VSCode and didn't notice any custom, working reset strategy implementation. Regards, Krzysztof Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hi Malkai, I am very much interested in a solution as I get exactly the same problem. Is it possible to send me your solution or advice? Many thanks. [email protected] Best regards Junshu Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hi Malte That would be much appreciated. My mail is [email protected] Best regards Niels Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hi Niels, no thanks to the NXP support, which is less than helpful, I worked out a solution for this problem. If you tell me your e-mail address or any other way of contacting you directly I will be glad to help you. Kind regards, Malte Kaiser Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @Sanket_Parekh  I'm in the exact same situation as the original author. It appears that the JLink script provided by NXP doesn't actually reset the M33 core, but only halts it. This leaves registers and processor state unchanged and if a fault was encountered, I'm not able to continue debugging properly without resetting the core through Linux first. Is there any way that I can trigger such a reset of the M33 core but using the JLink debugger? Best regards Niels Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello Sanket_Parekh, (1) Where can I get the NXP J-Link script patch for i.MX93 Cortex-M33? (2) According to Segger there is no roadmap yet to support i.MX93 in J-Link. But it make come in Q1/Q2. Is there any other possibilities to debug the Cortex-M33? BR Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @malkai , I hope you are doing well. "What is the procedure intended by NXP to reset the Cortex-M33 core in the i.MX93?" ->The System Reset Controller (SRC) is responsible for the generation of all the system reset signals and boot argument latching. ->Its main functions are as follows: • Deals with all global system reset sources from other modules and generates global system reset. • Responsible for power gating of MIXs (Slices) and their memory low power control. ->The SRC takes the POR_B from the PAD and fuse bits to complete the boot sequence and the GPC low power request to complete the power down/up sequence. Please refer to Chapter 33 System Reset Controller (SRC). https://www.nxp.com/webapp/Download?colCode=IMX93RM Thanks & Regards, Sanket Parekh Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @Sanket_Parekhm, thank you for your reply. However, that information does not help to solve the issue. As you know, the Cortex-M33 core in the i.MX93 has the Armv8-M architecture which does not have a VECTRESET bit in the AIRCR register (see D1.2.3 in https://developer.arm.com/documentation/ddi0553/latest/). So the only available reset request is SYSRESETREQ to which there is no reaction by the Cortex-M33 core nor by the entire system. Why is that? I already looked into the reset strategies used by the J-Link. The thing is, that the patch from NXP replaces these with just halting the CPU, as I told you. And the reset line cannot be used here, since it resets the entire SoC. So, the issue still remains: What is the procedure intended by NXP to reset the Cortex-M33 core in the i.MX93? Thank you and kind regards, Malte Kaiser Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @malkai , I hope you are doing well. ->The Reset selection controls the target device reset operation. All reset options apply to Cortex-M processor-based devices, are available in JTAG and SWD mode, and halt the CPU after the reset. ->Core - performs a reset of the Cortex-M core only by setting the VECTRESET bit. On—chip peripherals are not reset. For some Cortex—M devices, this reset method is the only way they may be reset. However, in most cases, this method is not recommended, because most target applications rely on the reset state of some peripherals (PLL, External memory interface, etc.) and may be confused if they boot up, but the peripherals are already configured. ->ResetPin - J-Link pulls its RESET pin low to reset the core and peripherals. Normally, this causes the CPU RESET pin of the device to go low as well, resulting in a reset of the CPU and peripherals. This reset method will fail if the RESET pin of the target device is not pulled low. Please refer to the section reset strategies in the below link. https://community.nxp.com/ pwmxy87654/attachments/ pwmxy87654/kinetis/28743/1/ UM08001_JLink.pdf Thanks & Regards, Sanket Parekh Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @Sanket_Parekh, thank you for your reply. Unfortunately, that information is not helping to solve my problem. In the meantime, I found out multiple things: 1. The J-Link script provided by NXP in the patch for the i.MX93 does not implement a reset. It replaces resetting the CPU with just halting it. 2. Requesting a reset by manually writing AICR.SYSRESETREQ to 1 through the debugger does not result in a reset of the Cortex-M33 core. So, my original question remains: What possibility exits to reset the Cortex-M33 through a debugger? Thanks and regards, Malte Re: i.MX93: Cortex-M33 Reset using J-Link and SYSRESETREQ not working Hello @malkai, I hope you are doing well. Please refer to this link, It will be helpful. https://community.nxp.com/t5/ i-MX-Processors-Knowledge- Base/All-Boards-JTAG/ta-p/ 1106822 ------------------------------ ------------------------------ ------------------------------ ----------------------------- Note: If this post answers your question, please click the Correct Answer button. ------------------------------ ------------------------------ ------------------------------ ----------------------------- Thanks & Regards, Sanket Parekh

カスタムボードの Yocto BSP の DDR バイナリを置き換えるにはどうすればよいでしょうか? こんにちは、 カスタム ボードの Yocto BSP 内の DDR バイナリを置き換えようとしています。 新しいマシンが作成され、必要なファイルを含むレシピ ddr-firmware のディレクトリもカスタム メタ レイヤーに作成されます。しかし、SRC_URI に新しい値を割り当て、レシピ追加で元の値を削除しても、Bitbake が評価ボードの元のパスを検索するのを止めることはできません。レシピ追加を使用しない場合も、この検索については何も変わりません。 唯一機能する方法は、元のレシピをマスクし、カスタム レイヤーに新しいレシピを作成することです。 しかし、それは好ましい方法ではないと思います。これは、カスタム マシン用に作成された DDR バイナリを使用するのに簡単に実行できるはずです。ここで何が見逃される可能性があるでしょうか? よろしくお願いします！ クレーン Re: How to replace DDR binaries in Yocto BSP for the custom board? はい、うまくいきました。NXP_FIRMWARE_LOCAL_DIR に設定されているフォルダーと正確に一致しないようです。しかし、いずれにせよ、それは機能します。 もう 1 つ質問があります。カスタム レイヤーの .bbappend で NXP-EULA ライセンスを閉じるにはどうすればよいでしょうか? よろしくお願いいたします。 クレーン Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、鶴 ご返信よろしくお願いします。 お客様の DDR にも DDR ファームウェアが含まれている必要があります。Yocto で BSP をビルドするときに、S32G3_LinuxBSP_44.0_User_Manual.pdf を参照して DDR ファームウェアを追加していただけますか。 BR ジョーイ Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、ジョーイ。 ご返信よろしくお願いします。 S32G3で、BSPは「bsp44.0」です。 よろしくお願いいたします。 クレーン Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、クレーン お問い合わせいただきありがとうございます。 使用している BSP のバージョンはどれですか? S32G3 または S32G2 チップを使用していますか? BR ジョーイ Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、クレーン フォルダ(fsl-車載-Yocto-bsp/build_s32g274ardb2/conf)内のlocal.confファイルを変更してみてください。 ACCEPT_FSL_EULA = "1" BR ジョーイ Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、ジョーイ。 .bbappend を追加しようとしましたが機能しませんでしたカスタムボード用。 ERROR: /home/crane/work/yocto/sources/meta-alb/meta-alb-bsp/recipes-bsp/ddr-firmware/ddr-firmware.bb: Unable to get checksum for ddr-firmware SRC_URI entry NXP-EULA: file could not be found The following paths were searched: .bbappendを試してみたLICENSE = "CLOSED"、LIC_FILES_CHKSUM = "" で、SUMMARYのみ、.bbappendも試しませんでした。すべて同じエラーメッセージが表示されます。 元のレシピに基づいてレシピを追加するのではなく、NXP からの元のレシピをマスクしてカスタム レシピを作成するのが、カスタム DDR バイナリを処理する唯一の方法ですか? よろしくお願いいたします。 クレーン Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、クレーン フォルダーに NXP-EULA ファイルを追加しましたか? BR ジョーイ Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、ジョーイ。 このファイルを元のレシピまたはカスタムレシピにコピーしようとしましたが、どちらも機能しません。ファイルは両方の方法で見つかりますが、どちらも以下のエラー メッセージを生成します。 ERROR: No recipes in default available for: /home/crane/work/yocto/sources/meta-crane/recipes-bsp/ddr-firmware/ddr-firmware_%.bbappend 私は NXP の DDR バイナリを使用していないので、NXP によって生成された NXP-EULA を使用するのは意味がないと思います。NXP-EULA のチェックを無効にするのが合理的ですよね? よろしくお願いいたします。 クレーン Re: How to replace DDR binaries in Yocto BSP for the custom board? こんにちは、クレーン ご返信よろしくお願いします。 この問題の根本原因を見つける必要があります。NXPのDDRファームウェアとNXP-EULAファイルを使用するには、YoctoでBSP44をビルドしてみてください。BSP44を正常にビルドできた場合は、DDRファームウェアを交換してから再度ビルドしてみてください。 BR ジョーイ

i.MX RT1042 - 使用 lwIP 时 DTC RAM 溢出，将数据移至 OCRAM 后 DHCP 失败 你好，恩智浦社区、 我正在使用 MCUXpresso SDK 在 i.MX RT1042（Cortex-M7）上开发固件。我的应用程序由多个模块组成，我使用 lwIP 与以太网连接，并启用了 ping 功能。 初始问题 - DTC RAM 溢出 启用 lwIP 后，我发现即使其他内存区域未使用，DTC RAM 也会溢出。以下是该配置的内存使用情况： 内存区域 已用大小 区域大小%已用年龄 ------------------------------------------------------- BOARD_FLASH: 223652 B 8 MB 2.67% Sram_DTC: 141580 B 128 KB 108.02% sram_itc: 0 b 128 kb 0.00% sram_oc: 0 b 256 kb 0.00% board_sdram: 0 b 30 mb 0.00% ncache_region: 0 b 2 mb 0.00% 现阶段，我还需要添加更多的应用模块，但 DTC RAM 已经满了。 尝试的解决方案 - 将数据移至 OCRAM 为了减少 DTC RAM 的使用，我更改了全局数据放置配置，并修改了链接器脚本，将以下部分移入 OCRAM： *(DataQuickAccess) *(NonCacheable.init) *（不可缓存） 更改后，内存映射如下所示： 内存区域 已用大小 区域大小%已用年龄 ------------------------------------------------------- BOARD_FLASH: 223652 B 8 MB 2.67% Sram_DTC： 8KB 128KB 6.25% sram_itc: 0 b 128 kb 0.00% Sram_OC: 133388 B 256 KB 50.88% board_sdram: 0 b 30 mb 0.00% ncache_region: 0 b 2 mb 0.00% 在这种配置下，大多数模块都能正常工作，但 DHCP 无法获取 IP 地址，而以太网链接却能启动，应用程序的其他部分也能继续运行。 问题 对于使用 lwIP + 以太网的应用，在 i.MX RT1042 上处理高 DTC RAM 使用率的建议和正确方法是什么？ 如何决定哪些数据或模块应存放在......？ DTC RAM ITC RAM OCRAM NCACHE 地区 SDRAM 具体到 lwIP，哪些数据结构（pbufs、heap、netif、DMA 缓冲区、堆栈）必须保留在 DTC 或非高速缓存内存中才能正确运行？ 将 lwIP 数据移至 OCRAM 时，DHCP 故障是否与高速缓存一致性、MPU 设置、对齐或非高速缓存要求有关？ 如有任何指导、最佳实践或参考示例，将不胜感激。 顺祝商祺！ i.MX RT105x Re: i.MX RT1042 – DTC RAM overflow with lwIP, DHCP fails after moving data to OCRAM 你好@Dkakadia、 感谢您对 NXP MIMXRT 系列的关注！ DHCP 故障问题很可能与缓存一致性有关。在启用了数据缓存的情况下使用以太网 DMA 时，需要缓存一致性管理。对于 lwIP，当使用 OCRAM 作为主 RAM 时，建议将关键数据结构放在 SRAM_DTC 或其他非高速缓存区域。 您可以参考这位客户的帖子： https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Problem-with-sample-lwip-and-OCRAM/td-p/985330 此外，您可以考虑配置 FlexRAM 以增加 DTCM 空间，而不是将所有内容直接传输到 OCRAM。请参阅此 AN： https://www.nxp.com/docs/en/application-note/AN12077.pdf 致以最诚挚的问候， Gavin Re: i.MX RT1042 – DTC RAM overflow with lwIP, DHCP fails after moving data to OCRAM 你好@Gavin_Jia 感谢您的回复和分享参考。 根据您的建议，我检查了缓存一致性方面的问题，并相应地更新了内存位置。有了这些更改，以太网 + lwIP 协议栈（包括 DHCP）现在可以正常工作了。 在我当前的产品设计中，未填充外部同步动态随机存取存储器(SDRAM)，因此我从项目中移除了所有同步动态随机存取存储器(SDRAM)依赖关系。目前，我已在 OCRAM 中声明了 NCACHE 区域，并小心翼翼地将以太网 DMA 相关缓冲区和 lwIP 关键数据结构放入不可缓存内存中。 但是，随着我继续集成其他模块，我再次开始面临内存压力，主要是在内部 RAM 区域。该应用程序现在包括多个外围设备和中间件，例如： lwIP + 以太网、FlexPWM、SPI、UART、I2C 其他特定应用模块 由此，我想到了几个后续问题： 在使用以太网 + LwIP 和多个外设驱动器的 i.MX RT1042 上运行中等复杂的应用程序，实际上是否需要包括外部同步动态随机存取存储器(SDRAM)，还是应该在仔细放置的情况下完全从内部存储器运行这样的应用程序？ 在内存分区、缓存配置或 FlexRAM 配置方面，我是否可能遗漏了重要步骤或最佳实践，从而无法进一步优化内部内存的使用？ 在非 SDRAM 设计中，推荐的长期策略是什么： 扩展应用功能 管理 lwIP 缓冲区、堆和任务栈 在添加更多模块时防止内存反复溢出 如果不使用同步动态随机存取存储器(SDRAM)，这是否是预期的限制，或者是否建议进一步优化，任何指导都将非常有帮助。 再次感谢您的支持和真知灼见。 致以最诚挚的问候， Daksh Re: i.MX RT1042 – DTC RAM overflow with lwIP, DHCP fails after moving data to OCRAM 此外，当增加任何一个 DTCM/ITCM/OCRAM 超过 128KB 时，都会导致代码出现硬故障，文件中提到可以为任何部分分配更多大小，但要注意总大小，即 512KB。 Re: i.MX RT1042 – DTC RAM overflow with lwIP, DHCP fails after moving data to OCRAM "此外，您可以考虑配置 FlexRAM 以增加 DTCM 空间，而不是将所有内容直接传输到 OCRAM。请参阅此 AN： https://www.nxp.com/docs/en/application-note/AN12077.pdf" 该文件提到 ITCM 或 DTCM 可以配置为 0 KB（另见表 1 中显示的可能静态配置）。 但是，当我将 DTCM 配置为 0 而不增加/增加 ITCM 时，应用程序会崩溃。

S32K388CVB-Q289 Driving PTC21 Dear Team I am using S32K388CVB-Q289, and enabling the FlexCAN_0 along with the TJA1153 CAN0. I am connected a second node on the physical bus for testing porpose. But the FlexCAN_0 gets Ack errors upon transmission When I double check that the TJA1153 transceiver is enabled, I measure pin 5 in J95 But it reads ~2 Volts. And when I change the GPDO85 register between 0 and 1, the voltage read on the pin is not affected. Although I can see that pin is Set high in GPDO85 register, and that the Output driver is enabled in MSCR85 Configuration: Re: S32K388CVB-Q289 Driving PTC21 Hi, to check pin level simply remove J95.5-6 jumper and check MCU (5) and TJA1153 (6) side. Note TJA1153 has VIO connected to VDD_HV_B_PERH (VDD_HV_B 3.3V) using J804, while used MCU pins are on VDD_HV_A (5V) There is no need to drive EN pin, unless user want to switch between TJA1153 modes. Both EN and STB_N are pulled up to VIO by external resistors. STB_N should be driven low by MCU to allow local configuration if device is in Vanilla state. At the end of config TJA1153, STB is put back to Normal mode with EN, STB_N high. If you see message on the bus, but it is not ACKed, most probably it is due to inconsistent CAN bit timing between both nodes. Anyway, ready example for S32K388EVB is posted on  https://community.nxp.com/t5/S32K/Need-MCAL-working-CAN-Configuration-for-S32K388-EVB-bench/m-p/1923345/highlight/true#M38660   BR, Petr Re: S32K388CVB-Q289 Driving PTC21 Thanks for your response. The voltage levels seems now good. EN and nSTB go to high. Still I get Ack errors, with nothing appearing on the bus in my test measurement tool. Is it possible that my transceiver is in Vanilla state, and hence it is not operational till I configure it once? I read the example, but it would be way easier for my current setup to just send the CAN messages from test tool, rather than connecting the transceivers to each other. Can you share with me the initialization sequence, what I should send through CAN for a basic configuration that just send and receive (no security requirements needed)? Re: S32K388CVB-Q289 Driving PTC21 Hi, by default the device is in Vanilla state so must be configured, either from host or remotely. After configuration, the state can be changed, but in examples it is commonly kept in Vanilla state, so init is needed after each power on. If the posted example is working between FlexCAN modules on the board, it should work as well if just single one is connected to your CAN tool. In that example the ID being transmitted is added to the CAN0 transceiver's passlist, other configurations are left as default. You can refer to below example, done in IP level,  for another init sequence. https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K358-FlexCAN-TXRX-ISR-S32DS35-RTD400-500/ta-p/1981987 It expects transceiver in Vanilla state as well and set transceiver's passlist to pass all std and ext ID and do not block any message coming from bus. Finally leaving configuration mode without writing to non-volatile memory nor locking the transceiver (keeping Vanilla). BR, Petr

Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp Hello, I’m trying to establish communication between two Imx95 verdin EVK A1 Silicon version boards, through their Aquantia 10 Gbps interfaces. Both boards are running Debian 12 ( linux kernel 6.12.3) with the aquantia10 G firmware (AQR-G4_v5.6.D-AQR_Marvell_NoSwap_XFI_ID44834_VER2068.cld ) properly installed using the nxp installer (aquantia-firmware-utility/aq_api_2_9_7 at master · nxp-qoriq/aquantia-firmware-utility · GitHub). They are physically connected using a Cat6a Ethernet cable. When I run performance tests using iperf3, I get around 5 Gbps in TCP and 1.2 Gbps in UDP with 0% of loss, even when specifying a target bandwidth of 7 Gbps: # TCP Test iperf3 -s # on the first board iperf3 -c -t 30 # on the second board # UDP Test iperf3 -s iperf3 -c -u -b 7G -t 30 when i try to activate jumbo frame with ip link set dev enp1s0 mtu 9000 but i get an error that i exceded the limit (it’s weird that a 10Gbps interface does not accept jumbo frames) also i tried to to increase the UDP buffer size, but i get the same bitrame the CPU load does not exceed 40% when i run iperf3 in both sides Are there any specific n configurations to apply or additional tools to install in order to reach the maximum throughput (close to 10 Gbps)? is the Aquantia FW version is good? the linux kernel version? the FW installer version??? SOmeone have already tried to use the 10Gbps interface on this Targets??? Regards, Abdelmonaem Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp 1. Try configuring following settings on both of your systems: cpufreq-set -g performance sysctl -w net.core.rmem_max=26214400 sysctl -w net.core.wmem_max=26214400 sysctl -w net.core.netdev_max_backlog=250000 sysctl -w net.ipv4.tcp_rmem='4096 87380 16777216' sysctl -w net.ipv4.tcp_wmem='4096 65536 16777216' 2. If possible use a different reference system as iperf server (e.g. Intel Xeon) 3. iperf3 itself is single-threaded per test stream, try using  -P option: e.g. iperf3 -c -u -b 10G -t 30 -P 6 (6 streams) 4. Check both forward and reverse stream (-R) iperf3 -c 192.168.1.1 -t 10 -b 10G -u -R Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp Hi, Thank you for your feedback, applying your configuration: cpufreq-set -g performance sysctl -w net.core.rmem_max=26214400 sysctl -w net.core.wmem_max=26214400 sysctl -w net.core.netdev_max_backlog=250000 sysctl -w net.ipv4.tcp_rmem='4096 87380 16777216' sysctl -w net.ipv4.tcp_wmem='4096 65536 16777216' Now i'm able to achieve 10Gbps some times 8,8 or 9,8Gbps on emitter side only and with only iperf and not iperf3, on the receiver side i can only achieve 5.59Gbps with 36% of loss frames, could you help to resolve this issue Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp it will be a minor version upgrade to 6.12.49 BTW, you may also want to consider DPDK or AF_XDP for better throughput?  Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp => TCP vs UDP send performance When you are using iperf3 to send TCP packets, each TCP packet is 128KB, and the packet will be fragmented by the LSO feature of ENETC Hardware. So you see higher TCP transfer performance. iperf3 does not enable UDP_SEGMENT when creating UDP sockets. Therefore: - Each UDP packet is approximately MTU-sized (≈1500 bytes). - For the same data size, UDP requires to send many more packets than TCP. More packets → more kernel processing → lower performance compared to TCP with LSO. => Why receive is much lower in comparison to send for TCP? - The TX and RX paths are not symmetrical in the Linux kernel, so the processing time for each RX packet and each TX packet in the kernel is different. Also TCP is using LSO offload in send. - RSC is not enabled by default in kernel; We need to disable TCP timestamp so that the RSC of ENETC can work properly. Currently, the RSC of i.MX95 is disabled by default. a) Enable RSC of i.MX95 (receiver side): ethtool -K eth1 large-receive-offload on b) Disabled TCP timestamp (sender side) : sysctl -w net.ipv4.tcp_timestamps=0 sysctl -p /etc/sysctl.conf After enabling RSC, you will see the TCP performance at receiver side will be increased. Additionally you can try using Jumbo frames to get higher throughput. (Hope you are running latest release). # Change MTU to 9000 on both side ip link set dev eth1 mtu 9000 # Change RX buffer length in the ethernet driver. ethtool -G eth1 rx-buf-len 16384 We can see between 8 to 10 Gbps UDP RX/TX with multi-stream mode. Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp Hi, I'm interested only on UDP for the moment and not TCP and i think that the offload mecanisms are not applicable for UDP I tried to activate the jumbo frames by setting mtu to 9000 but i get an error that i exceeded the limits which is 1500 (im using the kernel version 6.12.3) Regards, Abdelmonaem Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp Ok i will try this and told you what i get, Could you precise the linux kernel version for LF-Q4?? As i told you i'm on 6.12.3 and i cannot go to a superior version because i have a A1 silicon revision, i need to know if i have to upgrade to B0 revision or not Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp The RSC settings will also improve UDP performance. The changes/fixes for Jumbo frames in ENETC should be available in upcoming LF-Q4 release in two weeks.  Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp With i don't have an issue i can go to 10Gbps sometime 9, 8Bps with iperf in parallel flows with only one flow i'm at 5Gbps , but my big issue is the Udp, in mono flow i'm at 2Gbps with no lost frame it's ok, but in parallel flows i'm at 5,5Gbps with 42% of loss Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp i don't think that AF_XDP or DPDK will help to reduce a 46% of loss to 0%, i verified also the IRQ affinty and i can see that on the 10G interface i have 6 IRQ each one is affected to a CPU, and i don't see any CPU load issue during the test, the maximum CPU load for 1 CPU is 40%, i still don't understand why i keep loosing frames , maybe the fact that the kernel version used does not support jumbo frames , did you have any performance tests on the 10G interface in your Side (NXP) i think you should test in your side and see if you have the same issue than mine Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp AF_XDP or DPDK do not use kernel networking stack.  DPDK specially have a different driver and work in userspace only. It is highly optimized for networking and packet processing.  It can provide really fast performance for all IP packets.  you may check it out at;  Chapter 10: https://www.nxp.com/docs/en/reference-manual/RM00293.pdf Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp this test is performed on which silicon revision A1 or B0?? do you confirm that the kernel version used for this test 6.12.49 is applicable only for B0 or could be applicable on A1??? i'm not seeing this kernel version in your bsp delivery, the last one is 6.12.34 https://www.nxp.com/pages/alpha-beta-bsps-for-microprocessors:IMXPRERELEASES Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp The new kernel tree and changes are available at: https://github.com/nxp-imx/linux-imx/commits/lf-6.12.49-2.2.0 A1 support has been dropped from newer LF release.  You have following options; 1.  Just build the kernel independently and replace the kernel only in your build. (It may work)   2. Ask your marketing contact to replace your boards with B0 - so that you can run LF-Q4'2025 release.  Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp Ok got it, but just to be sure, could you do the test with MTU = 1500 at reception side i need to know if you have the same result than me on this new version and also i see on your test you put TX at 1500 and reception at 9000 but this does not change anything it's like you are in 1500 in both side if you need to test jumbo frames you need to be at 9000 in both sides , please redo the tests with following configuration: 1- RX/TX with MTU = 1500 in both sides with mono and muti streams 2- RX/TX with MTU = 9000 in both sides with mono and muti streams thank you in advance Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp i don't understand that frome those lines: Single UDP Stream send (1500 MTU): 2 Gbps(this seems at tx with MTU 1500 in single stream you are at 2Gbps) Multi UDP stream send (1500 MTU): 10 Gbps (this seems at tx with MTU 1500 in multi streams you are at 10Gbps) Single UDP Stream send (9000 MTU): 8.2 Gbps(this seems at tx with MTU 900 in single stream you are at 8.2Gbps) Single UDP Stream receive(9000 MTU): 3.9 Gbps(this seems at Rx with MTU 9000 in single stream you are at 3.9Gbps) Multi UDP Stream receive(9000 MTU): 10Gbps(this seems at Rx with MTU 9000 in Multi streams you are at 2Gbps) for me i don't see : Single UDP Stream receive(1500 MTU) Multi UDP Streams receive(1500 MTU) Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp yes, this how the results were tested. MTU was same on both side in all cases (either both 1500 or both 9000) Re: Imx95 verdin EVK, Aquantia10gbps interface limited on 1.2gbps on udp see attached,  Also note that I am also running it on A1 SOC UBOOT logs: -  U-Boot 2025.04-g8c1de2e1deca (May 09 2025 - 15:29:26 +0000) CPU:   i.MX95 rev1.1 at 1800MHz CPU:   Automotive temperature grade (-40C to 125C) at 30C LM Boot reason: sw, origin: 2, errid: 1 LM shutdown reason: sw, origin: 2, errid: 1 Model: NXP i.MX95 19X19 board DRAM:  15.8 GiB --- SM logs >$ info SM Version = Build 633, Commit c37b26da SM Config = mx95evk, mSel=0 Board = i.MX95 EVK, attr=0x00000000 Silicon = i.MX95 A1 Boot mode = normal Boot device = MMC1 Boot stage = primary Boot set = 1 ECID = 0x6E5F04BA0000000500041D0899123F81 PMIC 0 (0x08) = 0x20, 0x09, 0x10, 0x00, 0x01 PMIC 1 (0x2A) = 0x54, 0x22, 0x00, 0x0B PMIC 2 (0x29) = 0x55, 0x22, 0x00, 0x0A Compiler = gcc 14.2.1 20241119

安装 MCUXpresso IDE 和 SDK（日文博客） 这篇文章怎么样？ NXP 的微控制器软件开发环境MCUXpresso及其SDK均免费提供，任何人都可以轻松安装并立即开始运行示例代码。😃 这篇博客文章将一步一步地向您展示如何安装MCUXpresso IDE和 SDK。 * 在本文中，我们将使用FRDM-MCXA153作为示例板。 我们发布了一段视频，讲解安装步骤。点击此链接观看。   什么是MCUXpresso IDE？ NXP 提供的通用微控制器的各种示例代码旨在MCUXpresso上运行，MCUXpresso 是 NXP 免费提供的软件开发环境。 MCUXpresso 有两个版本：“ MCUXpresso IDE （以下简称 IDE）”和“ MCUXpresso VisualStudio Code （以下简称 VSC）”。IDE 是一个集成了所有功能的应用程序。VSC 是 Microsoft Visual Studio Code 的一个插件。 在本博客中，我们将介绍如何安装 IDE 和 SDK 。 该集成开发环境可在 Windows、macOS 和 Linux 系统上运行，并且在所有操作系统上都可以使用相同的用户界面进行操作。 要尝试在 MCUXpresso 上运行的示例代码，您必须先安装 IDE，然后安装要运行该代码的微控制器/板（目标）的 SDK。 IDE代表集成开发环境，是一款集成开发环境应用程序。该应用程序包含用于编辑源代码的编辑器、编译器和链接器等工具链，以及将代码组织成项目并进行项目管理以及各种设置的软件。 SDK代表软件开发工具包，其中包含每个微控制器芯片所需的驱动程序代码和配置信息。您必须为每个要创建的微控制器芯片或电路板（目标）安装SDK 。 让我们一步一步地学习如何安装这些软件。 本文以 macOS 为例，但使用几乎相同的步骤也可以在 Windows 和 Linux 上进行安装。 登录 nxp.com 要执行以下步骤，您必须先登录nxp.com 。 如果您还没有 nxp.com 帐户，请先注册，然后再登录。 如何注册 MyNXP 账户 安装 MCUXpresso IDE 从MCUXpresso IDE 下载站点下载 IDE 安装程序。此下载需要您在 nxp.com 上注册用户，因此如果您尚未注册，请提前注册。 前往MCUXpresso IDE 下载网站，然后按下“下载”按钮。 页面将滚动并出现一个指向下载页面的链接按钮。点击此“下载”按钮。 点击 MCUXpresso IDE 链接。 使用条款将会显示。如果没有问题，请点击“我同意”按钮。 选择与您的操作系统匹配的安装程序，然后单击链接。 如使用Linux，下载安装程序时请选择文件名末尾带有“.deb.bin”扩展名的文件。如使用Windows，请下载文件名末尾带有“.exe”扩展名的文件。 使用macOS，文件名末尾的扩展名为“.pkg”，但有两种类型：如为M1或更高版本M系列（Arm）处理器的 Mac，请下载“MacOSX-aarch64”；如为配备英特尔CPU的 Mac，请下载“MacOSX-86-64”。 *如果版本号不同，请替换为版本号。 下载完成后，启动安装程序并按照说明完成安装。   安装 SDK   MCUXpresso IDE 启动和工作区 MCUXpresso IDE 安装完成后，启动 MCUXpresso IDE 。 在 macOS 系统中，启动后会询问您要将工作区设置在哪里（在教程视频的 2 分 49 秒左右）。工作区是指您进行工作的文件夹。 默认情况下，将在用户文件夹内的“文档”文件夹内创建一个新文件夹。 * 下图显示了默认设置示例。在本例中，用户名为“demo”，因此路径指定为“/Users/demo/...”。 您可以在用户文件夹内的任何位置创建工作区（文件夹）。在下面的示例中，在用户文件夹内创建了一个名为“mcux”的文件夹，并在该文件夹内创建了一个名为“project0”的工作区。 安装 SDK 启动应用程序后（启动并指定工作区后），将出现如下所示的欢迎屏幕。在此屏幕中，单击“下载并安装 SDK” 。 服务器查询一段时间后，显示界面将如下图所示。在这种默认显示状态下，屏幕的右侧和底部会被隐藏，因此您需要根据需要放大窗口或滚动屏幕。 扩大窗口尺寸以确保显示区域安全 在显示屏右上角的搜索框中输入您正在使用的电路板或微控制器的型号。 这里，我们将以FRDM-MCXA153为例，所以我们输入了“A153”。结果，FRDM-MCXA153 开发板显示为候选产品。 选择 FRDM-MCXA153 板后， “安装”按钮将高亮显示，点击即可。 安装过程中会弹出对话框。 安装完成后，您将返回欢迎界面。 点击标签页的关闭按钮即可关闭此显示。 这将是IDE的默认显示状态。 已安装的 SDK 显示在底部中央窗格的“已安装 SDK”选项卡中。 准备好！ 现在你可以出发了！ 在左上角的“项目资源管理器”中，您可以创建一个新项目，或者从 SDK、GitHub 或下载的项目导入并运行项目。 小知识：如需直接测试电路板的运行 SDK包含示例代码。 到目前为止，我们已经以 FRDM-MCXA153 为例安装了 SDK，所以我们将尝试一下其中包含的示例代码。 首先，使用 USB 数据线将开发板连接到计算机。对于 FRDM-MCXA153，请使用标有“MCU-Link”的 USB 接口（参见照片）。 在 IDE 的左上角窗格中，单击“项目资源管理器”选项卡中的“导入 SDK 示例...” 。 将显示已安装的 SDK，然后单击“下一步>” 。 将显示示例代码列表。 可以在“ driver_examples ”→“ gpio ”→“ gpio_led_output ”中找到闪烁 LED （= 闪烁 L）的示例，因此请按照如下所示的层次结构进行操作，选中相应的复选框，然后按“完成”按钮。 示例代码已导入。 点击蓝色小虫图标（开始调试项目） 。 此时将出现一个选择目标的对话框，请检查显示的电路板信息，然后按“确定”按钮。 代码编译完成后写入微控制器的闪存。然后代码暂停，准备运行。 点击由黄色正方形和绿色三角形组成的图标（继续），即可运行板上的代码。 这段示例代码交替向一个GPIO （通用输入/输出）引脚输出高电平和低电平。该引脚连接到一个红色 LED ，因此 LED会闪烁。 参考资料 教学视频：快来使用MCUXpresso IDE吧！ 相关信息：为 VSC 和 SDK 安装 MCUXpresso（日文博客） 变更历史记录： 2025-05-07：第一版 2025-06-26：新增“登录 nxp.com”部分。 2025-10-28：链接更正 2025年11月10日：链接已更新 2025-11-14：添加了安装程序视频的链接/添加了参考资料部分。 2025年11月18日：在开篇图片和所用电路板上添加了注释。更改了视频链接图片。 2026-03-17：更正了“什么是 MCUXpresso IDE？”部分中的图表。 2026-04-05：添加了“启动 MCUXpresso IDE 和工作区”部分。  ========================= 我们目前无法回复此帖子“评论”部分的评论。 对于由此造成的不便，我们深表歉意。如有任何疑问，请参阅“ NXP技术问题-如何联系我们（日语博客） ”。 （如果您已经是恩智浦的分销商或与恩智浦有合作关系，您可以直接询问负责人。） MCUXpresso IDE 可免费用于 NXP MCX 系列微控制器的软件开发。 此外，我们还提供了可与各种 MCUXpresso IDE 配合使用的示例代码。接下来，我们将介绍 IDE 和 SDK 的安装步骤。 读完本文后，任何人都可以轻松安装开发环境和 SDK ，甚至可以运行示例代码！ 通用微控制器 MCUXpresso MCUXpresso IDE MCX 日本博客

S32G2 IPC通信 NXPコミュニティの親愛なるメンバーの皆様、 私はちょうどNXP S32G2 IPCフレームワークに取り組み始めました。私は次のアプリケーションノートAN13750ています:「S32G2でのマルチコアアプリケーションの有効化 using S32G2 Platform Software Integration」と題し、いくつかの疑問を抱きました。 まず、ドキュメントからの流れを正しく理解しているかどうか 1. IPCを使用してLinuxイメージをビルドし、SDカードを使用してA53コアを起動します。 2. Design Studio を使用して M7 の IPC イメージをビルドし、ブートローダーを使用して M7 を SRAM に読み込みます。ブートローダーはEB Tresosによって提供されます。 3. A53からM7でIP通信を開始します。 上記の理解が正しいことを前提として、 1. デバッガを使用して、デザインスタジオからM7アプリケーションを直接実行できますか。 2. LinuxイメージをA53のSDカードから起動させます。 3. A53 linuxからM7とのIPC通信を開始します。 これは可能ですか?私は今のところEBブートローダーを扱いたくありませんが、プロセス全体についての私の理解が間違っていて、このブートローダーがIPCの機能にとって重要である場合を除きます。どんなコメント/提案も大歓迎です。 PS:アプリケーションノートで使用されている3つのコアではなく、1つのM7コアのみを使用したいです。 最良 ヴィシュヌ Re:S32G2 IPC通信 編集:「Description.txt」

imx-smw ele バックエンドを複数のプロセスで同時に使用する プラットフォーム: iMX8ULP imx-smw: lf-6.6.52-2.2.0 imx-セキュア・エンクレーブ: lf-6.6.52-2.2.0 mbedts の暗号ドライバとして、imx-smw ライブラリによって公開されている PSA 暗号 API を使用しています。HSM ELE で秘密鍵を生成します。私たちのアプリケーションは、mbedtls で秘密鍵を不透明鍵としてロードして使用します。異なるプロセスで実行されている複数のアプリケーションは、同時に同じキーを使用できる必要があります。一例として、HSM でラップされたキーを秘密キーとして使用する Web サーバーが挙げられます。 私たちの知る限り、2 つの異なるプロセスが imx-smw ライブラリを使用して同時に同じキーを使用することはCANません。これは、各プロセスがキーにアクセスするために同じ (ele) キーストア サービスを開く必要があり、HSM ドキュメントに記載されているように、同じキーストアを同時に開くことができないためです。複数のプロセスが同じキーを同時に使用するCASEはサポートされていないようです。 この問題をどうしたら克服CANでしょうか? 考えられる解決策としては、imx-smw ライブラリの上にデーモンを作成し、キーにアクセスするための単一のエントリ ポイントを作成することです。しかし、もしかしたら私たちは何かを見逃しているのかもしれませんし、それに対処する別の方法があるかもしれません。 i.MX8ULP Security Re: use imx-smw ele backend in multiple processes simultaneously こんにちは@GiacomoDS このCASEについては社内チームと相談させていただきますが、その前にNXPについて名を教えていただけますか？プライバシーに関するCASEは、内部チケットを発行することもCAN。ここからアクセスして、NXP サポート プロフェッショナルによる機密のサポートを受けてください。 よろしくお願いします。 Harvey