i.MX93 EQoS Ethernet DMA Reset Failure with LAN8720A PHY (RMII Mode) Hello NXP Team, I am using an i.MX93 SoM with an external LAN8720A PHY in RMII mode. Hardware Configuration Processor: i.MX93 PHY: LAN8720A RMII Interface PHY Address: 0 PHY Reset GPIO configured MAC provides 50 MHz RMII reference clock sue Observed Ethernet interface fails to initialize and the following errors are reported: imx-dwmac 428a0000.ethernet eth1: PHY [stmmac-1:00] driver [SMSC LAN8710/LAN8720] imx-dwmac 428a0000.ethernet: Failed to reset the dma stmmac_hw_setup: DMA engine initialization failed __stmmac_open: Hw setup failed dmsg Response oot@myd-lmx9x:~# dmesg | grep -i eth [ 0.000000] OF: reserved mem: initialized node ethosu_region@B0000000, compatible id shared-dma-pool [ 0.000000] psci: probing for conduit method from DT. [ 0.953397] fec 42890000.ethernet: Invalid MAC address: 00:00:00:00:00:00 [ 0.960228] fec 42890000.ethernet: Using random MAC address: b2:da:68:e1:93:b7 [ 0.970863] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version [ 1.008422] igb: Intel(R) Gigabit Ethernet Network Driver [ 1.071474] usbcore: registered new interface driver kaweth [ 1.082559] usbcore: registered new interface driver cdc_ether [ 1.646174] optee: probing for conduit method. [ 1.744525] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.560730] fec 42890000.ethernet eth0: registered PHC device 0 [ 2.567579] imx-dwmac 428a0000.ethernet: IRQ eth_lpi not found [ 2.573824] imx-dwmac 428a0000.ethernet: User ID: 0x10, Synopsys ID: 0x52 [ 2.580662] imx-dwmac 428a0000.ethernet: DWMAC4/5 [ 2.585448] imx-dwmac 428a0000.ethernet: DMA HW capability register supported [ 2.592568] imx-dwmac 428a0000.ethernet: RX Checksum Offload Engine supported [ 2.599692] imx-dwmac 428a0000.ethernet: TX Checksum insertion supported [ 2.606382] imx-dwmac 428a0000.ethernet: Wake-Up On Lan supported [ 2.612538] imx-dwmac 428a0000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 2.620184] imx-dwmac 428a0000.ethernet: Enabled L3L4 Flow TC (entries=8) [ 2.626958] imx-dwmac 428a0000.ethernet: Enabled RFS Flow TC (entries=10) [ 2.633749] imx-dwmac 428a0000.ethernet: Enabling HW TC (entries=256, max_off=256) [ 2.641316] imx-dwmac 428a0000.ethernet: Using 32/32 bits DMA host/device width [ 5.034969] systemd[1]: /lib/systemd/system/proftpd.service:8: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. [ 9.808139] SMSC LAN8710/LAN8720 42890000.ethernet-1:00: phy_poll_reset failed: -110 [ 9.872078] fec 42890000.ethernet eth0: Unable to connect to phy [ 9.879398] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 10.892065] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) [ 10.900872] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 11.904042] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) [ 12.838630] SMSC LAN8710/LAN8720 42890000.ethernet-1:00: phy_poll_reset failed: -110 [ 12.896039] fec 42890000.ethernet eth0: Unable to connect to phy [ 12.899637] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 13.904038] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) [ 289.712584] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 290.740032] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) [ 322.123525] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 323.104042] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) [ 655.579526] imx-dwmac 428a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 656.612033] imx-dwmac 428a0000.ethernet eth1: __stmmac_open: Cannot attach to PHY (error: -110) Re: i.MX93 EQoS Ethernet DMA Reset Failure with LAN8720A PHY (RMII Mode) Step 1 — isolate EQoS
Temporarily disable FEC:
&fec {
status = "disabled";
};
Then boot and check:
dmesg | grep -Ei "dwmac|stmmac|eqos|mdio|phy|LAN87"
You want to see the PHY under the EQoS/stmmac MDIO bus, not under 42890000.ethernet.
Step 2 — verify MDIO manually
If you have mdio-tool or phytool:
phytool read eth1/0/2
phytool read eth1/0/3
LAN8720A PHY ID should be readable. If reads timeout or return all 0xffff/0x0000, this is hardware/MDIO/reset/clock, not IP stack.
Step 3 — verify clock tree
cat /sys/kernel/debug/clk/clk_summary | grep -Ei "enet|qos"
Also measure the RMII reference clock on the pin. The NXP RMII thread specifically documents the need to generate the expected 50 MHz clock and the DTS update using <100000000>, <50000000>.
Step 4 — check driver patch status
grep -n "RMII_RESET_SPEED\|imx_dwmac_mx93_reset\|fix_soc_reset" \
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
If missing, apply/backport the i.MX93 RMII DMA reset patch. The upstream patch states it addresses i.MX93 reset logic and requires configuring correct interface speed under RMII mode to complete reset. (https://www.spinics.net/lists/netdev/msg894184.html) Re: i.MX93 EQoS Ethernet DMA Reset Failure with LAN8720A PHY (RMII Mode) Here are the changes which need to applied to the standard NXP BSP for i.MX 93 (or in some way also i.MX 91) for network interfaces in
RMII mode
With a reference Clock provided from i.MX to PHY
These are the changes for u-boot (from the NXP git hub), if you go for the mainline u-boot you may see it slightly different, but the principle is the same. Any parameters for the device tree you may find on the web, like "snps,ext-refclk;" fall definitely under the category "Use code from the web carefully".
Such parameters may not be evaluated at all in the u-boot code or in the Linux Kernel (or maybe just for older platforms), so if you want to be sure, start a text search on this parameter and check if it's taken into account.
It could be that with the correct DTB settings both network interfaces work fine in Linux, but on u-boot command prompt just the FEC. For this, check the changes below applied to imx93_evkimx93_evk.c and dwc_eth_qos.c.
uboot-imx/arch/arm/dts/imx93-11x11-evk.dts:
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <ðphy2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <0>; /* adapt to MDIO PHY address on your board */
eee-broken-1000t;
};
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>; /* adapt to MDIO PHY address on your board */
eee-broken-1000t;
};
};
};
pinctrl_eqos: eqosgrp { /* for 10/100 board, drive strength settings tbd */
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0000017E
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x0000017E
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x0000017E
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x0000017E
MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x0000017E
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x0000017E
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x0000017E
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x0000017E
MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x0000017E
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x0000011E
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x0000057E
>;
};
pinctrl_fec: fecgrp { /* for 10/100 board, drive strength settings tbd */
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x0000011E
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x0000011E
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x0000011E
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x0000011E
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x0000011E
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x0000011E
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x0000011E
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x0000011E
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x0000011E
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x0000011E
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x0000051E
>;
};
uboot-imx/arch/arm/dts/imx93.dtsi:
fec: ethernet@42890000 {
compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x42890000 0x10000>;
interrupts = ,
,
,
;
clocks = <&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <100000000>, <250000000>, <50000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
status = "disabled";
};
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = ,
;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
uboot-imx/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi:
&fec {
/* adapt GPIOx y to the actual pin used on your board */
phy-reset-gpios = <&gpiox y GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
ðphy1 {
/* adapt GPIOx y to the actual pin used on your board */
phy-reset-gpios = <&gpiox y GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
Things to consider in imx93_11x11_evk_defconfig:
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
uboot-imx/drivers/net/dwc_eth_qos.c in function eqos_start(struct udevice *dev):
if (ret) {
pr_err("EQOS_DMA_MODE_SWR stuck indicated, continue anyway.\n");
/* ignore this error, comment the goto instruction out */
/* goto err_stop_resets; */
}
uboot-imx/board/freescale/imx93_evkimx93_evk.c:
static int setup_fec(void)
{
/*
There are PHYs which also work with a 25 MHz input clock,
configurable with a pin strapping or over MDIO, so the parameter
could also be ENET_25MHZ)
*/
return set_clk_enet(ENET_50MHZ);
}
static int setup_eqos(void)
{
struct blk_ctrl_wakeupmix_regs *bctrl = (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
u32 *IOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = (u32 *)(IOMUXC_BASE_ADDR + 0xA4);
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TD2_SION (1<<4)
clrbits_le32(&bctrl->enet_clk_sel,
BCTRL_ENET_CLK_SEL_ENET1_TX_CLK_SEL);
clrbits_le32(&bctrl->enet_clk_sel,
BCTRL_ENET_CLK_SEL_ENET_QOS_CLK_TX_CLK_SEL);
/* set INTF as RMII, enable RMII TX clock */
clrsetbits_le32(&bctrl->eqos_gpr,
BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
BCTRL_GPR_ENET_QOS_INTF_SEL_RMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
setbits_le32(&IOMUXC_SW_MUX_CTL_PAD_ENET_TD2,
IOMUXC_SW_MUX_CTL_PAD_ENET_TD2_SION);
/*
There are PHYs which also work with a 25 MHz input clock,
configurable with a pin strapping or over MDIO, so the parameter
could also be ENET_25MHZ)
*/
return set_clk_eqos(ENET_50MHZ);
}
int board_init(void)
{
#ifdef CONFIG_USB_TCPC
setup_typec();
#endif
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
setup_eqos();
board_gpio_init();
return 0;
}
Regards, Bernhard.
Re: i.MX93 EQoS Ethernet DMA Reset Failure with LAN8720A PHY (RMII Mode) This is a tricky one - unfortunately not (yet) described in one of our documents.
The EQOS Ethernet MAC is an IP from a 3rd party and is also used in a chip from ST Microelectronics. That's the reason why you find code for the i.MX in the folder for an ST platform. It seems there is a problem or was a problem with the reset of the DMA in the EQOS IP, but I wasn't able to verify exactly where this was coming from. For the i.MX 93 I found out that it solves the problem to ignore this check, so comment the jump to "err_stop_resets" out:
/drivers/net/dwc_eth_qos.c in function eqos_start
if (ret) {
- pr_err("EQOS_DMA_MODE_SWR stuck\n");
- goto err_stop_resets;
+ pr_err("EQOS_DMA_MODE_SWR stuck indicated, but continue anyway\n");
+ //goto err_stop_resets;
If you see the 50 MHz reference clock on the TD2 pin of the EQOS RMII interface, if you configured the SION bit to feed the clock from the TD2 pad back into the EQOS MAC, then you should be fine.
The FEC should come up with no changes in the source files, just the required adaption in the device tree
I will look for the required configuration of the device tree and the board_init function and post it later here.
Regards, Bernhard.
查看全文
