FS2400 current consumption after wakeup hello expert: my chip is S32K312 and SBC is FS2400 now i need to wake up the chip and the wakeup source is a GPIO falling edge before make S32K312 going to standby ,i set the FS2400 goto LPON mode  /* register M_WU1_EN : filed CAN_WUEN set to wakeup and interrupt(03) */ Sbc_FS24_Ip_WriteRegister(0, SBC_FS24_IP_M_WU1_EN_ADDR, SBC_FS24_IP_M_CAN_WUEN_MASK); /* register M_IOWU_EN : filed WAKE2,WAKE3,HVIO1 set to no wakeup and interrupt(00) */ Sbc_FS24_Ip_WriteRegister(0, SBC_FS24_IP_M_IOWU_EN_ADDR, 0x00); /* register M_CAN : filed CAN MODE set to Transceiver receive only mode */ Sbc_FS24_Ip_WriteRegister(0, SBC_FS24_IP_M_CAN_ADDR, SBC_FS24_IP_M_CAN_MODE_RX_ONLY); /* go to LPON mode */ Sbc_FS24_Ip_WriteRegister(0, SBC_FS24_IP_M_SYS_CFG_ADDR, SBC_FS24_IP_M_GO2LPON_MASK) after wakeup ,i set the SBC goto normal Lpspi_Ip_Init(&Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_SBC_Instance_0); Sbc_FS24_Ip_InitDriver(&Sbc_FS24_Ip_Config); Sbc_FS24_Ip_InitDevice(SBC_FS24_DEVICE_ID); eReturnValue = Sbc_FS24_Ip_CanTrcvSetState(SBC_FS24_DEVICE_ID, SBC_FS24_CANTRCV_STATE_ACTIVE); Sbc_FS24_Ip_WriteRegister(0, SBC_FS24_IP_M_SYS_CFG_ADDR, SBC_FS24_IP_M_GO2NORMAL_MASK); i found the current consumption is 54mA but the POR current consumption is 72mA if i do nothing about the SBC before goto standby ,after wakeup ,the current consumption is same as POR, so i think the sbc status is something wrong ,can you tell me why? Re: FS2400 current consumption after wakeup Hello PINKMAN Good day! Based on the behavior you described, I do not think the FS2400 is necessarily "stuck", but it is very likely that after waking from LPON the SBC is not returning to exactly the same configuration/state as after a POR The datasheet states that waking from LPON returns the device directly to Normal mode through the wake-up sequence. The device does not re-enter INIT state automatically after an LPON wake-up Also, if the device goes in LPON or LPOFF or Fail-safe mode while in INIT state, the device stays in INIT state, which can lead to misconfiguration of the device. It is recommended to read the INIT_S status bit in M_STATUS register before going to LPON or LPOFF mode, and to go only if the device is no longer in INIT state I would capture and compare the following registers in both cases (POR path and LPON-wakeup path): M_STATUS M_SYS_CFG M_CAN M_SYS1_CFG M_REG_CTRL M_IOWU_EN M_WU1_EN I hope this information has helped you, please let me know if you need help with anything else. Have a great day and best of luck. Re: FS2400 current consumption after wakeup hi : RafaR Based on your suggestion, I compared the FS2400 registers during POR and wake-up. I found that during POR, the value of register M_REG_CTRL is 0x04, while after wake-up, the value of register M_REG_CTRL is 0x1304. Based on this finding, I traced it to the function Sbc_FS24_Ip_InitDevice → Sbc_FS24_Ip_OptionalInitSequence → Sbc_FS24_Ip_InitMain, where there is an operation on M_REG_CTRL. However, this function has a prerequisite that SBC_FS24_NORMAL == ePowState. Therefore, during POR, this function can be executed, but during wake-up, GOTONORMAL is executed after Sbc_FS24_Ip_InitDevice, so this function cannot be executed, resulting in a power consumption difference. So I have two questions: 1. Is Sbc_FS24_Ip_InitDevice mandatory? Because I found that even if I do not call it during initialization, CAN message transmission/reception and power supply still work fine. 2. Where does this power consumption difference mainly come from?

imx95 AHAB SGK support Hello, I am working on AHAB secure boot support on i.MX95 and would like to confirm the supported signing-key hierarchy. I understand that some i.MX9 variants, such as i.MX93, currently do not support subordinate signing keys (SGK) for AHAB container signing, and only SRK-based signing is supported, as discussed here: https://community.nxp.com/t5/i-MX-Processors/imx93-AHAB-SGK-support/td-p/2181212 Could you please confirm whether i.MX95 supports signing AHAB boot containers using subordinate keys (SGK), with the SRK certificate carrying the CA flag, or whether the current released ELE firmware supports only direct SRK-based signing? If SGK is supported, could you also clarify whether support depends on the i.MX95 silicon revision, ELE firmware version, AHAB container format, or BSP release?

Scrubbing ECC RAM MCU: S32K148 Driver: RTD 3.0.0 OS: Bare metal With the above MCU, is there a way of 'scrubbing' the ECC SRAM? 'Scrubbing' means that if a correctable error is detected, the SRAM cell is updated with the correct value if the user configures some appropriate registers. Some competing products such as TI Hercules have this feature. Re: Scrubbing ECC RAM Thank you very much for the feedback. Re: Scrubbing ECC RAM S32K1 devices do not support a hardware SRAM scrubbing mechanism that would automatically write corrected data back to memory after a correctable ECC event. A software-based implementation is also not feasible, as single-bit SRAM ECC correction events are not reported by the ERM, so the application cannot identify the affected memory location. While the S32K3 family also does not provide automatic SRAM scrubbing, it does report single-bit ECC events, which gives the application visibility into these errors and enables implementation of more advanced fault-handling strategies.

NXP SR040 Peak Power Consumption Hello, what is the peak power consumption of the SR040? And can I get a breakdown of Tx/Rx/idle? Re: NXP SR040 Peak Power Consumption Hello, Hope you are doing well. Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public. For more information about the chip could you please contact one of our distributors available in the Distributor Network|NXP? Or if you have any direct contact who helped you getting this device, please contact them. If you are looking for information about our UWB products or you are interested in this technology, I would recommend you check these Development Kits and Modules from our Partners (Trimension UWB Partners). In case you are interested in one of these Kits/Modules, you would need to go directly with them to know the process and the support that they can provide them, as the support path for this technology is through them. The documentation and software are distributed by the corresponding UWB Module partner. By selecting a module, you will be guided to our partner’s page where you can access datasheets, application notes, and the required enablement Regards, Ricardo

Dual core communication S32K322 Hi everyone, I have started a dual-core project where both Core 0 and Core 1 are enabled. As a test, I have created an incrementing variable on each core. What is the recommended way to share or transfer this variable data from Core 1 to Core 0 (and vice versa)? Any examples or best practices using shared RAM would be greatly appreciated. microcontroller : NXPS32k322 IDE: S32 Design Studio RTD: v3 Debugger: PEMicro Thanks! Re: Dual core communication S32K322 Hi @db16122 I started working on a dual-core setup and verified that Core 0 and Core 1 are running by using counters. However, my main question is: how do I pass data from Core 1 to Core 0 and vice versa? Do you have an example related to data sharing between cores? Re: Dual core communication S32K322 I would recommend to use Inter-Platform Communication Framework (IPCF) https://www.nxp.com/design/design-center/software/automotive-software-and-tools/inter-platform-communication-framework-ipcf:IPCF Examples and trainings are included. Re: Dual core communication S32K322 How about add two counter for each M7 core? Once the M7 is running, the counter start to count and you can check the value if it is same or not. BTW, what is the purpose to check each core status? for safety reason? Re: Dual core communication S32K322 Hi @davidtosenovjan  According to the demo training, the IPCF Quick Start Guide includes a middleware block and driver, but they are not available in my configuration tool. configuration as in Demo training configuration in my project is there any-other way to share the data between the cores ?

应用程序中读取DCSR寄存器的值引发CPU停滞的问题 我的设备环境是硬件芯片平台B4860搭载ose操作系统，有一个dcsr的地址空间映射类型为SASE: 0xf1100000 - 0xf14fffff 0x00400000 rw-r-- cio ----g- SASE dcsr 我对其中的地址范围:0xf1124fff -- 0xf1125fff中任意一个地址进行解引用的时候引发了CPU停滞，之后由于芯片看门狗超时而复位。这个地址空间范围是4kb大小，我想知道关于这个芯片dcsr寄存器相关的信息。dcsr寄存器的作用是什么呢？它不能够直接访问读取寄存器值吗？

imx8 nano kernel migration for a53 core from 5.15 to 6.18 imx_rproc_kick Hi  I am upgrading my kernel of the A53 core from 5.15 to 6.18 but i am imx_rproc_kick missing. please find the debug messages # dmesg | grep -nE "rpmsg|virtio|remoteproc|imx-rproc|imx_rproc_kick|goodbye|new channel|get [0-9]" 118:[ 0.030048] imx rpmsg driver is registered. 222:[ 1.538994] remoteproc remoteproc0: imx-rproc is available 224:[ 1.544537] remoteproc remoteproc0: attaching to imx-rproc 225:[ 1.555034] rproc-virtio rproc-virtio.1.auto: assigned reserved memory node vdevbuffer@b8400000 226:[ 1.564322] virtio_rpmsg_bus virtio0: rpmsg host is online 227:[ 1.569846] rproc-virtio rproc-virtio.1.auto: registered virtio0 (type 7) 228:[ 1.576689] remoteproc remoteproc0: remote processor imx-rproc is now attached 327:[ 5.860600] imx-rproc imx8mn-cm7: imx_rproc_kick: failed (1, err:-62) Regards Yadunath R

mc9s08qg8 compiler proto type: i have a product using this chip. it is not obsolete. i have the code to compile, from 1980. what i want to do, is update the cs v6.3 code on windows 11. i want to update the product from and evaluation unit to a working unit, to be released to manufacturers of sewing equipment. I have three lines of c code to update the product for production.  HISTORY: BOBBIN SHOW < 1980. displayed prototype of unit at the show and sold 15 copies for $150 each. I developed specialized gate array chips at International Microciruits INC(IMI) to implement functions. WELL, the unit was a single use. I got a patent and I put the  BOBBIN CONTROLLER "BC" away until 1983.  Used the mc9s08qg8 chip to up grade the BC to many more functions. living on welfare, i did not have money to further my business. NOW i took the developed unit out of storage, and being 72 i am trying to finish off the last coding to get the latest functions. i am going to try to sell it big before i die. my last move before i die, i can not loose. If u can not help me further, i am going to TI and use their chips. U have me locked out of your devlopment software. So i got maybe 12 years left, and ur chip is the core of the product. If U R not intersested in this product, i will go to TI. I do not have time to play with you business cycles. I figure if the unit takes off, i can sell 20,000 units. It works better than i tought 43 years ago, So am I in or out. I need the BDM drive for my wiztronics. com board interface and cw 11.1 to finish the final unit off. ALSO, i am still on SS. NO money, only a dream. i can not afford $500 fora P&E USB multilink Universal prgrammer. Maybe u would like to "venture capital" the device. u got the whole c code, which i downloaded to u!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! the ball is in ur court. Re: mc9s08qg8 compiler Hello I give you a suggestion on your other post if it could help you in repairing the BDM driver to use the device in CodeWarrior mc9s08qg8 drivers Could you confirm if you have consulted with Wiztronics about the driver's usage in their boards, do you have any feedback? Best Regards

演示资料上传错误 电源管理IC的功能安全及相关系统注意事项 | NXP 半导体  这个视频里的资料填写的是视频地址，不是资料地址。

S32DS K116编译问题 NXP 工程师，你好！ 我刚开始使用MCSPTE1AK116, 我安装了MCSPTE1AK116-SW；S32K11x_AMMCLIB_RTM_1_1_45_BIN；S32DS-IDE-ARM_2.2.2_D2312；以及FMASTERSW32；我在使用S32DS 导入MCSPTE1AK116_PMSM_FOC_1Sh样例工程并编译，然后把.srec直接复制E盘，并断电重启，使用freemaster连接并运行，可以通讯上，给定速度也可以运行，但是跑一会（几秒钟）就停止，并报PDB0错误。我直接把原始SW下的.srec文件拷贝到E盘，就能正常运行。是我编译的时候哪里设置有误吗？ Re: S32DS K116编译问题 Hi 如果你测试原始文件夹下的.srec可以运行，但你编译后的.srec运行却遇到错误。 那么建议下载较老版本的Automotive Math and Motor Control Library Set for S32K11x试一下。 比如安装MCSPTE1AK116-SW过程中提到的版本S32K11X_AMMCLIB_RTM_1_1_29_BIN MCSPTE1AK116_ReleaseNotes.txt里能看到该项目是基于以下版本开发的： The Development Kit application was built and tested using the following IDE, Drivers and Tools: ===================================================================================== - S32 Design Studio (S32DS) for ARM 2.2 - S32 Software Development Kit (SDK) for S32K1xx 3.0.3 - FreeMASTER 3.1.4.5 请确认S32K1 SDK已经安装了上述3.0.3版本 Best Regards, Robin 回复： S32DS K116编译问题 很奇怪的问题，我使用配套的BLDC_6Steps和PMSM_FOC_2Sh工程直接下载和编译后下载都能正常运行，使用PMSM_FOC_1Sh工程直接下载也可以，就是编译后再下载就不行。

dpaa2_net: FS table with 1 entries full hi creating 1 dpni and dpdmux. on Port 0 creating 2 RXQ . Adding rte_flow as below  memset(&udp_spec, 0, sizeof(udp_spec)); memset(&udp_mask, 0, sizeof(udp_mask)); udp_spec.hdr.dst_port = rte_cpu_to_be_16(udp_port); udp_mask.hdr.dst_port = 0xffff; pattern[0].type = RTE_FLOW_ITEM_TYPE_UDP; pattern[0].spec = &udp_spec; pattern[0].mask = &udp_mask; pattern[1].type = RTE_FLOW_ITEM_TYPE_END; action[0].type = RTE_FLOW_ACTION_TYPE_QUEUE; action[0].conf = &queue; action[1].type = RTE_FLOW_ACTION_TYPE_END; struct rte_flow *flow = rte_flow_create(port_id, &attr, pattern, action, &error); Creating 2 flow on port 0 for RXQ 0 and RXQ 1  create_udp_queue_flow(port_id, 5000, 0); create_udp_queue_flow(port_id, 5001, 1); Getting below error. dpaa2_net: FS table with 1 entries full Re: dpaa2_net: FS table with 1 entries full Hello, The logs and restool output tell a clear story. The DPNI object was provisioned with only 1 fs_entry , which gets consumed by the first flow rule ( UDP 5000 → RXQ 0 ). Any subsequent rte_flow_create() call fails immediately because the hardware FS table has no room left. Port 0 started with 2 RX queues and 7 TX queues UDP port 5000 -> RXQ 0 created dpaa2_net: FS table with 1 entries full dpaa2_net: Failure to create flow, return code (-1) Flow create failed: unknown fslmc: dpaa2_get_qbman_swp(): New Portal 0x17ffebbc0 (2) affined thread - 8602 fslmc: dpaa2_configure_stashing(): Portal= 2 CPU= 1 SDEST= 0 fslmc: DPAA Portal=0x17ffebbc0 (2) is affined for eth rx to thread 8602root@localhost:/home/user# restool dpni info dpni.1 dpni version: 8.2 dpni id: 1 plugged state: plugged endpoint state: 0 endpoint: dpdmux.0.2, link is down link status: 0 - down mac address: ce:8a:4d:82:e7:dc max frame length: 1536 dpni_attr.options value is: 0x80000310 Unrecognized options found... num_queues: 16 num_cgs: 24 num_rx_tcs: 8 num_tx_tcs: 16 mac_entries: 16 vlan_entries: 16 qos_entries: 64 fs_entries: 1 qos_key_size: 56 fs_key_size: 56 10:53 AM     DPAA2 Flow Steering Table Full — Root Cause & Fix The logs and restool output tell a clear story. The DPNI object was provisioned with only 1 fs_entry , which gets consumed by the first flow rule ( UDP 5000 → RXQ 0 ). Any subsequent rte_flow_create() call fails immediately because the hardware FS table has no room left. Root Cause dpaa2_net: FS table with 1 entries full dpaa2_net: Failure to create flow, return code (-1)   Confirmed by restool : fs_entries: 1 ← only 1 hardware flow-steering slot   The DPNI was created (either via DPL or restool dpni create ) without explicitly setting fs-entries , so it defaulted to 1. Fix — Recreate the DPNI with More FS Entries Option 1 — Dynamically via restool (no reflash needed): # Destroy the existing DPNI restool dpni destroy dpni.1 # Recreate it with sufficient FS entries (e.g., 16 or 64) restool dpni create \ --options=DPNI_OPT_HAS_KEY_MASKING \ --num-queues=16 \ --fs-entries=64 \ --num-rx-traffic-classes=8 \ --num-tx-traffic-classes=16 # Re-bind to the DPDMUX endpoint restool dpdmux connect dpdmux.0.2 --endpoint=dpni.X Replace dpni.X with the newly created ID shown after dpni create . Option 2 — Edit the DPL (Data Path Layout) file: Find the dpni@1 object block in your DPL ( .dts / .dpl ) and increase fs_entries : dpni@1 { compatible = "fsl,dpni"; ... fs_entries = <64>; /* was 1, increase as needed */ ... }; Then reload the DPL: restool dprc load dprc.1  Your DPNI already has qos_entries: 64 and qos_key_size: 56 , so the hardware supports it — only the provisioned FS table size was too small. Quick Validation After Fix # Confirm new fs_entries value restool dpni info dpni. | grep fs_entries # Expected: fs_entries: 64 (or whatever you set)   Then retry your DPDK application — the Flow create failed error should be gone.   regards       Re: dpaa2_net: FS table with 1 entries full root@localhost:/home/user# restool dpni info dpni.1 dpni version: 8.2 dpni id: 1 plugged state: plugged endpoint state: 0 endpoint: dpdmux.0.2, link is down link status: 0 - down mac address: ce:8a:4d:82:e7:dc max frame length: 1536 dpni_attr.options value is: 0x80000310 Unrecognized options found... num_queues: 16 num_cgs: 24 num_rx_tcs: 8 num_tx_tcs: 16 mac_entries: 16 vlan_entries: 16 qos_entries: 64 fs_entries: 1 qos_key_size: 56 fs_key_size: 56 Re: dpaa2_net: FS table with 1 entries full ./dpdk-multirxq-sample-prog  -l 1-3 -n 1 --log-level=fslmc,8 --huge-dir /dev/hugepages --proc-type=auto -b fslmc:dpio.16 -b fslmc:dpio.17 -b fslmc:dpio.18 -b fslmc:dpio.19 -b fslmc:dpio.20 -b fslmc:dpio.21 -b fslmc:dpio.22 -b fslmc:dpio.23 -b fslmc:dpmcp.38 -b fslmc:dpmcp.39 EAL: Detected 16 lcore(s) EAL: Detected 1 NUMA nodes EAL: Auto-detected process type: PRIMARY fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) EAL: Multi-process socket /var/run/dpdk/rte/mp_socket fslmc: fslmc_get_container_group(): Container: dprc.2 has VFIO iommu group id = 11 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: **Devargs matched dpmcp.39 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: **Devargs matched dpio.18 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: **Devargs matched dpio.16 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: Skipping invalid device (power) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: **Devargs matched dpio.22 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: **Devargs matched dpio.20 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: **Devargs matched dpio.19 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: **Devargs matched dpmcp.38 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: **Devargs matched dpio.17 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: **Devargs matched dpio.23 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: **Devargs matched dpio.21 fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.16) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.17) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.18) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.19) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.20) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.21) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.22) fslmc: rte_fslmc_parse(): Parsing dev=(dpio.23) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.38) fslmc: rte_fslmc_parse(): Parsing dev=(dpmcp.39) fslmc: FSLMC Bus scan completed fslmc: List of devices scanned on bus: fslmc: dpni.1 fslmc: dpseci.1 fslmc: dpseci.2 fslmc: dpseci.3 fslmc: dpseci.4 fslmc: dpseci.5 fslmc: dpseci.6 fslmc: dpseci.7 fslmc: dpseci.8 fslmc: dpseci.9 fslmc: dpseci.10 fslmc: dpseci.11 fslmc: dpseci.12 fslmc: dpseci.13 fslmc: dpseci.14 fslmc: dpseci.15 fslmc: dpseci.16 fslmc: dpcon.32 fslmc: dpcon.33 fslmc: dpcon.34 fslmc: dpcon.35 fslmc: dpcon.36 fslmc: dpcon.37 fslmc: dpcon.38 fslmc: dpcon.39 fslmc: dpbp.2 fslmc: dpbp.3 fslmc: dpbp.4 fslmc: dpbp.5 fslmc: dpbp.6 fslmc: dpbp.7 fslmc: dpbp.8 fslmc: dpbp.9 fslmc: dpbp.10 fslmc: dpbp.11 fslmc: dpbp.12 fslmc: dpbp.13 fslmc: dpbp.14 fslmc: dpbp.15 fslmc: dpbp.16 fslmc: dpbp.17 fslmc: dpio.16 fslmc: dpio.17 fslmc: dpio.18 fslmc: dpio.19 fslmc: dpio.20 fslmc: dpio.21 fslmc: dpio.22 fslmc: dpio.23 fslmc: dpio.24 fslmc: dpio.25 fslmc: dpio.26 fslmc: dpio.27 fslmc: dpio.28 fslmc: dpio.29 fslmc: dpio.30 fslmc: dpio.31 fslmc: dpci.0 fslmc: dpci.1 fslmc: dpmcp.37 fslmc: dpmcp.38 fslmc: dpmcp.39 fslmc: dpdmai.0 fslmc: dpdmai.1 fslmc: dpdmai.2 fslmc: dpdmai.3 fslmc: dpdmai.4 fslmc: dpdmai.5 fslmc: dpdmai.6 fslmc: dpdmai.7 fslmc: dpdmux.0 fslmc: dprc.2 EAL: Selected IOVA mode 'VA' EAL: No available hugepages reported in hugepages-2048kB EAL: No available hugepages reported in hugepages-32768kB EAL: No available hugepages reported in hugepages-64kB EAL: Probing VFIO support... EAL: VFIO support initialized fslmc: fslmc_get_container_group(): Container: dprc.2 has VFIO iommu group id = 11 fslmc: fslmc_vfio_setup_group(): VFIO Container FD is [0x1B] fslmc: fslmc_map_dma(): --> Map address: 0x140000000, size: 1073741824 fslmc: rte_fslmc_vfio_dmamap(): Installed memory callback handler fslmc: rte_fslmc_vfio_dmamap(): Total 1 segments found. fslmc: Unable to map region (errno = 22) fslmc: dpmcp.38 Blacklisted, skipping fslmc: dpmcp.39 Blacklisted, skipping fslmc: Device (dprc.2) abstracted from VFIO fslmc: Device (dpni.1) abstracted from VFIO fslmc: Device (dpseci.1) abstracted from VFIO fslmc: Device (dpseci.2) abstracted from VFIO fslmc: Device (dpseci.3) abstracted from VFIO fslmc: Device (dpseci.4) abstracted from VFIO fslmc: Device (dpseci.5) abstracted from VFIO fslmc: Device (dpseci.6) abstracted from VFIO fslmc: Device (dpseci.7) abstracted from VFIO fslmc: Device (dpseci.8) abstracted from VFIO fslmc: Device (dpseci.9) abstracted from VFIO fslmc: Device (dpseci.10) abstracted from VFIO fslmc: Device (dpseci.11) abstracted from VFIO fslmc: Device (dpseci.12) abstracted from VFIO fslmc: Device (dpseci.13) abstracted from VFIO fslmc: Device (dpseci.14) abstracted from VFIO fslmc: Device (dpseci.15) abstracted from VFIO fslmc: Device (dpseci.16) abstracted from VFIO fslmc: Device (dpcon.32) abstracted from VFIO fslmc: Device (dpcon.33) abstracted from VFIO fslmc: Device (dpcon.34) abstracted from VFIO fslmc: Device (dpcon.35) abstracted from VFIO fslmc: Device (dpcon.36) abstracted from VFIO fslmc: Device (dpcon.37) abstracted from VFIO fslmc: Device (dpcon.38) abstracted from VFIO fslmc: Device (dpcon.39) abstracted from VFIO fslmc: Device (dpbp.2) abstracted from VFIO fslmc: Device (dpbp.3) abstracted from VFIO fslmc: Device (dpbp.4) abstracted from VFIO fslmc: Device (dpbp.5) abstracted from VFIO fslmc: Device (dpbp.6) abstracted from VFIO fslmc: Device (dpbp.7) abstracted from VFIO fslmc: Device (dpbp.8) abstracted from VFIO fslmc: Device (dpbp.9) abstracted from VFIO fslmc: Device (dpbp.10) abstracted from VFIO fslmc: Device (dpbp.11) abstracted from VFIO fslmc: Device (dpbp.12) abstracted from VFIO fslmc: Device (dpbp.13) abstracted from VFIO fslmc: Device (dpbp.14) abstracted from VFIO fslmc: Device (dpbp.15) abstracted from VFIO fslmc: Device (dpbp.16) abstracted from VFIO fslmc: Device (dpbp.17) abstracted from VFIO fslmc: dpio.16 Blacklisted, skipping fslmc: dpio.17 Blacklisted, skipping fslmc: dpio.18 Blacklisted, skipping fslmc: dpio.19 Blacklisted, skipping fslmc: dpio.20 Blacklisted, skipping fslmc: dpio.21 Blacklisted, skipping fslmc: dpio.22 Blacklisted, skipping fslmc: dpio.23 Blacklisted, skipping fslmc: dpaa2_create_dpio_device(): LX2160 Platform Detected fslmc: Device (dpio.24) abstracted from VFIO fslmc: Device (dpio.25) abstracted from VFIO fslmc: Device (dpio.26) abstracted from VFIO fslmc: Device (dpio.27) abstracted from VFIO fslmc: Device (dpio.28) abstracted from VFIO fslmc: Device (dpio.29) abstracted from VFIO fslmc: Device (dpio.30) abstracted from VFIO fslmc: Device (dpio.31) abstracted from VFIO fslmc: Device (dpci.0) abstracted from VFIO fslmc: Device (dpci.1) abstracted from VFIO fslmc: Device (dpdmai.0) abstracted from VFIO fslmc: Device (dpdmai.1) abstracted from VFIO fslmc: Device (dpdmai.2) abstracted from VFIO fslmc: Device (dpdmai.3) abstracted from VFIO fslmc: Device (dpdmai.4) abstracted from VFIO fslmc: Device (dpdmai.5) abstracted from VFIO fslmc: Device (dpdmai.6) abstracted from VFIO fslmc: Device (dpdmai.7) abstracted from VFIO fslmc: Device (dpdmux.0) abstracted from VFIO PMD: dpni.1: netdev created, connected to dpdmux.0 fslmc: dpaa2_get_qbman_swp(): New Portal 0x17fff3280 (1) affined thread - 8602 fslmc: dpaa2_configure_stashing(): Portal= 1 CPU= 1 SDEST= 0 fslmc: DPAA Portal=0x17fff3280 (1) is affined to thread 8602 Port 0 started with 2 RX queues and 7 TX queues UDP port 5000 -> RXQ 0 created dpaa2_net: FS table with 1 entries full dpaa2_net: Failure to create flow, return code (-1) Flow create failed: unknown fslmc: dpaa2_get_qbman_swp(): New Portal 0x17ffebbc0 (2) affined thread - 8602 fslmc: dpaa2_configure_stashing(): Portal= 2 CPU= 1 SDEST= 0 fslmc: DPAA Portal=0x17ffebbc0 (2) is affined for eth rx to thread 8602

How Can I Watch All Live Events? Hi everyone, I’m a student and I’m trying to find a simple and reliable way to watch live events, sports, news, and other live programs online without getting confused by too many different websites and apps. I’ve heard people mention IPTVGREAT, but I’m not looking to promote any service. I just want to understand my options and find something that is safe, affordable, and easy for a student to use. If you have experience with watching live content online, could you please share some advice? I’d especially appreciate recommendations for legal and reliable options, free services, or affordable platforms that work well on a laptop or phone. Thanks to anyone who can help. I’m just trying to find a practical solution without spending too much as a student.

Clarifications required regarding Fail safe oscillator drift Fault(FS_OSC_DRIFT) Hi Nxp, I have been using FS2613 SBC chip and I found safety requirement (SM48) which is related to Fail safe oscillator drift Fault (FS_OSC_DRIFT). But ASIL level information is not available in reference manual. So, kindly clarify that, this fault comes under either ASIL B/ ASIL D/ QM? Thanks, Sivahari G Re: Clarifications required regarding Fail safe oscillator drift Fault(FS_OSC_DRIFT) Hello Sivahari Good day! The FS_OSC_DRIFT fault (SM48) corresponds to the monitoring of the independent fail-safe oscillator used by the FS26 fail-safe state machine. According to the FS26 Safety Manual, this mechanism is implemented within the ASIL D fail-safe domain. You can find this representation in Figure 8. Safety architecture. I hope this information has helped you, please let me know if you need help with anything else. Have a great day and best of luck.

S32K144W SDK installed but not available when creating a project Hello, I am having the same problem described in this topic. I am working with an S32K144W. My S32 Design Studio version is: S32 Design Studio for S32 Platform Version: 3.6.10 Build id: 260720 When I create a new S32DS Application Project, select the S32K144W processor, and click the SDK button, no SDK is available. The strange thing is that I have already installed the SDK. It does appear in the SDK Management, so apparently the installation was successful. Figure 1 – SDK Management showing that the SDK is installed. However, when I create a new S32DS Application Project and select the S32K144W, the SDK is not available. Figure 2 – S32K144W selected in the New S32DS Application Project wizard. When I click the SDK button, the list is completely empty: Figure 3 – SDK selection window showing no available SDK. I have been looking for a solution to this problem for quite some time. I also followed the official offline installation procedure described here: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-offline-install-S32K3-RTD-4-0-0-in-S32DS-v3-5/ta-p/1968014 However, this did not solve the problem. So, I would like to understand what exactly is required for an SDK to become available in the project creation wizard for the S32K144W. Is there a specific SDK/RTD version that is compatible with S32 Design Studio 3.6.10 and the S32K144W? Is there any additional package or configuration that I need to install? The fact that the SDK appears in SDK Management, but does not appear when creating a project, makes me think that the SDK is installed but is not being recognized as compatible with the selected processor/project. If anyone has already solved this issue with the S32K144W, I would really appreciate it if you could explain the exact steps. Thank you! Re: S32K144W SDK installed but not available when creating a project Solved! I finally found the solution to this issue. Even though the RTD 3.0.0 was already installed and appeared in SDK Management, it was not available when creating a new project. The solution was to install: NXP GCC for Arm Release version 10.2 build 1728 Then, when creating the project, I selected GCC 10.2 as the project's toolchain. After doing this, RTD 3.0.0 appeared correctly as an available SDK option. My environment is: S32 Design Studio for S32 Platform 3.6.10 Build id: 260720 S32K144W RTD 3.0.0 NXP GCC for Arm 10.2 build 1728 So, if someone has the same problem where the SDK appears in SDK Management but does not appear in the project wizard, make sure that the corresponding NXP GCC 10.2 toolchain is installed and selected. This solved the problem for me.

S32K144如何开辟一段内存地址 实现独立变量的存储 恩智浦官方的技术人员你们好 我在开发S32K144芯片的过程中遇到了一个问题 以上述地址说明为例  我想单独开辟出一段地址 来存放一些全局变量 1.可以实现掉电保存 擦除和改写的功能 2.还有在程序运行的过程中还要可以参与逻辑运算 3.在编译生成srec文件后 可以将这段地址内容数据截取出来 我不清楚  将这些变量放在哪个地址段合适 地址分配的编程语法该怎么写  应该怎么改写工程内部的 Linker_files文件夹中的.ld文件 有没有  这方面的参考资料 提供学习 我对  S32K144芯片的开发还存在不懂的地方 对于 Linker_files文件夹中的.ld文件 flash分配  用语法该怎么写  为什么这么写  我还不知道 我想能得到这方面的知识  能有一个官方明确 正确的 语法规范和内部逻辑说明 以提供学习 衷心期待您的回复    万分感谢！ Re: S32K144如何开辟一段内存地址 实现独立变量的存储 Hi@Ni_ 请下次务必使用贵司的邮箱账户进行提问，对于通用邮箱，例如QQ,163,GMAIL等邮箱账户，我们不会优先处理。 我先回答你的第一个问题： 我以RTM版本提供的链接文件为例，其实在该链接文件中已经告知该如何实现划分独立的地址空间用于自定义数据存储。 细看“m_data_2”,其先在MEMORY定义地址空间范围 （这里你可以自己划分内存，例如你可以把m_text再划分为更多的其它自定义空间，注意其实地址和范围） /* Specify the memory areas */ MEMORY { /* Flash */ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0 /* SRAM_L */ m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000 /* SRAM_U */ m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007000 } 其次在SECTIONS中定义：".customSection"，其属于m_data_2。 /* Custom Section Block that can be used to place data at absolute address. */ /* Use __attribute__((section (".customSection"))) to place data here. */ .customSectionBlock ORIGIN(m_data_2) : { __customSection_start__ = .; KEEP(*(.customSection)) /* Keep section even if not referenced. */ __customSection_end__ = .; } > m_data_2 最后使用“customSection”的时候，可在程序中定义变量： __attribute__((section (".customSection"))  unsigned int i = 0; 变量“i”会被放置在“customSection”中，可以通过编译后的xx.map文件来查看变量“i‘所在的地址是否正确。 你的第二个问题是关于掉电保存数据，这个你完全可以通过S32K1的EEPROM实现，可参考该链接文章。 https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw==&mid=2247486584&idx=1&sn=3b8651b928edd19c642b17838a8c75bd&chksm=e91248fede65c1e87214ce913baab45431f816d0bfd0362e00aea1ed4232f200d5ae2720cd71&scene=21#wechat_redirect

Can I use the same IRQ for multi core Hi helper I am using S32K358 multi core. Using Eirq for io interrupt. I have a question: I want core0 use eirq0 and core2 use eirq1 But the two irq channel trigger the same IRQ handler SIUL2_EXT_IRQ_0_7_ISR So there is the problem. If eirq0 and eirq1 both come. The Both core trigger  SIUL2_EXT_IRQ_0_7_ISR. Both core operate the same register. It will be cause bad software expectation.It will clear other non-init channel.   Do I understand OK?   please give me a help. Brs   Re: Can I use the same IRQ for multi core Hello @Licunhao , Your understanding is partially correct. On S32K3 devices, the SIUL2 external interrupt inputs are grouped into interrupt vectors. Therefore, EIRQ0 and EIRQ1 belong to the same interrupt group and are handled by the same grouped interrupt handler, for example SIUL2_EXT_IRQ_0_7_ISR. So, EIRQ0 and EIRQ1 cannot be used as two fully independent interrupt vectors. If the same SIUL2 interrupt group is routed or enabled on more than one core, both cores may enter the same interrupt handler and access the same SIUL2 registers. This can lead to unexpected behavior if the software does not implement proper multicore synchronization and ownership of the SIUL2 interrupt group. However, the SIUL2 interrupt flags are still available per individual EIRQ channel. A correct interrupt handler should check which EIRQ flag is pending and clear only the corresponding flag bit. The status flags should not be cleared globally or with an incorrect mask, otherwise another pending EIRQ flag could be affected. For a multicore application, I would recommend one of these approaches: Assign the whole SIUL2 interrupt group, for example EIRQ0 to EIRQ7, to one core only. This core should handle the grouped ISR and, if needed, notify another core by software or inter-core communication. If you need independent interrupt routing to different cores, use EIRQ channels from different SIUL2 interrupt groups, for example one channel from EIRQ0 to EIRQ7 and another channel from EIRQ8 to EIRQ15, if this is possible with your pin configuration. If both cores must access the same SIUL2 registers, the access must be protected by a proper multicore synchronization mechanism. But in general, a single-owner model for the SIUL2 interrupt group is cleaner and safer. Best regards, Pavel

i.MX8M Plus EXT4-fs error i.MX8M Plus EXT4-fs error  EXT4-fs error (device dm-6): ext4_find_dest_de:2030: inode #228492: block 918033: comm Binder:296_3: bad entry in directory: rec_len is smaller than minimal - offset=0, inode=0, rec_len=0, lblk=0, size=4096 fake=1

ls104x higher version of Linux 6.+ Does NXP officially have a higher version of Linux 6.0 or above for the LS104X chip? Can you provide a download link

OX05B1S GMSL2 camera with MAX96717/MAX96724 on i.MX95 Hi NXP Team, We are testing an OX05B1S GMSL2 camera on an i.MX95 19x19 EVK running Linux. Setup: OX05B1S camera - MAX96717 - GMSL2 - MX95MBDESER01 MAX96724 - i.MX95 The OX03C10 camera supplied with the MX95MBDES10001 kit works with the same deserializer board and is visible using cam -l. However, the OX05B1S camera with MAX96717 is not listed by cam -l. The BSP contains ox05b1s.ko, max96724.ko, max96717_lib.ko, and OX05B1S DTB files. The OX05B1S DTB appears to describe a direct MIPI connection, while the OX03C10 DTB contains the MAX96724 topology. Does NXP provide a reference device tree configuration for this setup? OX05B1S - MAX96717 - MAX96724 - i.MX95 If not, could you please advise what changes are required to use this OX05B1S GMSL2 camera with the MX95MBDESER01 board? Thank you. Best regards, Tharun Re: OX05B1S GMSL2 camera with MAX96717/MAX96724 on i.MX95 Thank you for the clarification. We understand that the current BSP officially supports OX05B1S through the direct MIPI-CSI interface, while MAX96717/MAX96724 SerDes support is provided for OX03C10. We are using an OX05B1S camera module with a MAX96717 serializer connected to the i.MX95 through the MAX96724 deserializer. The GMSL2 link locks successfully, and the MAX96717 is accessible over the remote I2C channel. Is OX05B1S + MAX96717 + MAX96724 currently unsupported by the BSP, meaning that a custom driver/device-tree integration is required? Or is there any reference implementation or patch available for this combination? Re: OX05B1S GMSL2 camera with MAX96717/MAX96724 on i.MX95 current bsp supports  OX05B1S with MIPI_CSI miniSAS connector to connect imx95 board directly, The Omnivision OX03C10 sensor is supported on i.MX 95 using serializer/deserializer solutions from the following vendors: • Analog Devices: MAX96717/MAX96724 • Texas Instruments: DS0UB953/DS0UV960 for more detailed information, pls refer to the chapter 6.1.3 Cameras of reference manual https://www.nxp.com/docs/en/reference-manual/RM00293.pdf

S32K322 could not view registers when an error occurs Hi NXP Technology Team, The current software version of my project will malfunction after running for a period of time. However, when I try to view the registers, I am unable to do so and the simulation has been disconnected. The screenshot from Lautbach is attached below. I have checked that the 3v3 and 1v5 power supplies for the chips are all normal and show no abnormal waveforms. My situation seems to be similar to that of a previous post.@https://community.nxp.com/t5/S32K/S32K3-core-power-down-error-amp-running-bus-error/m-p/1853122 Could you please tell me how to troubleshoot and solve this problem? RTD version is SW32K3_S32M27x_RTD_4.4_4.0.0_P24_D2405, and it is located in the EB Tresos AUTOSAR.