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[i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP Environment & Hardware Setup Processor / Platform: NXP i.MX95 FRDM Board Camera Module: RPI-CAM-MIPI (AR0144 Sensor + AP1302 Onboard ISP) Firmware Used: ap1302_60fps_ar0144_27M_2Lane_awb_tuning.bin (renamed to ap1302_ar0144_single_fw.bin and placed in /lib/firmware/) Issue 1: Pink / Magenta Color Tint from AP1302 ISP I am experiencing a persistent pink / magenta color cast in the decoded images/video streams coming from the AR0144 camera module via the AP1302 ISP. Despite using this tuned firmware file, the decoded frames still exhibit a noticeable pink cast (sample image attached). Is this a known issue with the AR0144 + AP1302 setup? Is there an updated AP1302 firmware binary available to fix this color balance issue? Issue 2: Bypassing AP1302 to Use the i.MX95 Internal NEO ISP The NXP documentation for the RPI-CAM-MIPI camera module states: "The bypassable onboard ISP chip allows it to be used with a wide range of SoCs." Since the i.MX95 features an integrated hardware NEO ISP, we would like to bypass the AP1302 onboard processing and route the RAW Bayer stream from the AR0144 directly into the i.MX95 internal NEO ISP using libcamera and the neo-ipa-uguzzi pipeline handler. Questions for NXP: Is RAW passthrough (bypassing AP1302 hardware processing to feed RAW Bayer directly to the i.MX95 NEO ISP) officially supported on the i.MX95 FRDM board? If yes, could NXP provide the step-by-step configuration required to enable RAW passthrough? How can we acquire or generate the required DTP / YAML tuning files for the AR0144 sensor under the NEO ISP? Does NXP have a pre-calibrated YAML/DTP file available for AR0144 that can be shared? face_detection_input_image.png face_detection_input_image.png Re: [i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP I reproduce this on my imx95 frdm board, doesn't have any color issue, you should set the correctly since you can bring up the camera, just check if your display has any issue or not 1) set the dtb file as imx95-15x15-frdm-ap1302.dtb   2) your firmware is correct 3) use the command gst-launch-1.0 libcamerasrc ! autovideosink joanxie_0-1786086912147.jpeg Re: [i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP Hi, Thank you for testing and providing the feedback on Question 1.  Re: Question 2 — Bypassing AP1302 for the i.MX95 Internal NEO ISP Could you please also address my second question regarding bypassing the onboard AP1302 ISP to utilize the i.MX95's internal NEO ISP? Since the RPI-CAM-MIPI board documentation states that the onboard ISP is bypassable, we want to route the RAW Bayer stream from the AR0144 sensor directly into the i.MX95's internal NEO ISP. Could you please clarify: Is RAW passthrough (bypassing AP1302 hardware ISP processing) supported for the AR0144 on the i.MX95 FRDM board in the Linux 6.12.49_2.2.0 BSP release? Device Tree Changes: What exact Device Tree configuration or overlay is needed to bypass the AP1302 ISP block and capture RAW Bayer frames directly on the MIPI-CSI interface? Tuning & YAML Configuration: Does NXP provide the tuning/DTP configuration files for the AR0144 under the NEO ISP pipeline handler? If available, could you share these files or guide us on how to properly set up libcamera and LIBCAMERA_IPA_MODULE_PATH for this workflow? Thank you for your assistance! Re: [i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP Is RAW passthrough (bypassing AP1302 hardware ISP processing) supported for the AR0144 on the i.MX95 FRDM board in the Linux 6.12.49_2.2.0 BSP release?>couldn't support it as default bsp, you can find the dtb file named ap1302 only Device Tree Changes: What exact Device Tree configuration or overlay is needed to bypass the AP1302 ISP block and capture RAW Bayer frames directly on the MIPI-CSI interface?> refer to the ap1302 dtso file https://github.com/nxp-imx/linux-imx/blob/lf-6.18.y/arch/arm64/boot/dts/freescale/imx95-15x15-frdm-ap1302.dtso isp_en-gpios = <&adp5585_isp 2 GPIO_ACTIVE_HIGH>; this pin is enable ap1302, you can bypass ap1302 by control this pin, hi is for enable, low is for bypass 3.Tuning & YAML Configuration: Does NXP provide the tuning/DTP configuration files for the AR0144 under the NEO ISP pipeline handler? If available, could you share these files or guide us on how to properly set up libcamera and LIBCAMERA_IPA_MODULE_PATH for this workflow? >you can find all of the SW pacakge here https://github.com/nxp-imx-support/imx-camera-sw-pack Re: [i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP Hi, Thank you for the detailed clarification regarding bypass mechanism. Regarding the color issue, I want to clarify that this is not a display or monitor artifact. To be certain, we did not take a photo of the screen; rather, we dumped the raw image/video file directly from the GStreamer pipeline and inspected the saved file on a separate host machine, where the light reddish/magenta pink tint is clearly present in the pixel data. Since we are using the correct DTB (imx95-15x15-frdm-ap1302.dtb) and the official AWB-tuned firmware (ap1302_60fps_ar0144_27M_2Lane_awb_tuning.bin), could you please help us isolate the root cause? Question: Is there a specific test we can run from user space to verify whether this pink tint is caused by a hardware defect in the specific AR0144 camera module unit we have, or if it is a configuration/software issue? Thank you for your continued support! Re: [i.MX95 FRDM] AR0144/AP1302 Pink Tint Issue & Bypassing AP1302 for NXP NEO ISP Hi @joanxie ,  1) As I mentioned earlier we have confirmed this is NOT a display issue. Because the images are dumped to a file and pulled to a host PC (Not a capture from the Display) 2) We have checked the same camera on IMX 95 EVK and IMX 95 FRDM baord, just to confirm that the problem is with the camera module or not. Both the places we are able to see the red tint. 3) We are using this firmware for ap1302: https://github.com/ONSemiconductor/ap1302_binaries/blob/main/NXP_i.MX93/ap1302_60fps_ar0144_27M_2Lane_awb_tuning.bin And placing this in /lib/firmware with a name "ap1302_ar0144_single_fw.bin" (as we saw this is file name from dmesg logs).  Can you confirm whether you are using the same firmware. If not could you please let us know from where we can get the proper firmware 4) Is there any way to identify whether it's a tuning, firmware problem . Or some hardware issue with the specific module we are having? If it is hardware issue we want to consider buying another fresh unit
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i.MX 8QXP - LPDDR4 memory compatibility guide Hi Team, We are planning for an alternate for the LPDDR4 for the IMX8QXP. Please let me know if there is any updated list for the compatible LPDDR4 parts. i.MX 8/8X/8XLite - LPDDR4 and DDR3L memory compatibility guide Thanks and regards, Rohith Re: i.MX 8QXP - LPDDR4 memory compatibility guide Hi, Thank you for your interest in NXP Semiconductor products, The list was updated this year, that would be the last compatibility guide. Are you planning to use another memory? Regards Re: i.MX 8QXP - LPDDR4 memory compatibility guide Hi Joseph, We are planning to use a different LPDDR4 due to the lead time and other reasons. Whether NXP will support for validating the Memory? And what is the procedure for validating new memory from NXP side Thanks and regards, Rohith 
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S32K118 VLPS: I/O retention in the low power mode, plus SIRCSTEN and VLPSA queries Hi, We have VLPS entry and pin wake-up working on the S32K118, verified standalone with no debugger attached: four consecutive clean sleep/wake cycles, SMC_PMCTRL[VLPSA] clear on each, and SMC_PMSTAT confirming VLPR immediately before each WFI. So this is not a question about VLPS failing to work - it is about current consumption during a sleep that is working correctly. Setup: MCU: S32K118, 48-pin LQFP Board: S32K118EVB-Q048 (SCH-47530 Rev A1) Tools: S32 Design Studio 3.6.8, GCC 11.4 Issue: GPIO output state is retained through VLPS, and a driven RGB LED consumes current for the entire sleep. The on-board RGB LED is connected to PTD15 (green), PTD16 (red) and PTE8 (blue) through series resistors. What we observed: Our application drives the RGB LED from a periodic task while running. When the device enters VLPS, whatever level the LED pins were last driven to is still being driven for the whole time the device is asleep. The core is stopped, the clocks are gated, nothing in software is running - but the LED stays lit and keeps sourcing current until the device wakes. The effect on consumption is large. A single lit LED channel draws several milliamps through its series resistor, which is far above the VLPS current specified for this device and dominates the total completely. Our first supply-current measurements at J15 showed no meaningful drop between RUN and VLPS, and the retained LED state turned out to be the entire reason. The failure is silent. There is no flag, no error, and no difference in any status register between a sleep with the LED off and a sleep with the LED lit. The only symptom is that the low-power mode appears not to save any power, which is easily mistaken for VLPS not being entered at all. It cost us a significant amount of investigation time before we identified the cause. Questions: (a) Is this retention of GPIO output state through VLPS the intended behaviour of the device? (b) Is there any configuration on S32K118 that changes it, or must the application drive every pin to its intended sleep state before entry? (c) Is there recommended practice for configuring digital I/O prior to low-power entry - in particular pull-up/pull-down settings on pins tied to external switches or transceivers, where a retained pull is a continuous leakage path for the duration of the sleep? (d) Under what I/O configuration are the specified VLPS current figures for this device measured? Without knowing that, the specified figure cannot be compared against a measurement on a real board. (e) Are there any pins whose retained state can affect VLPS entry itself, or the wake-up path? deep sleep would put the I/O into an inactive state and the LED would go off by itself, since the core is stopped and all the clocks are gated. That is not what we see - the LED stays lit for the whole sleep at full brightness. Please confirm whether the LED is expected to remain lit in VLPS, and if so, whether there is any device setting that makes the output pins go inactive on low-power entry rather than holding their last driven level. Thanks Re: S32K118 VLPS: I/O retention in the low power mode, plus SIRCSTEN and VLPSA queries Hello @autouser, a) Yes. All I/Os are retained upon entering VLPS:  Julin_AragnM_1-1786054875339.png b) It is up to the application to set the required pins to the intended state before entering VLPS. c) This is application dependent. But, if you have unused pins, you can refer to HW Design Guidelines chapter 8 (unused pins).  "For unused digital and analog pins, the pin function should be set to DISABLED by setting the correspondingPORTx_PCRn[MUX] field to 0b000. The DISABLED function is default state for all pins not initialized. For pins with ADC functionality software should not trigger ADC channel conversion on the channel which is multiplexed with the unused pin.” If they are configured as inputs, they should not be left floating, pulled to either VSS or VDD externally or internally (application-dependent). You can also refer to the S32K3 Low Power Management documentation; chapter 10 provides some HW considerations which apply to general MCU power consumption: Julin_AragnM_2-1786055927609.png d) Table 4.7 (Power consumption) from S32K1xx Data Sheet shows power consumption defined in the attached S32K1xx_Power_Modes_Configuration.xlsx: Julin_AragnM_3-1786056046103.png Last row of the attachment shows which IOs were enabled at measurement. Also, foot note 1 mentions: "All output pins are floating, and On-chip pulldown is enabled for all unused input pins." e) Other than the configured wake-up pins, which will either wake the device immediately if asserted, I cannot think of ones which may affect VLPS entry/exit. Best regards, Julián
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KE18F512VLH16 ECC Memory Cell Autocorrection It's understood that the HW provides automatic correction of single bit ECC errors. However, it's unclear where the corrections are being made. When the hardware autocorrects a single bit ECC error, does it correct on both the read out and the memory cell, or just on the read out? From the AN5335 example figure, is the Read-out Data being corrected from 0->1? That would mean we need to write back the corrected value to RAM to actually clear it within the memory cell. sean_dvorscak_0-1786035276314.png We are concerned if the data in the RAM memory cell is not corrected, a single bit error could degrade to a double bit error. Re: KE18F512VLH16 ECC Memory Cell Autocorrection Hello @sean_dvorscak  1. "When the hardware autocorrects a single bit ECC error, does it correct on both the read out and the memory cell, or just on the read out?" ->>The correction is performed only on readout; the SRAM cell contents are not written back. 2. "We are concerned if the data in the RAM memory cell is not corrected, a single bit error could degrade to a double bit error." ->>Yes, if you want to clear errors in the memory cells and prevent error accumulation, it is recommended that the software perform a read-correct-writeback operation. Thank you. BR Alice
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How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Hi everyone, I am working on an S32K3 MCU using the Green Hills Software (GHS) compiler, and I am implementing a DumpCallStack function. To obtain the frame pointer (FP), I am using the following inline assembly: __asm volatile ("mov %0, r7" : "=r" (locals.fp)); However, the value I get for locals.fp is 0x02B1, which does not appear to be a valid frame pointer. It is not aligned and does not point to a valid stack location, so the call stack cannot be unwound correctly. My questions are: What is the correct way to obtain the current frame pointer when using the GHS compiler on the S32K3 (Arm Cortex-M7)? Does the GHS compiler always use R7 as the frame pointer, or can it omit the frame pointer or use another register depending on the optimization level? Are there any compiler options that must be enabled to preserve the frame pointer for stack unwinding? Is there a recommended GHS-specific API or intrinsic for retrieving the frame pointer instead of using inline assembly? If anyone has implemented stack unwinding or a DumpCallStack function with the GHS compiler on S32K3, I would appreciate any guidance or examples. Thank you! Re: How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Hi, I would not assume that R7 is always used as the frame pointer. Depending on the GHS version, optimization level, and compiler options, the compiler may use a different register or omit the frame pointer entirely and use R7 as a general-purpose register. The value 0x02B1 suggests that R7 might not be acting as a frame pointer in your build.  Please check the generated assembly and verify whether GHS is creating frame records at all. If frame pointers are enabled, you should see a consistent function prologue saving/restoring the frame pointer; otherwise stack unwinding based on R7/R11 will not be reliable. Since this is primarily a compiler-specific question, I would also recommend contacting Green Hills Software support. They can advise on: Whether GHS uses R7, R11, or another register as the frame pointer for your target/configuration. Which compiler options preserve frame pointers. Whether there is a recommended intrinsic or API for obtaining the current frame pointer. Preferred methods for implementing call stack unwinding with GHS. They are best positioned to provide guidance specific to your compiler version and settings. BR, Petr Re: How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Sure
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S32K3 Request to support always-on LPI2C Pin Low Timeout monitoring after transfer completion Hi,NXP We attempted to leverage the I2C_MASTER_EVENT_PIN_LOW_TIMEOUT event to implement recovery for a slave device that holds SDA low. During testing, we observed that the pin-low timeout interrupt is turned off once a transfer completes or an abnormal condition is detected. 企业微信截图_17859835472427.png Our expectation is that this interrupt should remain enabled continuously, since real-time monitoring of the bus is required and the timeout interrupt enable must not be cleared at the end of a transfer. We consider the current RTD 7.0.1 handling of the timeout interrupt to be flawed. Could NXP provide an official recommendation or guidance on how to correctly handle this? Best Regards, xianlong Re: S32K3 Request to support always-on LPI2C Pin Low Timeout monitoring after transfer completion Hello @wuxianlong , Thank you for the detailed description and for pointing to the driver code. Your observation is correct: in the current RTD implementation, LPI2C_IP_MASTER_PIN_LOW_TIMEOUT_INT is enabled as part of the master transfer interrupt handling and it is disabled again when the master transfer is ended. This means that the RTD driver does not keep this interrupt enabled as a permanent bus-monitoring mechanism after transfer completion. From the hardware point of view, the S32K3 LPI2C module supports the pin-low timeout feature. The timeout threshold is configured by MCFGR3[PINLOW], and the MSR[PLTF] flag can be set when the selected SCL or SDA line remains low longer than the configured threshold. The reference manual also states that this flag can be set even when the LPI2C controller is idle. However, this hardware capability does not necessarily mean that the RTD driver keeps the corresponding interrupt enabled continuously. The current RTD implementation appears to manage this event in the context of an active master transfer. For continuous I2C bus monitoring after transfer completion, the recommended approach is to handle this at the application level, for example by checking the MSR[PLTF] status as part of the bus recovery logic. Please also note that the pin-low condition itself must be resolved by software. The PLTF flag cannot be cleared while the low condition is still present, and it must be cleared before a new START condition can be generated. Best regards, Pavel
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Ara240 Module Bring-Up on FRDM-IMX95-PRO Getting Started Video: (function() { var wrapper = document.getElementById('lia-vid-6403214335112w960h540r398'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) This guide provides step-by-step instructions on how to verify successful communication and the runtime software environment to interface with the Ara240 module with the FRDM i.MX 95 Pro development board. Out of the Box: Get Familiar with the Ara240 Module Ara240 Module [Back view]Ara240 Module [Back view] Ara240 Module [Top view]Ara240 Module [Top view]         Connecting the M.2 Module This section explains how to connect Ara240, a discrete module, to the FRDM i.MX 95 Pro development board. The instructions in the FRDM i.MX 95 Pro Getting Start Guide will walk you through the boot-up process for the pre-loaded Embedded Linux image on the board and how to connect the USB debug cable. For additional details, see the official FRDM i.MX 95 Pro Development Board documentation. References: FRDM i.MX 95 Pro Quick Start Guide FRDM i.MX 95 Pro Development Board product page  FRDM i.MX 95 Pro Getting started page Getting Started with ARA2-M2-16G-GT Follow the steps below to connect the Ara240 module to the FRDM i.MX 95 Pro development board: Spoiler (Highlight to read) Important: Ensure the board is powered off before making any connections. Important: Ensure the board is powered off before making any connections. Insert the Ara240 module into the M.2 Key-M socket on the FRDM i.MX 95 Pro development board. Using the screw provided, secure the module. Connect the fan cable to the board’s fan header (refer to the FRDM i.MX 95 Pro board documentation for the exact header location). "How to connect two Ara240 devices?" The figure below illustrates the connection of Ara240 devices to the two M.2 Key-M slots on the FRDM i.MX 95 Pro development board. You can install one Ara240 device in either slot or connect two devices simultaneously by using both slots. Connect the Ara240 to the FRDM i.MX 95 Pro development board.Connect the Ara240 to the FRDM i.MX 95 Pro development board. Power on the Board Follow the instructions to power on (boot) the board found in the Getting Started with FRDM-IMX95-Pro. After powering on, verify that the fan and green LED indicators Ara240 module are on are on. Get the Software This section will walk you through the Ara240 Runtime software development kit (SDK), a streamlined subset of the Ara240 SDK designed for rapid enablement and execution on NXP platforms. The Runtime SDK simplifies installation and configuration, enabling developers to quickly deploy and run AI/ML workloads on the Ara240 module with minimal effort. Overview Refer to Ara240 software release notes for details on the Ara240 software development kit (SDK) The Getting Started page for Ara240 only outlines usage on specific i.MX development platforms For any other platforms please reach out to your NXP representative for guidance. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Module Enumeration and Software Configuration This section provides instructions to verify proper installation of Ara240 module and configuration of the Ara240 Runtime SDK on the FRDM i.MX 95 Pro development board. Verify Device Detection Once the board has successfully booted, connect to the serial debug port to monitor system logs. To confirm that the Ara240 module is being detected by the board, run the following command: $ lspci | grep 1e58 Expected output: 0000:01:00.0 Processing accelerators: Device 1e58:0002 (rev 02) Enable Ara240 device For quick enablement, the Ara240 Runtime SDK starts at boot time. Refer to the Ara240 Runtime SDK documentation for detailed instructions and environment setup steps. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Developer Experience This section provides an overview of Ara240 runtime software enablement using the FRDM i.MX 95 Pro development board. Verify Setup Environment Use the following guidance on how to connect required devices. For most of the demos, you would need a camera, keyboard, mouse, internet connection and a HDMI display monitor. Setup preparation for FRDM i.MX 95 Pro boardSetup preparation for FRDM i.MX 95 Pro board Spoiler (Highlight to read)  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.   Runtime setup Description Runtime SDK delivers a complete runtime environment that enables AI/ML acceleration on the Ara240 module. To run demo applications, ensure that the Ara240 bring-up process has been successfully completed and the system is ready for demo evaluation. Refer to the Runtime SDK documentation for detailed guidance on: Verifying correct installation of the Runtime SDK. Checking and updating the Ara240 firmware version. Validating proxy service bring-up status. Executing benchmark tests on Ara240. Following these steps ensures that the module is properly initialized and ready for use. Ara240 supports the execution of CNNs, LLMs, VLMs, and agentic frameworks, enabling advanced AI workloads to run directly on Ara240. For comprehensive examples and end-to-end workflow guidance, please refer to the Ara SDK documentation page. Ara240 Demos Henceforth Q2'26 Linux BSP, GoPoint can be launched to explore preselected Ara240 demonstrations included in the NXP provided Linux Board Support Package. User Guide: GPNTUG: GoPoint for i.MX Applications Processors User Guide  FRDM-IMX9
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S32K3 FS26 new WDG period not work Hello, On my board, after power‑on reset, I configure the FS26 watchdog period to INFINITE during initialization. Then I exit DEBUG mode and enter NORMAL mode (the value read from SBC_FS26_FS_STATES_ADDR is 0xB). After that, I change the watchdog period to 64 ms (as shown in the screenshot), perform one watchdog refresh (feed), and the return value indicates success. WD_RFR_CNT increases by 1, and reading SBC_FS26_FS_WDW_DURATION_ADDR gives 0xB0CD, confirming that the period has been successfully updated to 64 ms. However, if I stop feeding the watchdog after this point, no error or reset occurs. In contrast, if I configure the watchdog period to 64 ms during initialization , then after exiting DEBUG mode, not feeding the watchdog does cause a reset as expected. Why does the watchdog not take effect when the period is changed from INFINITE to 64 ms in NORMAL mode, even though the register write and the refresh both succeed? Jason22_0-1785918605528.pngJason22_0-1785918605528.pngJason22_0-1785918605528.pngJason22_0-1785918605528.png S32K344 RTD7.0.0 FS26 6.0.0 S32DS3.6.4 EB30.0 BR, Jason Re: S32K3 FS26 new WDG period not work Hello, Oh! I forgot to switch accounts when replying – Jason07 is my another account. BR, Jason Re: S32K3 FS26 new WDG period not work Hello, Thank you very much for your reply. The reason I set the watchdog period to INFINITE during initialization is that, according to the driver code, certain operations are only performed when the period is INFINITE – for example, closing INIT_FS during the execution of the Sbc_fs26_InitDevice() function, and calling Sbc_fs26_WdRefresh inside Sbc_fs26_ClearFaultErrorCounter to clear the fault error counter. Jason07_1-1785986004068.pngJason07_1-1785986004068.pngJason07_1-1785986004068.pngJason07_1-1785986004068.png Jason07_2-1785986074130.pngJason07_2-1785986074130.pngJason07_2-1785986074130.pngJason07_2-1785986074130.png If I set the period to a finite value,  Sbc_fs26_WaitFailsafeRelease return E_NOT_OK inside Sbc_fs26_FsxbRelease, and the FS26 stays in the FS_STATES_FS0B_ASSERT state, unable to transition to FS_STATES_NORMAL_FS. Jason07_0-1785985959468.pngJason07_0-1785985959468.pngJason07_0-1785985959468.pngJason07_0-1785985959468.png BR, Jason Re: S32K3 FS26 new WDG period not work Hello, The watchdog does not become active because it was disabled when INIT_FS was closed. Configuring WDW_PERIOD[3:0] = 0000 selects the Infinite Open Window. According to the FS26 watchdog specification, the watchdog window can be disabled only during the initialization phase, and the disabling becomes effective when the initialization phase is closed. A watchdog disabled in this way cannot subsequently be enabled in NORMAL mode by writing a finite value to FS_WDW_DURATION. The successful register readback confirms that the new WDW_PERIOD field was written, and the incremented WD_RFR_CNT confirms that the refresh was accepted. These observations do not indicate that watchdog timeout monitoring was re-enabled. Runtime period changes are supported when the watchdog was enabled with a finite period during initialization. Therefore, configure a finite watchdog period during INIT_FS, for example the maximum finite period of 1024 ms if a long initialization interval is required. After entering NORMAL mode, the period can be changed to 64 ms. The new finite period becomes effective after the next watchdog refresh. This behavior also explains why the reset occurs when 64 ms is configured during initialization: in that case, the watchdog is enabled when INIT_FS closes. petervlna_0-1785930476258.pngpetervlna_0-1785930476258.pngpetervlna_0-1785930476258.pngpetervlna_0-1785930476258.png From safety perspective, infinite state is reached by watchdog disable, as the compare is in HW and flag will always rise on match. Best regards, Peter Re: S32K3 FS26 new WDG period not work Hello, Based on the observed behavior, the FS26 watchdog monitoring does not appear to start after changing WDW_PERIOD from Infinite Open Window to 64 ms in NORMAL_FS. The register write is successful, as confirmed by the readback value (0xB0CD), and watchdog refresh commands continue to be accepted, as indicated by WD_RFR_CNT incrementing. However, the absence of any watchdog timeout reaction after refreshes are stopped indicates that watchdog supervision itself is not active. When the watchdog period is configured as Infinite Open Window, Sbc_fs26_NormalFSSequence() closes INIT_FS by issuing an immediate watchdog refresh. Likewise, Sbc_fs26_ClearFaultErrorCounter() clears the fault error counter using consecutive watchdog refreshes because there is no watchdog window timing restriction in Infinite mode. When a finite watchdog period is configured, the driver follows a different path. Watchdog refreshes must be synchronized with the valid watchdog window, and the driver uses the watchdog timing mechanism (pfWdgNotification, timer synchronization, and Sbc_fs26_TimeWaitClearFault()) instead of issuing consecutive immediate refreshes. petervlna_0-1786002507583.pngpetervlna_0-1786002507583.pngpetervlna_0-1786002507583.pngpetervlna_0-1786002507583.png Re: S32K3 FS26 new WDG period not work Hello @Jason22  Did you manage to solve this problem? Did you succeed to push FS26 out of FS0B_ASSERT state to NORMAL_FS state after the call of Sbc_fs26_InitDevice ? Thank you. Re: S32K3 FS26 new WDG period not work Thank you for your answer. Re: S32K3 FS26 new WDG period not work Hello@Djuric Normal mode can be entered only when the watchdog period is initialized to infinity. If the initial value of the watchdog period is finite, the normal mode cannot be entered.
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Please help renew my S32DS5.5 license Hi team, My S32DS5.5 license expired but i still need it for some old projects. Please help me renew it. Thank you! JoaquinL_0-1785918181438.pngJoaquinL_0-1785918181438.png BR, Joaquin Re: Please help renew my S32DS5.5 license Hi,  your S32DS license has been extended. Please activate S32DS again with your old code. 
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IGGM Points System & Rules Explained | How to Earn Points, Redeem And More? To provide players with more cost-effective gaming products and services, IGGM platform has officially launched a brand-new points system, designed to let you enjoy a superior shopping experience while spending less!   Below, we break down everything you need to know: how to earn points efficiently, use them for discounts or to redeem exciting rewards, and stack VIP benefits to maximize your savings.   Before Using the Points System - Registration Required   Please note that IGGM's new points system is available only to new-registered and logged-in users. If you haven't registered or logged in yet, you will need to do so to access Check-in and Points pages.   How to Earn Points?   Accumulating points at IGGM is simple and straightforward, primarily through two channels: daily check-ins and order rewards.   1. Daily Check-in   Simply click the "Check In Today" button on the IGGM Check-in Center page to complete your check-in; once the button changes to "️Checked In (Come back tomorrow)," your points have been successfully credited! Alternatively, you can also check in by clicking the current date on the calendar.   One-tap check-in (Easter egg)   There's a little Easter egg here! If you forget to check in for the day and land straight on the coupon redemption page, just tap the "little rocket" emoji at the bottom of the list to check in instantly - no need to navigate back to the Check-in Center. You'll still get those incremental rewards for consecutive check-ins.   Please note the visual differences between PC and mobile versions! For PC users, the small rocket only begins to shake and emit flames when you hover your cursor over it; a single click launches the rocket and credits your check-in points. For mobile users, the rocket icon shakes continuously—simply tap it to check in and earn your points instantly!   Other Check-in Entry   In addition, IGGM provides the following access points for quick and convenient daily check-ins:   1. Click "Go Now" on the coupon redemption page to visit the check-in center.   2. Click the coupon section at the bottom of the homepage to access the check-in center.   3. Click the banner at the bottom of any product page on IGGM to access the check-in center.   Incremental Rewards for Consecutive Check-ins   IGGM's check-in system rewards consistency. If you check in without interruption, your daily points will increase over time: 5 points on the first day, 6 points on the second, and 8 points on the third. From the fourth day onwards, as long as you maintain your streak, you will consistently receive the maximum reward of 10 points per day.   Notes: If you check in via the check-in banner on the product page during your shopping journey, you can return to your original page via Back Shopping at the bottom after completing the check-in and triggering the points accumulation. You don't have to worry about your shopping progress being affected!   Reset Upon Interruption   If you miss a day or break your streak for any reason, your progress will reset to zero. Your next check-in will start back at the Day 1 rate of 5 points. Please note that the daily check-in reset is based on the server's time zone; be sure to check in on time to avoid losing progress due to network issues or other interruptions.   2. Points for Orders   Additionally, whenever you make an order on the IGGM platform, the system will award you points based on your subtotal amount.   Point Accrual Rate: $1 = 1 Point   Under standard conditions, every $1 of your actual spending converts directly into 1 point. To simplify calculations for order amounts involving decimals, IGGM rounds to the nearest whole number when determining the points earned. For example, if you pay $17.35, you receive 17 points; if you pay $34.86, you receive 35 points.   To ensure system efficiency for small transactions, the subtotal amount paid for an order must be at least $1 to trigger point accrual; orders under $1 do not generate any points.   Furthermore, points for all orders will be automatically credited to your account by the system only after the order status has officially changed to "Completed"; the number of points corresponds to the amount of the qualifying purchase.   New User Perk: 10x Point Rewards   IGGM has a welcome gift for new users! Your first paid order on IGGM automatically qualifies for a generous 10x points reward (meaning you earn 10 points for every $1 spent).   Please note the calculation method: the subtotal amount is first rounded to the nearest whole number, and then multiplied by 10 to determine the points for your first order. For example, if your first order's subtotal is $17.35, you will receive 170 points ($17.35 → 17 × 10 = 170 points), rather than multiplying by 10 first and then rounding ($17.35 × 10 = 173.5 → 174 points).   However, if your first order's subtotal is less than $1, you will not receive any points, and your first-order privilege as a new user will be used up. Therefore, IGGM recommends buying higher-value items you need during your first order to make the most of the 10x point reward.   Due to the significant value of this offer, points for the first order will be credited after the order is successfully delivered and passes a security review, provided no refund occurs within 24 hours.   You can view the specific points added upon completion in the My Account → My Orders section of IGGM.com. If you have just completed a payment but do not see the points immediately, please do not worry - simply wait a short while.   Point Value and Validity   Understanding the value of your points helps you make the best use of them. In the IGGM point system, 100 points = $1 (meaning each point is worth approximately $0.01).   Please note that points are not valid indefinitely; each point expires 90 days from the date it was earned. IGGM employs a user-friendly rolling expiration policy: points earned on Day 1 will expire at the end of Day 91. The specific calculation time for rolling expiration depends on the time zone of your account's IP address.   You can check for notifications regarding points nearing expiration on the "My Points" page of your account at any time to ensure you don't miss out on benefits.   Multiple Ways to Use Points: Direct Cash Deduction and Coupon Exchange   When buying items on IGGM, you can choose to use your accumulated points to directly offset the cash cost of your order or exchange them for significant discounts at IGGM Coupon Redemption Center. The choice is entirely yours!   Option A: Direct Cash Deduction at Checkout   On the checkout page, you can use the points in your account balance to reduce the cost of your current order. However, to maintain the integrity of the IGGM points system, the proportion of the order total that can be offset by points is directly linked to your order subtotal.   Please refer to the table below for specific deduction ratios based on order subtotal ranges:   Order Subtotal Range Max Point Deduction Ratio $1.00 - $9.99         5% $10.00 - $49.99         8% $50.00 +                10%   Important notes on using points for cash deductions:   1.Points are awarded only for successfully completed orders; orders that are voluntarily cancelled, flagged for suspected fraud, or fully refunded are not eligible for points;   2.Points for your first order are not credited immediately; they will be issued within 24 hours after successful delivery, provided no refund has occurred;   3.If an order involving points undergoes a partial refund, the system will deduct the corresponding points (rounded based on the refund amount) and return any points that were consumed. Returned Consumed Points = Consumed Points × (Refund Amount / Subtotal Amount);   4.Points can be used in conjunction with VIP discounts;   5.Cannot be used in conjunction with discount codes or cash coupons;   6.Cannot be exchanged for cash;   7.Cannot be withdrawn as cash;   8.Cannot be transferred between accounts;   9.IGGM.com reserves the right of final interpretation for all points-related policies.   Option B: Redeem Discount Codes or Cash Coupons   You can also visit the points redemption page to exchange points (in tiers ranging from 100 to 500 points) for discount codes (various rates) or cash coupons (subject to minimum order requirements). For example, the $10 cash coupon can only be used if your order's subtotal amount is $100 or more. If your subtotal is less than $100, the coupon will not automatically appear at checkout.   Points Spent Discount Code Cash Coupon (Min. Order Req.) 100 3% $1 (Order ≥ $10) 200 4% $3 (Order ≥ $30) 300 5% $5 (Order ≥ $50) 400 8% $8 (Order ≥ $80) 500 10% $10 (Order ≥ $100)   All discount codes and cash coupons are limited to 30 per week, first come, first served! Different colors clearly indicate the current stock status: green for 21-30 remaining, orange for 11-20, and red for 1-10. When stock reaches zero, it will display "Out of stock." But don't worry, just come back next week!   By the way, if you forget to check in for the day, the little rocket emoji on this coupon page is your quick way to do so! With a simple tap, a shake of the little rocket, and your points are in the bag!   While coupons are great, please keep in mind that all discount codes or cash coupons are valid for only 3 days. Redeem them carefully and ensure the items you wish to buy are in stock to avoid wasting your points.   You can view your coupons and their current expiration status on the My Account → My Coupons page.   Note: You can quickly access the coupon redemption page via the "Coupon Center" at the bottom of the IGGM homepage. We recommend bookmarking this page for convenient future check-ins and redemptions - saving you time and effort.   Notes on Points Redemption Coupons:   1.Each reward is limited to the first 30 users per week on a first-come, first-served basis.   2.All discount codes and cash coupons require CF verification upon redemption.   3.Redeemed discount codes/cash coupons are valid for 3 days from the time of claim.   4.Only one discount code/cash coupon can be used per order. They cannot be combined with VIP discounts or points deductions.   5.Discount codes/cash coupons are not valid for gift cards and top-up services.   6.Redeemed discount codes, cash coupons and free orders cannot be returned or exchanged once claimed.   7.IGGM.com reserves the right of final interpretation.   Hidden Option C: Direct Exchange for In-Game Currency/Items (Coming Soon)   In addition to coupons, IGGM will soon add options to the redemption page allowing you to exchange points directly for specific in-game items, such as Monopoly GO cards, Diablo 4 materials, or POE 1/2 currency.   Once you meet the points requirements and click to redeem, a pop-up window will prompt you to enter the necessary delivery details for the game. After accurately filling in the information and completing the verification, the system will automatically generate a free order and display it in Coupon Order list; you just need to wait for it to be delivered safely. More point redemption features and options are coming soon - stay tuned!   If you encounter errors during the redemption verification process, please check your network connection and try again using a reliable VPN.   Furthermore, given the nature of virtual items, returns or exchanges are not possible once an order begins processing; however, if delivery fails due to issues on the IGGM platform, the points used will be fully refunded.   VIP Ranks & Benefits   For VIP members, IGGM offers tiered discounts to all users based on accumulated spending. Once your cumulative spending hits a specific threshold, you automatically unlock a permanent VIP discount:   VIP 1: Your Spending (<$1,000), Get a 1% discount.   VIP 2: Your Spending (≥ $1,000 and < $3,000) , Get a 2% discount.   VIP 3: Your Spending (≥ $3,000 and < $6,000), Get a 3% discount.   VIP 4: Your Spending (≥ $6,000 and < $10,000), Get a 4% discount.   VIP 5: Your Spending (≥$10,000), Get a 5% discount.   Discount Stacking Rules:   VIP Discounts CAN be combined with Points Deductions. VIP Discounts CANNOT be stacked with Discount Codes or Cash Coupons.   At checkout, you may apply either:   Option A: Discount Code or Cash Coupon (Alone) Option B: VIP Discount + Points Deduction (Note: Discount Codes and Cash Coupons are not valid for Gift Cards or Top-up services.)   Stacking Discounts and Maximizing Savings   How can you get the most savings when checking out? IGGM has designed a smart checkout system based on our VIP ranks and point-redemption rules.   At IGGM, VIP discounts stack perfectly with direct point deductions. However, please note that redeemed discount codes or cash coupons cannot be combined with VIP discounts or point deductions. Additionally, only one coupons may be used per order.   At checkout, the system automatically compares the final costs of "Option 1 (VIP Benefits + Direct Point Deduction)" and "Option 2 (Single Discount Codes or Cash Coupons)" to select the most cost-effective choice for you, saving you the trouble of manual calculations. Which option offers the best deal will be displayed next to that option (Best Value). Of course, if you have your own preferences regarding coupon and point usage, you are free to select your preferred discount method.   Refunds and Point Returns   IGGM's refund policy allows you to request a refund at any time prior to the completion of delivery. However, we have specific rules regarding the refund and rebate of your points in this situation:   Situation 1: Full Refund   If you cancel your order for personal reasons, orders suspected of fraud or requiring a full refund will not be awarded points; furthermore, points already used in such orders will not be refunded.   However, if a full refund is issued due to reasons attributable to IGGM, the points consumed for the order will be fully refunded to your account.   Situation 2: Partial Refund   If an order involving awarded points undergoes a partial refund due to special circumstances, the system will refund a portion of the consumed points on a pro-rata basis relative to the refund amount. Naturally, the points rebate you would have originally received upon order completion will also be adjusted; the corresponding points will be deducted based on the refund amount, with the figure rounded to the nearest whole number.   Here is the formula for calculating point returns during a refund:   Returned Consumed Points = Consumed Points × (Refund Amount / Subtotal Amount) Deducted Earned Points = Subtotal Amount - Refund Amount (rounded to the nearest whole number)   The all-new IGGM member point system is designed to offer you more viable discount options for your long-term gaming purchases. Every point accumulated is a sincere token of our appreciation for your support.   Log in to your IGGM account now, visit the Check-in Center to start accumulating points, and experience a smarter, more rewarding checkout process like never before!   Frequently Asked Questions about IGGM Points System   Q1: Can I transfer my VIP 5 perks from my old account to a newly created account and start accumulating check-in points there?   A: No. To ensure account security and platform fairness, VIP tiers and points are treated as exclusive assets of an individual account. According to our system security rules, transferring, merging, or gifting perks across different accounts is strictly unsupported.   Q2: My account currently has 277 points. If I buy items worth $34.68 and use up all my points to get a $2.77 deduction, but later receive a partial refund of $15.44 due to certain factors, how many points will I end up with?   A: Your original $34.68 order generates 35 points based on rounding. Due to the partial refund of $15.44, the system will proportionately deduct 15 points (rounded to the nearest whole number). Therefore, the net points earned from this purchase will be: 35 - 15 = 20 points. Additionally, the system will return the points you consumed. Based on the calculation formula: Consumed Points × (Refund Amount / Total Purchase Amount), you will get back 123 points. As a result, your final account balance will be 123 + 20 = 143 points.   Q3: Can I create unlimited new IGGM accounts and place small orders to exploit the 10x points newcomer reward?   A: No. IGGM strictly prohibits the malicious registration of multiple accounts, utilizing technical exploits, or engaging in order manipulation to farm newcomer benefits. Our system is equipped with rigorous anti-fraud and risk control mechanisms: the 10x points multiplier for the first order will only be credited after the order is successfully delivered and passes a 24-hour anti-abuse system review. If the risk control system detects multi-account farming linked by the same IP, same device, same payment method, or malicious account associations, the platform reserves the right to permanently ban the related accounts and clear all accrued benefits.   Q4: I just registered an account and my first order was a small item for $0.9. Because it was under $1, the system didn't give me any points. Then, my second order was for $100. Why didn't my second order get the 10x points? My first order didn't receive any points anyway, shouldn't this second order count as my actual "valid first order"?   A: No. The system strictly identifies the "New User First Order" based on the very first paid order under your account, regardless of the transaction amount. The threshold ruling out points for subtotals under $1 is a foundational platform policy. Therefore, we highly recommend that new users consolidate their shopping carts on their first purchase and bundle higher-value items into the first order to fully maximize the value of the 10x points perk.   Q5: If a website error prevents me from checking in for the day, causing my check-in streak to break, what measures will IGGM take to compensate for my points loss?   A: We sincerely apologize for any inconvenience caused. The daily check-in resets based on a specific time matching the server's time zone. If the streak is broken due to network latency or missing the refresh window, the system will strictly execute the automatic reset policy. We recommend completing your check-in as early as possible each day and ensuring a stable network environment. If the interruption is conclusively caused by a large-scale server outage on the platform, an official site-wide points compensation announcement will be issued once resolved. Please note that support agents do not have the authorization to manually alter individual check-in histories. Thank you for your understanding.   Q6: I spent 300 points to redeem a $5 cash coupon, but the game items I wanted have been out of stock on the platform for the past few days. As a result, the coupon expired within 3 days without being used. The stockout is the platform's issue, so why should my 300 points be deducted for nothing?   A: We apologize, but once a reward is redeemed at the Rewards Center, the corresponding points will be deducted and cannot be refunded. Because each reward is strictly limited to the first 30 users per week on a first-come, first-served basis, and the cash coupons are valid for 3 days, we highly recommend verifying current product stock and your purchase intent before making a redemption to avoid accidental cash coupon expiration.   Q7: Can I still request a refund if my order status is "Completed"? Can the points be refunded?   A: If IGGM has successfully completed the delivery and you have confirmed the order's completion, we unfortunately cannot honor refund requests. The points spent will not be returned. However, if IGGM fails to complete the service due to our own issues (for example, if Tycoon Racers carry service fails to help you achieve Rank #1), we will refund the points you spent according to the refund ratio.   Q8: Why do I keep encountering errors when trying to redeem a coupon?   A: Coupon redemption errors typically occur due to network instability or system security protocols. Your IP address might be flagged as originating from a high-risk region. We recommend adjusting your VPN settings or connecting to a different network, then trying again. If the issue persists, please reach out to our 24/7 Customer Support team for further assistance.   Q9: Can I use a script or plug-in to claim the weekly limited 30 discount codes/cash coupons available each week?   A: To ensure fairness for all players, we have implemented strict security measures. Redeeming any discount codes or cash coupons requires passing verification, rendering any script-based simulated clicks ineffective. IGGM reserves the right to void coupons and impose account restrictions on any account found using irregular methods (such as multi-instance farming, emulators, or third-party software) to forcibly claim coupons.   Q10: If I use points to offset the cost but later receive a refund due to special circumstances, will the validity period of the returned points be extended?   A: No. Returned points retain their original acquisition date and continue to follow the 90-day expiration rule; the IGGM platform will not reset or extend the expiration date due to a refund. Please use the returned points as soon as possible to avoid expiration!
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关于S32k144的pwm频率会周期变化的问题 我现在在开发nxp的s32k144遇到一个问题,我使用eb配置工具,我配置好了FTM0的四个通道输出,并且再代码中调用了PWM_Init();setdutycycle(8129);我在配置中选择的是中心对齐模式,不启动死区,也不和别的通道绑定,并且周期设置的是0.00125,每个通道都是独立模式,得到的是250us,占空比20%的方波,这显然不对,我希望是25%才对,所以我后面换了一下占空比为setdutycycle(16339),但是这个得到的结果是波形不对,通道变成了由150us周期66占空比的方波和100us周期为50占空比的方波交替出现,请问这是为什么?这是我的实际波形; 事实上可以看出我这里有两个问题:1、为什么我的pwm占空比设置会有偏差;2、为什么我的pwm周期在不断地变化? Re: 关于S32k144的pwm频率会周期变化的问题 Hi 请告诉我你测试的是哪个版本的Real-Time Drivers for S32K1还是之前哪个版本的AUTOSAR MCAL for S32K1 devices? 请注意,MPC5xxx 和 S32K1xx 器件的 MCAL 已停止支持。如需进一步支持,需经市场团队批准,请联系您的恩智浦销售人员寻求帮助。 Best Regards, Robin Re: 关于S32k144的pwm频率会周期变化的问题 我不清楚你使用的哪个版本软件,但需要注意设置Loading Point,参考以下两个讨论: Changing FTM_PWM period and duty cycle S32K116 PWM输出问题
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S32K3 fast standby wake up fail Hello, In a Fast Standby example project, I defined an array arr in the .standby_data section, but this array is not used anywhere in the code. However, if I comment out this array definition, the device fails to wake up from Fast Standby; if I keep it, wake‑up works as expected. Moreover, I noticed that the optimization level also affects the behavior: with -O0 optimization, wake‑up fails, but changing to -Os makes it work. Why does defining a variable in the .standby_data section affect the wake‑up functionality? And why does the optimization level have such an impact? Jason22_0-1785895168596.png S32K312 RTD400 S32DS BR, Jason Re: S32K3 fast standby wake up fail Hi@Senlent Thank you very much for your reply. After changing the address to 0x20408000, the previously failing cases are now working properly. By the way, regarding my other thread (S32K3 ADC Optimize DMA Streaming), I replied to you using the new account(Jason07) registered with the company email – I forgot to switch accounts when replying. Re: S32K3 fast standby wake up fail Hi@Jason22 Whether you comment out the "arr" array in your program affects the value of __BSS_SRAM_START, which will be used as the initial value of the MSP after a fast wake-up. If this value is too small, it can cause a stack overflow. In our example project, we recommend setting this value to 0x20408000, which is the end address of the standby RAM.
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S32K358 config tool dma has no DMA_IP_HW_INST_1 1. S32DS 3.6.10 2. chip S32K358 3. RTD: 7.0.1 problem: dma emux has no instance 1 ,just instance 0 Licunhao_0-1785922766915.png this chip should have two instance of dma mux, but now the config tool just one. I want to use LPUart4 DMA,but it is in mux1. Someone give me a help. Re: S32K358 config tool dma has no DMA_IP_HW_INST_1 Hi, There is a single DMA module with 32 DMA channels and two DMAMUX instances. Each DMAMUX instance provides 16 channels and is mapped to half of the DMA channels. PetrS_0-1785931235713.png As the LPUART4 TX request is routed to DMAMUX1, you need to use DMA channels 16-31.   The DMAMUX configuration is handled in the RM component, so please add the RM component to the project and configure it accordingly. PetrS_1-1785931415785.png PetrS_2-1785931424284.png BR, Petr
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Request for Bare-Metal Driver Code Examples for LX2082 Processor I am currently working on a project based on the NXP LX2082A processor (custom board) and am looking for bare-metal software examples to accelerate our development. Could you please provide or direct me to any available bare-metal reference code, driver examples, or application notes for the following peripherals on the LX2082 processor? UART I2C SPI Ethernet (MAC/PHY initialization and communication) Specifically, I am interested in: Peripheral initialization sequences Register-level driver implementations Example source code in C Bare-metal examples without an operating system Any available board support package (BSP) or reference projects for the LX2082 platform If these resources are available under an NDA or require special access, please let me know the necessary procedure to obtain them. Thank you for your time and support. I look forward to your response. Best regards, sai chandu Re: Request for Bare-Metal Driver Code Examples for LX2082 Processor You could refer to bare-metal software provided in Real-time-edge software. Please refer to section "2.4 Baremetal on Cortex-A core" in the attached document.
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S32k344 design studio driver example code Hi Team  I wanted to run basic example codes on S32k344.  I have installed  S32 Design Studio for S32 Platform Version: 3.6.0 Build id: 241128 I am unable to find any diver examples in . I even with S32k extension and update to update s32k3xx package but the installation fails every time. It is stuck at 70%. Please let me know if you require any other information and help with basic examples. Regards Gopal Re: S32k344 design studio driver example code Hi @rathi_tg  To get started, we recommend using the latest version of the tools available, which is currently S32 Design Studio 3.6.10. There is no need to install it as a separate instance, as it can be installed as an update to your existing installation. Detailed instructions for this process can be found in the S32 Design Studio 3.6.10 RFP Installation Guide, which is available on the same download page as the S32DS installer. Regarding examples for S32K3 devices, these are included as part of the RTD packages. A good reference is the video How To Download, Install and Configure the RTD 5.0.0 with S32 Design Studio 3.6.0, which explains in detail what components need to be downloaded, how to install them, and how to create a project based on example. Although the video was created for RTD 5.0.0, the procedure is similar for newer RTD releases. Note: The latest RTD release available for S32K3 devices is RTD 7.0.1. Additionally, you may find useful examples and application projects in NXP's Application Code Hub, which contains a variety of ready-to-use examples for different devices and use cases. BR, VaneB Re: S32k344 design studio driver example code Hi   I have successfully imported the driver files and i have imported "Siul2_Dio_Ip_Example_S32K344" project. i have run the mex and updated the code. the code is built without any error. I have S32k344-WB with me which when powered on has a default switch and led program.  When I flash my built file the progress bar shows 100% but  i am unable to see any changes in the board behavior it is still executing the old code.  Regards  Gopal  Re: S32k344 design studio driver example code Hi @rathi_tg  How did you determine that the application is running old code? Also, please note that the example projects are tested with specific boards, which are listed in the description.txt file included with each example. Because different boards can have different hardware configurations, please verify that the pin assignments and configurations match your target board. You may need to update some of the pin settings accordingly to ensure the example works correctly on your hardware. Re: S32k344 design studio driver example code Hi @Valval  The issue got resolved i did not install the debug package  . Regards  Gopal
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I need RTM 1.5 package for S32 Power architecture Design Studio Project I am working on MPC5746 Target project using S32 Design Studio 2.1. While importing i am facing issue w.r.t Project was created using SDK_S32_PA_15 which is not installed. If i try to forcefully convert the project, i am facing compilation errors in CPU.h files. Please provide a compatible package. image.png Re: I need RTM 1.5 package for S32 Power architecture Design Studio Project Hello, The SDK_S32_PA_15 is also known as S32 SDK 3.0.3. You can install this SDK into S32 Design Studio for PA v2.1 using the S32DS Extensions and Updates menu. This menu is located by: Help -> S32DS Extensions and Updates   petervlna_1-1786000019769.png If this package is installed correctly, then you shouldn't receive this error message.  Best regards, Peter
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Zephyr UAC2 → SAI reference on i.MX RT1020 Hi everyone, I'm trying to get a USB-to-I2S audio pipeline working on the i.MX RT1020 using Zephyr's UAC2 asynchronous explicit feedback sample, but I'm running into issues with the NXP SAI (I2S) driver and eDMA. Before I spend more time debugging DMAMUX and IRQ configuration, does anyone know of a working USB-to-I2S example for the RT10xx series using Zephyr? I'm particularly looking for any reference project that implements a UAC2 to SAI audio path on Zephyr. Thanks in advance! Re: Zephyr UAC2 → SAI reference on i.MX RT1020 Hi @lpc73 , Thanks for your interest in NXP MIMXRT series! There is currently no ready-made UAC2→SAI reference project for the RT10xx in upstream Zephyr. The building blocks are all supported on RT10xx: the SAI/I2S driver (nxp,mcux-i2s), eDMA, and the UAC2 class. DMAMUX routing is done via the devicetree properties nxp,tx-dma-channel / nxp,rx-dma-channel + pinctrl, not manually in C. The main piece you'll need to add is the feedback loop for the RT platform, and be sure to place DMA audio buffers in non-cacheable memory. If Zephyr isn't mandatory, the MCUXpresso SDK's dev_audio_speaker + sai_edma_transfer are the most mature ready-to-use UAC2→SAI examples. Best regards, Gavin
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CircO2 Nitric Oxide Tablets Review: A Complete Buyer's Guide CircO2 is a nitric oxide support supplement made by Advanced Bionutritionals. Unlike a lot of pills you swallow with water, CircO2 comes in a quick-dissolving tablet (sometimes called a lozenge) that melts in your mouth. This is one of the things that makes it stand out from other CircO2 Tablets on the market. The main idea behind CircO2 Oxygen Booster and Circulation Support is simple: help your body make more nitric oxide, so your blood vessels can relax and widen. When that happens, blood (and the oxygen it carries) can move more freely through your body. That can mean more energy, warmer hands and feet, and better stamina during the day.  
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Request for NXP V2X Evaluation Board and Design Files Dear NXP Team, We are evaluating V2X communication solutions for an automotive application supporting V2V, V2I and V2P safety messages. We are interested in NXP’s RoadLINK/SAF5400-based V2X solution and the OrangeBox platform. Kindly provide the following information: Recommended NXP V2X evaluation board or reference platform Evaluation-board ordering part number SAF5400 availability and lifecycle status Reference schematic and hardware design files Bill of materials and PCB layout guidelines RF matching and antenna reference design Hardware user manual and software development kit BSP, drivers and example applications Functional-safety documentation, including ASIL-B support details Security-device recommendations for V2X message signing and verification NDA procedure for accessing controlled technical documents Our intended application is an automotive V2X communication unit operating in the 5.9 GHz band. Please also confirm whether NXP currently offers a solution supporting DSRC/IEEE 802.11p, C-V2X PC5, or both. Kindly share the applicable product documents, commercial contact details and procurement process. Best regards, Renjith Thomas Senior Design Engineer - HW Get My Solutions +91 8015237416 Re: Request for NXP V2X Evaluation Board and Design Files Hello, Hope you’re doing well. This is our DSRC Safety Modem product catalog for automotive V2X applications: DSRC Safety Modem. You can also find our recommended Products for V2X Communications here. The RoadLINK SAF5400 is an automotive-qualified single chip DSRC modem for V2X applications, compliant with IEEE 802.11p, IEEE 1609.4, ETSI EN 302663, ETSI EN 302571, and ARIB T-109M. I'm sorry for the inconveniences this may cause, but, unfortunately, information about the SAF5400 and other V2X Automotive Products is protected under a Non-Disclosure Agreement. To obtain information about these products, could you please contact your Local Distributor from the Distributor Network so they can not only help you with the NDA process but also provide you the information you might need of those products? Best regards, Ana Sofia.
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GPIO wakeup triggered by short noise pulses during suspend Hi NXP team, We are using i.MX8MP on a custom board with Linux BSP LF-6.12.20. Several GPIO pins are configured as wakeup sources. Problem: during EMC transient testing (ESD), short noise pulses on these GPIO lines falsely wake the suspended system. We have already confirmed that software debounce cannot solve this: the wakeup decision is made by hardware while the CPU is suspended, and the GPIO interrupt handler — including the gpio-keys debounce — only runs after the system has resumed, so software cannot prevent the wakeup itself. We have also reviewed the Linux drivers (LF-6.12.20) and the i.MX8MP reference manual, and we could not find any hardware filter for the GPIO wakeup path. Please confirm whether this understanding is correct. Questions: 1. Does i.MX8MP have ANY hardware option (in GPIO, GPC, or configurable via ATF) to ignore very short pulses on a wakeup pin — for example a glitch filter or a minimum pulse-width setting? This includes level-trigger mode: does it require the level to be held for a minimum time, or does any instantaneous pulse still trigger wakeup? 2. If no such hardware option exists, what is NXP's recommended solution for this kind of false wakeup? Any application note on ESD protection for GPIO wakeup inputs would be appreciated. 3. Is there any NXP reference design where the Cortex-M7 checks/filters wakeup signals while the A53 stays in suspend? Platform: i.MX8MP custom board, BSP: LF-6.12.20 Best regards, i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: GPIO wakeup triggered by short noise pulses during suspend Hello @Leo_dev  Hope you are doing very well. Q1. Your understanding is correct. The i.MX8MP GPIO/GPC wakeup path has no hardware glitch filter or minimum pulse-width setting or debouncing register. Q2. As there is not an On-chip solution, the recommended design is adding a filter to the PAD. Q3. Yes, you can take a look to the AN13400 "i.MX 8M Low Power Design By M Core Running In System Suspend" is the primary NXP reference for this kind of architecture. Best regards, Salas.
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