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GPIO wakeup triggered by short noise pulses during suspend

Hi NXP team,

We are using i.MX8MP on a custom board with Linux BSP LF-6.12.20. Several GPIO pins are configured as wakeup sources.

Problem: during EMC transient testing (ESD), short noise pulses on these GPIO lines falsely wake the suspended system.

We have already confirmed that software debounce cannot solve this: the wakeup decision is made by hardware while the CPU is suspended, and the GPIO interrupt handler — including the gpio-keys debounce — only runs after the system has resumed, so software cannot prevent the wakeup itself.

We have also reviewed the Linux drivers (LF-6.12.20) and the i.MX8MP reference manual, and we could not find any hardware filter for the GPIO wakeup path. Please confirm whether this understanding is correct.

Questions:

1. Does i.MX8MP have ANY hardware option (in GPIO, GPC, or configurable via ATF) to ignore very short pulses on a wakeup pin — for example a glitch filter or a minimum pulse-width setting? This includes level-trigger mode: does it require the level to be held for a minimum time, or does any instantaneous pulse still trigger wakeup?

2. If no such hardware option exists, what is NXP's recommended solution for this kind of false wakeup? Any application note on ESD protection for GPIO wakeup inputs would be appreciated.

3. Is there any NXP reference design where the Cortex-M7 checks/filters wakeup signals while the A53 stays in suspend?

Platform: i.MX8MP custom board, BSP: LF-6.12.20

Best regards,

i.MX 8M | i.MX 8M Mini | i.MX 8M NanoRe: GPIO wakeup triggered by short noise pulses during suspend

Hello @Leo_dev 

Hope you are doing very well.


Q1.

Your understanding is correct. The i.MX8MP GPIO/GPC wakeup path has no hardware glitch filter or minimum pulse-width setting or debouncing register.


Q2.

As there is not an On-chip solution, the recommended design is adding a filter to the PAD.


Q3.

Yes, you can take a look to the AN13400 "i.MX 8M Low Power Design By M Core Running In System Suspend" is the primary NXP reference for this kind of architecture.



Best regards,

Salas.

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