咨询CLRC663 SDK 以及 NFC 前端开发套件 (OM26630FDK) 我目前正在使用 CLRC663 加 NFC 前端开发套件 (OM26630FDK) 测试 NFC 卡读/写功能。虽然我已经使用 NXP NFC Cockpit 成功测试了功能，但我想继续在 MCUXpresso IDE 环境中创建和测试固件。 但是，我很难找到适合此目的的 SDK。您能否告诉我是否有可用的 SDK 支持 CLRC663 加 NFC 前端开发套件（OM26630FDK）作为独立设备，而不需要 FRDM-K82F 板？

i;MX8MP LVDS 时钟极性 大家好， 我们正在使用#i.MX8MP 应用处理器来驱动我们其中一块定制板上的 LVDS 面板。该小组目前看起来并不像预期的那样。文本几乎无法阅读，当我们显示红色屏幕时，我们会看到一些黑色（移动）闪烁。我们已经联系了面板的供应商，他们建议反转 LVDS 时钟的极性（根据当前设置从下降沿到上升沿或从上升沿到下降沿）。 然后我们查看了#i.MX8MP 的参考手册。我们没有找到任何有关 LVDS 接口时钟极性的相关寄存器/信息。您是否了解一些有关时钟极性的信息？默认设置是什么？这个可以配置吗？ 我们尝试交换正负时钟信号作为替代方案，但这并不奏效（电压水平不同，所以这并不意外）。我们还尝试改变 LCDIF 中像素时钟的极性。然而，面板看起来完全一样。是否有人有其他建议来排除故障或解决我们的问题？ 此致， 耀西

Hard/Bus Fault while running AN12255SW flash_remap_test I'm having trouble running the flash remap test from AN12255SW. Once I finish initializing FlexSPI, I receive a bus fault BFARVALID (7) BusFault Address Register (BFAR) valid flag and PRECISERR (1) Precise data bus error in addition to a forced hard fault. I needed to modify the clock configuration, otherwise the debugger would stop working - I believe this config is correct as I've used it with another flexspi flash example and my debugger remained active afterwards. I'm not sure if maybe I should be setting additional options for the AHB buffer? Also in the flexspi flash example, the flexspi flash driver code is run out of RAM instead of Flash using a linker script, but it doesn't look like that is needed here? int main { uint32_t i = 0; flexspi_config_t config; status_t status; uint8_t vendorID = 0; BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); BOARD_InitDebugConsole(); CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. 396M */ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */ SCB_DisableDCache(); // Flash remap registers not used at this point //IOMUXC_GPR->GPR30 = 0; //IOMUXC_GPR->GPR31 = 0; //IOMUXC_GPR->GPR32 = 0; PRINTF("\r\nFLEXSPI example started!\r\n"); /*Get FLEXSPI default settings and configure the flexspi. */ FLEXSPI_GetDefaultConfig(&config); /*Set AHB buffer size for reading data through AHB bus. */ config.ahbConfig.enableAHBPrefetch = true; config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; FLEXSPI_Init(EXAMPLE_FLEXSPI, &config); // BUS FAULT OCCURS HERE /* Configure flash settings according to serial flash feature. */ FLEXSPI_SetFlashConfig(EXAMPLE_FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); ... } i.MXRT 106x Re: Hard/Bus Fault while running AN12255SW flash_remap_test How can I set the fuse bits as outlined in AN12255 section 3.2.1? Re: Hard/Bus Fault while running AN12255SW flash_remap_test Thank you. I placed the FlexSPI functions into RAM using a similar method to the 'flexspi_nor_polling' example and I no longer had hard faults. I'm thinking the linker for this example was set up a different way that would have done this for me, but I'm not sure how/if it can work with MCUXpresso. The flash remap test uses the same drivers as the flex spi example (just adding the steps to set the GPR), so I pulled the code in to test it and the remap seemed to work just fine. Re: Hard/Bus Fault while running AN12255SW flash_remap_test Hello Diego, I'm using MCUXpresso and not IAR, is it required for using this example? Re: Hard/Bus Fault while running AN12255SW flash_remap_test Hi @schafbo  Thank you for reaching out! It seems that are you running the demo located in AN1225SW> SW\src\boards\evkmimxrt1060\use_case\flash_remap_test\nor\polling_transfer\, correct ? If yes, which scatter (icf) file did you selected? Below an example for more context.   It is expected that the AN12255 SW was working well when it was released, but this occurred  released sometime ago (2018), I do not know if latest IAR and compiler settings and version are affecting.  Diego Re: Hard/Bus Fault while running AN12255SW flash_remap_test You _definitely_ need to be running out of RAM when calling FLEXSPI_Init() and FLEXSPI_SetFlashConfig(). IIRC, in between those two function calls, the FLEXSPI peripheral will have no LUT sequences, so it won't be able to read anything out of flash. Maybe try wrapping your main() function in AT_QUICKACCESS_SECTION_CODE() and see if that helps? Also, if it's useful, here's how we did this in Mbed OS: https://github.com/mbed-ce/mbed-os/blob/master/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/TARGET_EVK/flash_api.c#L91 Re: Hard/Bus Fault while running AN12255SW flash_remap_test I'm using an iMXRT1062.

SDK for CLRC663 plus NFC Frontend Development Kit (OM26630FDK) に関するお問い合わせ 現在、CLRC663 plus NFC Frontend Development Kit(OM26630FDK)を使用してNFCカードの読み取り/書き込み機能をテストしています。NXP NFC Cockpitを使用して機能のテストに成功しましたが、MCUXpresso IDE環境でファームウェアの作成とテストを進めたいと思います。 しかし、私はこの目的のための適切なSDKを見つけるのに苦労しています。CLRC663 plus NFC Frontend Development Kit(OM26630FDK)をスタンドアロンデバイスとしてサポートするSDKがあれば、FRDM-K82Fボードなしでお知らせください。

Help Needed: Is My Schematic for PN7161 Correct? Hi everyone, I hope you're all doing well! I’ve designed a custom board based on the OM27160A1 reference design and connected it to an ESP32-C6. I’ve recently assembled the board and am now trying to work with the PN7161. Unfortunately, I’m already struggling to read the I2C address, and I’m unsure what might be causing the issue. I’m wondering if something might have gone wrong during the soldering process, or if there’s an issue with my schematic design from the start. To troubleshoot, I’ve included only the reader-relevant portion of my schematic in the attached images. I would greatly appreciate it if someone could kindly review my schematic and let me know if anything looks off. I’m open to any suggestions or feedback to help me get the PN7161 up and running. Thank you so much in advance for your help! Best regards, Alexander Re: Help Needed: Is My Schematic for PN7161 Correct? Thank you for the detailed answer and taking the time to look into my schematics!!! After applying the hardware fixes you mentioned and changing and trying with the software I finally managed to get my reader scanning tags! 🙂 For the Antenna etc. I build it exact the same as mentioned in the design guide, so I dont have to deal with this on my own (for my purpose its enough if it reads the UID atm) Re: Help Needed: Is My Schematic for PN7161 Correct? Hello, Good Day! Thank you very much for your interest in our products. Please consider that the OM2716A1HN evaluation board is not a Reference Design and is not intended to represent a final design recommendation for any particular application. The proper functionality of a final device heavily depends on proper printed-circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal quality. With that taken into account I would like to point out some differences that were found between the documented design and the design that you shared with us. As already mentioned, VDD(PAD) is connected to a cap that is connected to 3.3v. Should be connected to a grounded cap, and connected directly to VDD(PAD) Same thing happens with VDD(UP) as it should be connected to grounded cap, and connected directly to VDD(UP) as follows:                                  You could consider adding a 10k Resistor form DWL_REQ to GND to ensure the logic state of the pin.                                             C16 has a value of 0.1uF when in the EVK schematic that capacitor has a value of 4.7uF Please check with the XTAL manufacturer that it has everything it needs to work properly and confirm that it meets the specs of our recommended hardware. It is also, important to point out that resistors R8, R9, R10, R11 are well connected in the schematic, but should not all be placed during assembly of the board given that they interfere in the I2C address selection of the reader. In order to meet the proper range of valid addresses, the resistors should be connected (on the PCB) as follows:                                 R10 is equal to custom R10 R11 is equal to custom R11 R12 is equal to custom R8 R13 is equal to custom R9 Please refer to PN7160 Hardware Design Guide to find out more about recommended hardware specifications. I would also recommend checking out OM27160 User Manual to get a deeper understanding on how the Evaluation Board works, its possible hardware modifications and how this interacts with the signals. If you continue having trouble reading NFC cards, please make sure you stick to the PN7160 antenna design and matching guide specifications, since hardware variations can interfere with the proper functionality of the antenna. Also, consider checking out some of the NFC Antenna Design training videos that we offer publicly, as well as the AN11535 Application Note on the use of a Vector Network Analyzer (VNA) which is required for proper antenna tuning.  Unfortunately we may not be able to provide further support regarding the software you are using, as we limit the support scope to our recommended libraries, some of which can be downloaded from https://www.nxp.com/doc/SW6705 and easily ported to any other host providing I2C communication as described in NXP-NCI2.0 MCUXpresso examples guide, although keep in mind that porting to third-party platforms is out of our support scope. My best regards, Daniel. Re: Help Needed: Is My Schematic for PN7161 Correct? Hey thans for the feedback! Yes you are completely right I messed up there a little bit and now resoldered it and connected C21 to Ground and V3.3 before the connection. I can connect the module over I2C and I tried using the beta test firmaware for arduino / ESP32 from here https://github.com/ElectronicCats/ElectronicCats-PN7150/releases/tag/v3.0.0-beta But im not able to detect any cards. Can you see any other error in my schematics or do you know any ways to measure it? Re: Help Needed: Is My Schematic for PN7161 Correct? Hi first look is a problem on C21 that can not work at this point please check

[K32w041/K32061]有勘误表吗？ K32W041 或 K32W061 处理器是否有勘误表文档？ 我想知道硬件存在哪些问题，以便能够创建更稳定的产品。 我所知道的例子足以成为发布此类文件的理由： - 掉电检测具有重置 CPU 的功能，但会一直保持 CPU 重置状态，直到硬重置或 PAD RSTN。这使得此重置功能作为安全功能（几乎）毫无用处。 - 不支持同步 ADC？有强烈的迹象表明 ADC 的同步模式不受支持，请参阅 K32W061.h 中 ASYNMODE 的注释： ASYNMODE - 选择时钟模式。0：同步模式。不支持。 但是用户手册 UM11323 修订版 1.2（NXP 网站上的最新版本）指出：“有两种时钟模式可用：同步模式和异步模式。” 回复：[K32w041/K32061]是否有勘误表文档？ 谢谢，我觉得自己很愚蠢，没有找到该文件，但我发现该文件还不到 1 个月。

S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast This question might be similar to this one: https://community.nxp.com/t5/S32K/S32K312-LPSPI-DMA-AsyncTransmitFast/m-p/1923811  I have to send two spi transaction to a device. I am trying to use Lpspi_Ip_AsyncTransmitFast. const Lpspi_Ip_FastTransferType ft[] = { { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf_wren, .RxBuffer = rxbuf_wren, .DefaultData = 0, .Length = 1, .KeepCs = false, }, { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf, .RxBuffer = rxbuf, .DefaultData = 0, .Length = 10, .KeepCs = false, } }; void send_spi_txn(void) { Lpspi_Ip_StatusType status = Lpspi_Ip_AsyncTransmitFast( ft, 2, Lpspi_Ip_Callback_lpspi_0_dma ); if (status != LPSPI_IP_STATUS_SUCCESS) { failed_spi_dma = true; } }   I have already tested using Lpspi_Ip_AsyncTransmit to send a single transaction and then sending another one from the completion callback, but this is obviously not ideal so would like to be able to use the transferlist instead. The issue is that no data is being sent. the first time Lpspi_Ip_AsyncTransmitFast is called it reports success, but every subsequent call fails. also can see that there are no spi transfers. on the logic analyzer, but when i just do Lpspi_Ip_AsyncTransmit everything works fine. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Hello, is there any further update on this topic? is there any example project available. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Unfortunately I can't post the project because I am only using S32DS to configure the RTD and to generate driver config files. But I was able to work through the issues and unsurprisingly it was a data cache issue with the DMA. as for the setup issues: didn't properly link the scatter gather channels. (each channel needs to link to the next one and last one needs to be marked as final) didn't have the tx/rx dma channels priorities correctly (rx higher than tx) didn't have the tx/rx dma channel complete interrupts prioritized correctly. (tx higher than rx) and the data cache issue boiled down to the MemMap.h files. nxp uses these defines: #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" /* Pointer to the DMA Initialization Configuration. Based on this configuration pointer, the DMA Driver obtains all information for the Logic Channels and corresponding Channel Configurations. The Pointer is loaded when Dma_Ip_Init() is called. */ static const Dma_Ip_InitType * Dma_Ip_pxInit; #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" and in the  _MemMap.h they define what the compiler should do. in this case #pragma GCC section bss ".mcal_bss_no_cacheable" #ifdef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE /** * @file Mcl_MemMap.h */ #undef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #define ENTERED_MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #ifndef MEMMAP_MATCH_ERROR #define MEMMAP_MATCH_ERROR #else #ifndef MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #error "MemMap.h, no valid matching start-stop section defined." #endif #endif /** * @file Mcl_MemMap.h */ #undef MEMMAP_ERROR #pragma GCC section bss ".mcal_bss_no_cacheable" #endif   for gcc unless you use the gcc version that comes with the s32ds ide or download their specific version of gcc these types of pragmas aren't supported. so for now i just went through all the rtd files that used dma and manually added the right section attributes to make them non-cacheable either .mcal_bss_no_cacheable or .mcal_data_no_cacheableso for the snippet above i had to add:   __attribute__((section(".mcal_bss_no_cacheable"))) static const Dma_Ip_InitType * Dma_Ip_pxInit; i replaced all the  _MemMap.h with empty dummy files to make the compiler happy which means i have to manually add all the __attribute__((section())) compiler directives. Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast Hi @not_a_duck, Could you share the project so that I can test it? Thank you, Daniel Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast correction: `Lpspi_Ip_LPSPI_0_IrqTxDmaHandler` actually does get called but only once. and then never again Re: S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast @PetrS or @davidtosenovjan do either of you have any suggestions on what i can check? one additional thing i have noticed is that the dma interrupt for the tx channel is being called repeatedly. it is supposed to call Lpspi_Ip_LPSPI_0_IrqTxDmaHandler callback but it never does.

S32K344 SPI + DMA LPSPI_IP_异步传输快速 这个问题可能与以下问题类似： https://community.nxp.com/t5/S32K/S32K312-LPSPI-DMA-AsyncTransmitFast/mp/1923811 我必须向一个设备发送两个 spi 事务。我正在尝试使用 Lpspi_Ip_AsyncTransmitFast。 const Lpspi_Ip_FastTransferType ft[] = { { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf_wren, .RxBuffer = rxbuf_wren, .DefaultData = 0, .Length = 1, .KeepCs = false, }, { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf, .RxBuffer = rxbuf, .DefaultData = 0, .Length = 10, .KeepCs = false, } }; void send_spi_txn(void) { Lpspi_Ip_StatusType status = Lpspi_Ip_AsyncTransmitFast( ft, 2, Lpspi_Ip_Callback_lpspi_0_dma ); if (status != LPSPI_IP_STATUS_SUCCESS) { failed_spi_dma = true; } } 我已经测试过使用 Lpspi_Ip_AsyncTransmit 发送单个事务，然后从完成回调发送另一个事务，但这显然不是理想的，所以希望能够使用传输列表。 问题是没有数据被发送。第一次调用 Lpspi_Ip_AsyncTransmitFast 时报告成功，但后续每次调用都失败。还可以看到没有 spi 传输。在逻辑分析仪上，但是当我只执行 Lpspi_Ip_AsyncTransmit 时，一切工作正常。 回复：S32K344 SPI + DMA LPSPI_IP_AsyncTransmitFast 不幸的是我无法发布该项目，因为我只使用 S32DS 来配置 RTD 和生成驱动程序配置文件。 但我能够解决这些问题，不出所料，这是 DMA 的数据缓存问题。 至于设置问题： 没有正确链接散射聚集通道。（每个频道都需要链接到下一个频道，最后一个频道需要标记为最终频道） 没有正确设置 tx/rx dma 通道优先级（rx 高于 tx） 没有正确确定 tx/rx dma 通道完成中断的优先级。（tx 高于 rx） 数据缓存问题归结于 MemMap.h文件。 nxp 使用以下定义： #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" /* Pointer to the DMA Initialization Configuration. Based on this configuration pointer, the DMA Driver obtains all information for the Logic Channels and corresponding Channel Configurations. The Pointer is loaded when Dma_Ip_Init() is called. */ static const Dma_Ip_InitType * Dma_Ip_pxInit; #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" 并且在 _MemMap.h它们定义了编译器应该做什么。在这种情况下 #pragma GCC 部分 bss “.mcal_bss_no_cacheable” #ifdef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE /** * @file Mcl_MemMap.h */ #undef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #define ENTERED_MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #ifndef MEMMAP_MATCH_ERROR #define MEMMAP_MATCH_ERROR #else #ifndef MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #error "MemMap.h, no valid matching start-stop section defined." #endif #endif /** * @file Mcl_MemMap.h */ #undef MEMMAP_ERROR #pragma GCC section bss ".mcal_bss_no_cacheable" #endif   对于 gcc，除非您使用 s32ds ide 附带的 gcc 版本或下载其特定版本的 gcc，否则不支持这些类型的编译指示。 所以现在我只是检查了所有使用 dma 的 rtd 文件，并手动添加了正确的部分属性，使它们不可缓存 .mcal_bss_no_cacheable 或者 .mcal_data_no_cacheableso 对于上面的代码片段我必须添加：   __attribute__((section(".mcal_bss_no_cacheable"))) static const Dma_Ip_InitType * Dma_Ip_pxInit; 我更换了所有 _MemMap.h 使用空的虚拟文件来使编译器满意，这意味着我必须手动添加所有__attribute__ ((section())) 编译器指令。 回复：S32K344 SPI + DMA LPSPI_IP_AsyncTransmitFast 更正：` Lpspi_Ip_LPSPI_0_IrqTxDmaHandler`实际上确实被调用了，但只调用了一次，之后就再也没有调用过了。 回复：S32K344 SPI + DMA LPSPI_IP_AsyncTransmitFast @PetrS或@davidtosenovjan你们对我可以检查什么有什么建议吗？ 我注意到的另一件事是，tx 通道的 dma 中断被重复调用。它应该调用 Lpspi_Ip_LPSPI_0_IrqTxDmaHandler 回调，但它从来没有调用过。

PCA9509P VOL on PORT A Hello team, What is is the meaning of "Iload=100µA"  in table 6? Is the test circuit shown in Figure 20, with RL=1.35kohms  used for this characterization? Best regards. Sylvain Re: PCA9509P VOL on PORT A Hello Thomas, As the solution will  be implemented in a design, I need an "official answer" from NXP. The answer “I don't think so” is not safe from my point of view  :-). An answer starting with “yes/no 100µA is a strict requirement” will be appreciated. Regards Re: PCA9509P VOL on PORT A Hello Sylvain, I do not think that 100μA is a strict requirement. Please try increasing the pull-up resistor on Port A to reduce the current and check if your VOL improves while keeping rise times within acceptable limits for your application. BRs, Tomas Re: PCA9509P VOL on PORT A Hello, I need some recommandations about Pullup on port A: In paragraph 6.4.1.2, it's written that he pull-up resistor on the A side of the PCA9509P should be chosen to provide at least 100 μA of pull-up current. Is-it mandatory to respect this condition? In my application the VIL of of the master is 0.3XVCC where as the VOL (side A)of PCA9509P is  0.25VCCA (maximum value). The power supply is 1.8V. so VIL(min)=0.3*1.8=0.54V and VOL(max)@100µA=0.25*1.8 =0.45V The margin is : VIL(min)-VOL(max)= 0.54-0.45=0.09V. This margin is very small, so I think that if I reduce  current in port A, the VOL of Port A will be also reduced and the margin will increased. isn't it? Sylvain     Re: PCA9509P VOL on PORT A Hello Sylvain, The PCA9509P is relatively old device and I did not find the relevant test details/results. However, I assume that the "Iload = 100µA" in Table 6 specifies the test condition under which the VOL on Port A was characterized. When the device is driving the output low, it must maintain the VOL value while sinking a current of 100µA. I do not think the circuit in Figure 20 was used directly for the VOL test in Table 6. The load current would be in mA range which significantly exceeds the 100µA condition specified for VOL characterization. BRs, Tomas

QorIQ LS1088A(rdb) increasing the CORE frequency from 1.2 GHz to 1.6 GHz Hello experts, I have LS1088a based custom board. When I power on the device, the processor clock configuration in u-boot(boot by SD) is running at 1.2 GHz.  SoC: LS1088AE Rev1.0 (0x87030010) Clock Configuration: CPU0(A53):1200 MHz CPU1(A53):1200 MHz CPU2(A53):1200 MHz CPU3(A53):1200 MHz CPU4(A53):1200 MHz CPU5(A53):1200 MHz CPU6(A53):1200 MHz CPU7(A53):1200 MHz Bus: 500 MHz DDR: 1600 MT/s How do I increase the core frequency to 1.6GHz? If the clock configuration is related to RCW, which document and which section should I review?  Some components were used differently compared to the reference design. If you have any questions about these, I will get back to you immediately. Thank you. Re: QorIQ LS1088A(rdb) increasing the CORE frequency from 1.2 GHz to 1.6 GHz The DDR controller configuration parameters are different when DDR data rate are 2100 MT/s and 1900 MT/s.  Please use QCVS DDRv tool to connect to the target board to do DDR validation and optimization to get DDR controller configuration parameters at 2100 MT/s DDR data rate. Then use these parameters to modify plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c according to the file generated by QCVS DDR tool. You could create a new thread to continue to discuss DDR validation issue. Re: QorIQ LS1088A(rdb) increasing the CORE frequency from 1.2 GHz to 1.6 GHz @yipingwang Thank you for your support. CPU runs 1.6GHz and I increased DDR data rate to 1900 MT/s at now.  Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz CPU4(A53):1600 MHz CPU5(A53):1600 MHz CPU6(A53):1600 MHz CPU7(A53):1600 MHz Bus: 500 MHz DDR: 1900 MT/s When I try to 2100 MT/s data rate (MEM_PLL_RAT=21), I got this error: ERROR: Found training error(s): 0x2000 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. NOTICE: Incorrect DRAM0 size is defined in platfor_def.h ERROR: mmap_add_region_check() failed. error -22 ERROR: mmap_add_region_check() failed. error -22 I looked through the LS1088ARM document a bit, but I couldn't see the exact value ranges. What values ​​do I need to assign to work at a data rate of 2100 MT/s? Sys PLL Ref clock:100MHz and My current RCW values ​​are as follows: SYS_PLL_RAT=7 /* 5 */ MEM_PLL_RAT=21 CGA_PLL1_RAT=16 CGA_PLL2_RAT=16 HWA_CGA_M1_CLK_SEL=2 HWA_CGA_M2_CLK_SEL=1 DDR_REFCLK_SEL=2 DRAM_LAT=1 Re: QorIQ LS1088A(rdb) increasing the CORE frequency from 1.2 GHz to 1.6 GHz Please configure the following fields in RCW, please refer to "4.8.7.8.1 RCW" in LS1088ARM. CGA_PLL1_RAT CGA_PLL2_RAT For example, Sys PLL Ref clock:100MHz CGA_PLL1_RAT=16 CGA_PLL2_RAT=16

QorIQ LS1088A(rdb)により、CORE周波数が1.2GHzから1.6GHzに増加 専門家の皆さん、こんにちは。 LS1088aベースのカスタムボードを持っています。デバイスの電源を入れると、u-boot(boot by SD) のプロセッサクロックコンフィギュレーションが1.2GHzで実行されています。 SoC: LS1088AE Rev1.0 (0x87030010) Clock Configuration: CPU0(A53):1200 MHz CPU1(A53):1200 MHz CPU2(A53):1200 MHz CPU3(A53):1200 MHz CPU4(A53):1200 MHz CPU5(A53):1200 MHz CPU6(A53):1200 MHz CPU7(A53):1200 MHz Bus: 500 MHz DDR: 1600 MT/s コア周波数を1.6GHzに上げるにはどうすればよいですか?クロック設定が RCW に関連している場合、どのドキュメントとどのセクションを確認する必要がありますか。 一部のコンポーネントは、リファレンス デザインとは異なる方法で使用されていました。これらについてご不明な点がございましたら、すぐにご連絡いたします。 ありがとうございます。 Re: QorIQ LS1088A(rdb) の CORE 周波数を 1.2 GHz から 1.6 GHz に増加 DDR データ速度が 2100 MT/s と 1900 MT/s の場合、DDR コントローラの設定パラメータは異なります。 QCVS DDRvツールを使用してターゲットボードに接続し、DDRの検証と最適化を行い、2100 MT / sのDDRデータレートでDDRコントローラー構成パラメーターを取得してください。 次に、これらのパラメータを使用して、QCVS DDRツールによって生成されたファイルに従ってplat/nxp/soc-ls1088a/ls1088ardb/ddr_init.cを変更します。 新しいスレッドを作成して、DDR 検証の問題について引き続き説明できます。 Re: QorIQ LS1088A(rdb) の CORE 周波数を 1.2 GHz から 1.6 GHz に増加 @yipingwangご支援のほど、よろしくお願いいたします。CPUは1.6GHzで動作し、DDRデータレートを1900 MT / sに増やしました。 Clock Configuration: CPU0(A53):1600 MHz CPU1(A53):1600 MHz CPU2(A53):1600 MHz CPU3(A53):1600 MHz CPU4(A53):1600 MHz CPU5(A53):1600 MHz CPU6(A53):1600 MHz CPU7(A53):1600 MHz Bus: 500 MHz DDR: 1900 MT/s 2100 MT/sのデータレート(MEM_PLL_RAT=21)にしようとすると、次のエラーが発生します。 ERROR: Found training error(s): 0x2000 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. NOTICE: Incorrect DRAM0 size is defined in platfor_def.h ERROR: mmap_add_region_check() failed. error -22 ERROR: mmap_add_region_check() failed. error -22 LS1088ARMドキュメントを少し調べましたが、正確な値の範囲はわかりませんでした。2100 MT/秒のデータレートで作業するには、どの値を割り当てる必要がありますか? Sys PLL 参照クロック:100MHzおよび 私の現在のRCW値は次のとおりです。 SYS_PLL_RAT=7 /* 5 */ MEM_PLL_RAT=21 CGA_PLL1_RAT=16 CGA_PLL2_RAT=16 HWA_CGA_M1_CLK_SEL=2 HWA_CGA_M2_CLK_SEL=1 DDR_REFCLK_SEL=2 DRAM_LAT=1 Re: QorIQ LS1088A(rdb) の CORE 周波数を 1.2 GHz から 1.6 GHz に増加 RCWで以下のフィールドを設定してください、LS1088ARMの「4.8.7.8.1 RCW」を参照してください。 CGA_PLL1_RAT CGA_PLL2_RAT 例えば、Sys PLL Ref clock:100MHz CGA_PLL1_RAT=16 CGA_PLL2_RAT=16

S32K146 CSEc strict mode code size update Hi, We are developing a solution in which we need to enable CSEc strict mode. When we do, by using the boot flavor '00' in the command CMD_BOOT_DEFINE, everything works fine. However, after rebooting, if we update our boot loader and we try to define a new BOOT_SIZE, the command fails with code 0x800. Even if we try to update with the same BOOT_SIZE, the command fails, no matter the Boot Flavor we use in the command. If we ignore the error and reboot, the part is bricked (even using the same BOOT_SIZE and updating the MAC appropriately). The same process works without issue if the Sequential Boot Method is selected. The documentation states that Strict mode is OTP, but that BOOT_SIZE can be changed. How can we update BOOT_SIZE in Strict mode? Thank you very much! Re: S32K146 CSEc strict mode code size update Thank you very much for clarifying this. Best regards, Carlos Re: S32K146 CSEc strict mode code size update Hi @sinixtek  the result is that the SIZE cannot be updated. The sentence in the manual is confusing, I asked to update it. Thanks for pointing this out. Regards, Lukas Re: S32K146 CSEc strict mode code size update Hi @lukaszadrapa , Thank you very much for your support, let's see what they say. Best regards, Carlos Re: S32K146 CSEc strict mode code size update Hi @sinixtek  That's a good question, I have never tried this use-case. It looks like you are the first one who is trying to change the BOOT_SIZE in strict boot mode. Please give me more time to clarify this. I will probably need to discuss this with another team, so it may take some time. At a glance, my guess is that it's not supported even if the documentation says something different. But let's wait for the result. Regards, Lukas

[K32w041/K32061]Is there an errata document? Does an errata document exist for the K32W041 or K32W061 processor? I want to know what problems exist in the hardware so I can create a more stable product. Examples I know of and which would be reason enough to publish such a document: - Brown out detection has a feature to reset the CPU, but will keep the CPU in reset forever until a hard reset or PAD RSTN. This makes this reset feature (almost) useless as a safety feature. - Synchronous ADC not supported? There are strong hints synchronous mode for the ADC is not supported, see the comment for ASYNMODE in K32W061.h: ASYNMODE - Select clock mode. 0: Synchronous mode. Not Supported. But User Manual UM11323 rev. 1.2 (the most recent from the NXP website) states: "Two clocking modes are available, synchronous mode and asynchronous mode." Re: [K32w041/K32061]Is there an errata document? Thanks, I was feeling stupid for not finding the document, but I see it's less than 1 month old. Re: [K32w041/K32061]Is there an errata document? Hello, Hope you are doing well. Here is the Errata Documentation available for the K32W061/K32W041: K32W061 Errata. There is also more documentation on its product page: K32W061/41.

[K32w041/K32061]正誤表はありますか? K32W041 または K32W061 プロセッサのエラータ文書は存在しますか? ハードウェアにどのような問題があるのかを知りたいので、より安定した製品を作ることができます。 私が知っている例と、そのような文書を公開するのに十分な理由となる例: - ブラウンアウト検出には CPU をリセットする機能がありますが、ハード リセットまたは PAD RSTN まで CPU は永久にリセットされたままになります。これにより、このリセット機能は安全機能として(ほとんど)役に立たなくなります。 - 同期ADCはサポートされていませんか?ADC の同期モードがサポートされていないという強いヒントがあります。K32W061.h の ASYNMODE のコメントを参照してください。 ASYNMODE - クロックモードを選択します。0: 同期モード。サポートされていません。 しかし、ユーザーマニュアルUM11323 rev. 1.2 (NXP の Web サイトからの最新版) には、「同期モードと非同期モードの 2 つのクロッキング モードが利用可能です」と記載されています。 Re: [K32w041/K32061]正誤表はありますか? おかげで、ドキュメントが見つからないのは愚かだと感じていましたが、1か月未満前のようです。

S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast この質問は、次の質問と似ているかもしれません https://community.nxp.com/t5/S32K/S32K312-LPSPI-DMA-AsyncTransmitFast/m-p/1923811  私はデバイスに2つのspiトランザクションを送信する必要があります。Lpspi_Ip_AsyncTransmitFastを使おうとしています。 const Lpspi_Ip_FastTransferType ft[] = { { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf_wren, .RxBuffer = rxbuf_wren, .DefaultData = 0, .Length = 1, .KeepCs = false, }, { .ExternalDevice = &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0, .TxBuffer = txbuf, .RxBuffer = rxbuf, .DefaultData = 0, .Length = 10, .KeepCs = false, } }; void send_spi_txn(void) { Lpspi_Ip_StatusType status = Lpspi_Ip_AsyncTransmitFast( ft, 2, Lpspi_Ip_Callback_lpspi_0_dma ); if (status != LPSPI_IP_STATUS_SUCCESS) { failed_spi_dma = true; } }   私はすでにLpspi_Ip_AsyncTransmitを使用して単一のトランザクションを送信し、次に完了コールバックから別のトランザクションを送信することをテストしましたが、これは明らかに理想的ではないので、代わりにtransferlistを使用できるようにしたいと思います。 問題は、データが送信されていないことです。初めて Lpspi_Ip_AsyncTransmitFast が呼び出されたときは成功が報告されますが、その後のすべての呼び出しは失敗します。また、SPI転送がないことも確認できます。ロジックアナライザーでは、しかし私がただLpspi_Ip_AsyncTransmitとき、すべてが正常に動作します。 日時:S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast 残念ながら、S32DSを使用してRTDを構成し、ドライバー構成ファイルを生成しているだけなので、プロジェクトを投稿することはできません。 しかし、私は問題を解決することができました、そして当然のことながら、それはDMAのデータキャッシュの問題でした。 セットアップの問題については、次のようにします。 スキャッターギャザーチャンネルが正しくリンクされていませんでした。(各チャンネルは次のチャンネルにリンクする必要があり、最後のチャンネルは最終としてマークする必要があります) TX/RX DMA チャネルの優先順位が正しくありませんでした (Rx が Tx よりも高い) TX/RX DMA チャネルの完全割り込みの優先順位が正しく設定されていませんでした。(tx が rx より高い) そして、データキャッシュの問題はMemMap.hに要約されますファイル。 NXPは、以下の定義を使用します。 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" /* Pointer to the DMA Initialization Configuration. Based on this configuration pointer, the DMA Driver obtains all information for the Logic Channels and corresponding Channel Configurations. The Pointer is loaded when Dma_Ip_Init() is called. */ static const Dma_Ip_InitType * Dma_Ip_pxInit; #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #include "Mcl_MemMap.h" そして  _MemMap.h この場合 #pragma GCCセクションbss ".mcal_bss_no_cacheable" #ifdef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE /** * @file Mcl_MemMap.h */ #undef MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #define ENTERED_MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #ifndef MEMMAP_MATCH_ERROR #define MEMMAP_MATCH_ERROR #else #ifndef MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE #error "MemMap.h, no valid matching start-stop section defined." #endif #endif /** * @file Mcl_MemMap.h */ #undef MEMMAP_ERROR #pragma GCC section bss ".mcal_bss_no_cacheable" #endif   GCC の場合、S32DS IDE に付属している GCC バージョンを使用するか、特定のバージョンの GCC をダウンロードしない限り、これらの種類のプラグマはサポートされていません。 だから今のところ、私はDMAを使用していたすべてのRTDファイルを調べ、手動で適切なセクション属性を追加して、それらをキャッシュ不可にするか .mcal_bss_no_cacheable または .mcal_data_no_cacheableso上記のスニペットのために追加しなければなりませんでした。   __attribute__((section(".mcal_bss_no_cacheable"))) static const Dma_Ip_InitType * Dma_Ip_pxInit; コンパイラを満足させるために、すべての  _MemMap.h を空のダミーファイルに置き換えました。つまり、すべての __attribute__（((section()))コンパイラディレクティブを手動で追加する必要があります。 日時:S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast 訂正: 'Lpspi_Ip_LPSPI_0_IrqTxDmaHandler' は実際には呼び出されますが、一度だけ呼び出されます。その後は二度と呼び出されません 日時:S32K344 SPI + DMA Lpspi_Ip_AsyncTransmitFast @PetrSまたは@davidtosenovjan、どちらかが私が確認できるものについて何か提案がありますか? さらに、TX チャネルの DMA 割り込みが繰り返し呼び出されていることに気付きました。コールバックを呼び出すことになっていますがLpspi_Ip_LPSPI_0_IrqTxDmaHandler決して呼び出しません。

S32G3 serial RCON Hi, I am reviewing the serial RCON configuration. In the RMS32G3 manual, section 31.3.2.3, it mentions using RCON[7:8] to connect to the EEPROM. However, in AN13456 (S32G3 Boot Process), section 5.4, it states that the BootROM assumes the EEPROM is connected to RCON8 and RCON9. Could you please clarify this discrepancy? Thanks, XD Re: S32G3 serial RCON Dear @XD , Thanks for contacting NXP support. After reviewing the information, we confirm that you should follow the instructions in the RMS32G3 manual. The configuration mentioned in that manual is the correct one for your reference. If you have any further questions, please don't hesitate to contact us. Best regards, Celeste

freemaster 仪表板变量输入 在 freemaster 软件中，我无法从该变量的仪表板输入中覆盖监视变量部分中的虚拟变量。 请澄清！ <meta charset="UTF-8" /> <meta name="viewport" content="width=device-width, initial-scale=1.0" /> PWM Dashboard PWM Dashboard var01inc: Copyright 2020 NXP var i_var01inc; var s_status; function main() { i_var01inc = document.getElementById("input_var01inc"); s_status = document.getElementById("span_status"); // Check if FreeMASTER is available if (!pcm) { s_status.innerText = "ERROR: FreeMASTER not initialized!"; return; } // Display a message that FreeMASTER has initialized correctly console.log("FreeMASTER initialized. Ready to write variable."); } function writevar() { var v = i_var01inc.value; // Get the input value for var01inc // Attempt to write to FreeMASTER's virtual variable if (pcm.WriteVariable("var01inc", v)) { s_status.innerText = "Written: " + v; } else { s_status.innerText = "ERROR: " + pcm.LastRetMsg; } console.log("Attempting to write value: ", v); }

Mem_43_InFls Dependent files I am trying to configure the memory stack function of the S32K311 using the EB tool, and added Mem_43_InFls modules, but when compiling, I get an error that the files such as C40_Ip_Cfg.h, Mem_43_INFLS_Cfg.h and so on cannot be found. Looking at the manual, you can see that it needs to be manually generated, but I would appreciate how to do it and if someone can provide guidance. Re: Mem_43_InFls Dependent files Hi @ZMY666777, Before the project is compiled, the code must be generated. Refer to the documentation here: https://www.elektrobit.com/products/ecu/eb-tresos/evaluation-package/getting-started/ BR, Daniel

freemaster dashboard variable input In freemaster software i am unable to overwrite a virtual variable in the watch variabe section from the dashboard input for that variable. Kindly Clarify! <meta charset="UTF-8" /> <meta name="viewport" content="width=device-width, initial-scale=1.0" /> PWM Dashboard PWM Dashboard var01inc: Copyright 2020 NXP var i_var01inc; var s_status; function main() { i_var01inc = document.getElementById("input_var01inc"); s_status = document.getElementById("span_status"); // Check if FreeMASTER is available if (!pcm) { s_status.innerText = "ERROR: FreeMASTER not initialized!"; return; } // Display a message that FreeMASTER has initialized correctly console.log("FreeMASTER initialized. Ready to write variable."); } function writevar() { var v = i_var01inc.value; // Get the input value for var01inc // Attempt to write to FreeMASTER's virtual variable if (pcm.WriteVariable("var01inc", v)) { s_status.innerText = "Written: " + v; } else { s_status.innerText = "ERROR: " + pcm.LastRetMsg; } console.log("Attempting to write value: ", v); } Re: freemaster dashboard variable input Hello,  your script works well on my side. Please remember that the variable needs to be modifiable: Also note that current version of FreeMASTER will not update the variable value in the Watch view until you open the communication port. This issue will be fixed in the upcoming release - the virtual variables will not need a port being open at all and their value will refresh variable watch views. Regards, Michal

FreeMasterダッシュボード変数入力 freemasterソフトウェアでは、その変数のダッシュボード入力から時計の変数セクションの仮想変数を上書きすることはできません。 親切に明確にしてください! <meta charset="UTF-8" /> <meta name="viewport" content="width=device-width, initial-scale=1.0" /> PWM Dashboard PWM Dashboard var01inc: Copyright 2020 NXP var i_var01inc; var s_status; function main() { i_var01inc = document.getElementById("input_var01inc"); s_status = document.getElementById("span_status"); // Check if FreeMASTER is available if (!pcm) { s_status.innerText = "ERROR: FreeMASTER not initialized!"; return; } // Display a message that FreeMASTER has initialized correctly console.log("FreeMASTER initialized. Ready to write variable."); } function writevar() { var v = i_var01inc.value; // Get the input value for var01inc // Attempt to write to FreeMASTER's virtual variable if (pcm.WriteVariable("var01inc", v)) { s_status.innerText = "Written: " + v; } else { s_status.innerText = "ERROR: " + pcm.LastRetMsg; } console.log("Attempting to write value: ", v); }