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i.MX93 parallel diaply interface Hi, I am designing a board with i.MX93 (MIMX9332CVVXMAC) that has to drive a RGB display with parallel interface. From config tool the data bit are lebelled data0-23 without reference to R,G,B channel. I have also looked at evb FRDM and TM050RDH03-41, unfortunately on FRDM the data are as in config tool and the schematic of TM050RDH03-41 is not provided. Is it possible to have such schematic for confirmig the pinout? Or can you confirm me that the 24 bits can be muxed between channels R G and B freely? Thank you, Enrico Re: i.MX93 parallel diaply interface Hi, Thank you for your interest in NXP Semiconductor products, Please see the TM050RDH03-41 display connector schematic, if you are interested in the full schematic, please create a technical case. JosephAtNXP_0-1789574219944.png Regards
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有人用TapLinx吗? 有人使用 NXP 的 TapLinx SDK 与 MIFARE 卡进行交互吗? 我对一些最简单的控制台应用程序示例很感兴趣。这个示例应用程序有点难用,因为它是一个带有大量功能的图形用户界面应用程序。 我想找一些功能最简化的控制台应用程序,它们只需要对卡进行读写操作、身份验证等。 如果是 Kotlin 示例就更好了,但 Java 示例也可以。 入门指南 Re: Anyone using TapLinx? 你好@reid88 TapLinx SDK 支持 MIFARE DESFire、Plus、Classic、Ultralight、NTAG 等。您可以通过以下方式查看设计资源: TapLinx SDK for MIFARE, NTAG, ICODE and UCODE | NXP 半导体
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i.MX95: A55 never completes power-up or power-down — stalls identically on two different boards Summary On a custom System Manager configuration for i.MX95, booting the A55 logical machine (LM1) hangs inside the shared driver function SRC_MixSoftPowerUp() (devices/MIMX9/drivers/fsl_src.c) for srcMixIdx = PWR_MIX_SLICE_IDX_A55P (index 11). SRC_MixPowerUpCompleted() never returns true, FUNC_STAT freezes in a mixed/inconsistent state, and SM's own WDOG2 eventually fires an FCCU reset. Critically, when the sequence is forced to do a full power-down-then-up cycle, the power-down request never completes either — the hardware does not respond to software power control for this mix in either direction. The same firmware stalls identically on two physically different boards (FRDM-IMX95 15x15/LPDDR4x and FRDM-IMX95-PRO 19x19/LPDDR5), while both boards' factory-shipped eMMC images boot to a full Linux userspace, so the silicon and boards themselves are demonstrably capable. I have been able to rule out a large number of candidate causes with concrete evidence (listed below) and would appreciate guidance on what remains. Environment Item Value SoC i.MX95 (B0) Boards FRDM-IMX95 (15x15, LPDDR4x) and FRDM-IMX95-PRO (19x19, LPDDR5) System Manager nxp-imx/imx-sm at lf-6.18.20-2.0.0-5-g3198944 SM config Custom (SMCT/.mex-generated), not mx95evk M33/SM status Fully working M7 status Fully working — SCMI, TRDC partitioning, STOP/SUSPEND/deep-idle, I2C, Ethernet MDIO all functional A55 (LM1) Fails as described Boot media tested SD and eMMC (identical results) Symptom A55 is booted on demand from M7 via SCMI_LmmBoot() (also reproducible manually with lm LM1 boot from the SM debug monitor). The SCMI call itself succeeds: status = 0 LM1 then reports SCMI_LMM_STATE_SUSPEND (state = 2) Execution stalls in SRC_MixSoftPowerUp() waiting on SRC_MixPowerUpCompleted(PWR_MIX_SLICE_IDX_A55P) FUNC_STAT remains frozen for 4,000,000+ poll iterations Left unbounded, SM's WDOG2 supervisory watchdog fires an FCCU reset (errId = 18), taking down the whole system including M7 Register evidence SRC_XSPR_CORTEXMIX_PLATFORM (mix index 11) FUNC_STAT freezes at 0x00001010 or 0x00001011 depending on entry state. Decoding the seven status fields in PWR_MIX_FUNC_STAT_PUP/PDN: Field Observed state PSW_STAT "up" pattern SSAR_STAT "up" pattern A55_HDSK_STAT "up" pattern SYSMAN_STAT "up" pattern RST_STAT "powered-down" pattern ISO_STAT "powered-down" pattern MEM_STAT "powered-down" pattern This is an inconsistent state that matches neither a fully-powered-up nor a fully-powered-down condition, and it does not advance. Hardware measurement A scope was placed on VDD_ARM (output caps C211–C215, after inductor L7, downstream of the discrete PPF5301 DCDC — this board has a genuine dedicated ARM rail). During an lm LM1 boot attempt: The rail is already live at ~0.92 V before the attempt It visibly drops during the attempt So this is a real, physically observable incomplete power transition, not purely a permissions/timing/software artifact. Most informative single data point Forcing the entire power-down-then-up cycle unconditionally for the A55P mix (bypassing the MEM_STAT == 0 gate — i.e. SLICE_SW_CTRL |= PDN_SOFT, wait PowerDownCompleted, SLICE_SW_CTRL &= ~PDN_SOFT, wait PowerUpCompleted) shows that even the explicit power-down request never completes. FUNC_STAT is unchanged for the entire wait. This suggests the problem sits below the SRC register interface — e.g. a GPC handshake precondition, a missing clock to the SRC block itself, or a board/PMIC response issue — rather than anything correctable in SRC_MixSoftPowerUp()'s own sequencing logic. Already investigated and ruled out (with evidence) PERF_A55 argument (3 → 0, ODV → PRK voltage level) — byte-identical failure at either value. Rules out a DVS/voltage-level mismatch. config_bctrl.h (SM_BCTRL_A_CONFIG / SM_BCTRL_W_CONFIG) — was empty in my config; populating it with mx95evk's values changed nothing. I then read the live registers on the working factory system via the SM monitor (BLK_CTRL_NS_AONMIX 0x44210008–0x44210024, BLK_CTRL_WAKEUPMIX 0x42420030–0x42420064) — every word matched the mx95evk reference exactly. SM_A55P_CONFIG, config_user.h, TRDC SRC/GPC/ANATOP grants, WDOG2 timeout — all confirmed identical to mx95evk, or confirmed not to be the blocker. (SM's own DOM2 TRDC access to these registers demonstrably works — I can read and write changing register values.) Note SM_A55P_CONFIG and SM_DDR_CONFIG are empty in mx95evk's own config too. SRC_MixIsPwrReady() guard — correct logic, but it legitimately returns false here (mixed bit state), so it never changes behaviour. Unconditional SRC_MixSetA55HdskMode(..., ACK_WAIT) — zero effect; A55_HDSK_STAT was already in the correct "up" pattern throughout. Newer SM firmware — diffed the pinned SRCREVs across the walnascar → whinlatter span: zero changes to devices/MIMX9/ (including fsl_src.c, dev_sm_cpu.c, dev_sm_power.c). uboot-imx differences — real differences exist across releases, but none touch PD_A55P/SRC_XSPR/A55 power-up. This is also true by construction: U-Boot SPL runs on A55, i.e. only after this power-up has already succeeded. ERR053228 analog (MTR_ACK_CTRL) — i.MX95 has a per-mix MTR_ACK_CTRL/MTR_ACK_STAT handshake (offset 0x90/0x94) whose reset default (CNT_MODE = 0) waits indefinitely for a hardware MTR ack, which looked like a plausible match for the stuck MEM_STAT. I wrote CNT_MODE = 3 (timeout mode) with max MTR_CNT_CFG before the power-up transition and confirmed via readback that the write takes effect (no LOCK_CFG interference). No change. Real factory AP binaries — extracted bl31.bin / tee.bin / u-boot* from this board's own known-good factory eMMC image and built them into my flash.bin. No change (expected, since the stall precedes U-Boot's first instruction). Fuses/OTP — ruled out: fuses are burned once per die, and the factory image and my image run on the same physical board. Boot medium — SD and eMMC both tested, identical. Factory SM binary provenance — this one I want to highlight, because it closes off "maybe NXP ships a different SM build". I extracted the factory eMMC's own M33 image (ROM container 3, image 3, CORE_CM33, container-relative offset 0x79000, size 0x2C800) using mkimage_imx8 -soc IMX9 -parse, and verified the extraction by exact SHA384 match against the container's own recorded hash. Its build banner reads:   Hello from SM (Build 819, Commit c450f539, Mar 09 2026 03:24:50)   c450f539 is confirmed (git merge-base --is-ancestor) to be a direct ancestor of my own build, and the only intervening commit touching fsl_src.c/dev_sm_cpu.c/dev_sm_power.c is pure test-scaffolding cleanup with no functional change. So the factory image that successfully boots A55 is running functionally the same SM source that fails for me. Questions Given that the factory image boots A55 with functionally identical SM source, what differs outside imx-sm source and the BCTRL register configuration that could gate A55P mix power-up? Specifically, is there AHAB/ELE container signing or provisioning metadata that affects whether the A55 platform mix can be powered up? Is the observed FUNC_STAT pattern (PSW/SSAR/A55_HDSK/SYSMAN up, RST/ISO/MEM down, not advancing) a known signature? What is the expected next transition from that state, and what drives it? Why would the explicit power-down request also never complete? That seems the strongest clue — what preconditions must hold for SRC_XSPR to respond to SLICE_SW_CTRL.PDN_SOFT at all for this mix? Is there a known i.MX95 B0 erratum affecting A55P mix power sequencing beyond ERR053228? Is there any required initialisation for the A55 platform mix that is present in the reference mx95evk flow but not expressed in the generated config_*.h files — i.e. something a custom SMCT-based config would silently omit? Notes JTAG is not available on the PRO board (no header), and I have chosen not to use the fragile 0.5 mm test pads on the 15x15 board. All diagnosis above was done via SM's own debug monitor (lm info, err, btime, md), direct register reads, and scope measurement. I have a containment fix in place (bounded waits replacing the original unbounded while (!SRC_MixPowerUpCompleted()) {;} loops) so that the failure now degrades gracefully to LM1 = suspended instead of watchdog-resetting the entire system. Happy to share that separately if useful. Re: i.MX95: A55 never completes power-up or power-down — stalls identically on two different boards Please disregard the post above and close the ticket... I just did a fresh build with wrynose and it works! My previous builds were with whinlatter (selected because that's what the FRDM-IMX95 shipped with), but that didn't work.
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Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz) Hello NXP Community, Our custom board (using the PCF85263A RTC and AM6252) reads the RTC time exactly once during the initial boot sequence using the following command: hwclock -u -s We are experiencing an intermittent issue where it fails to fetch the RTC value approximately 1 out of 1,000 times. (However, if it fails and we immediately retry the read command, it successfully fetches the time without any issues.) During our troubleshooting, we lowered the I2C clock frequency from 400kHz to 100kHz (400000 -> 100000) under the exact same conditions. After this change, we conducted nearly 6,000 test iterations and the system operated perfectly without a single failure. According to the PCF85263A datasheet, it supports a maximum I2C-bus frequency of 400kHz (Fast-mode). Could you please advise: Are there any known issues, errata, or similar historical reports regarding this intermittent I2C read failure with the PCF85263A at 400kHz? Are there any specific configurations, bus capacitance/pull-up resistor considerations, or debugging steps you would recommend to resolve this while maintaining the 400kHz clock? Thank you in advance for your support. Re: Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz) Hello Iseori, There are no known errata or documented hardware issues with the PCF85263A itself at 400 kHz I²C operation. The part is specified and production-tested up to 400 kHz, and the behavior you describe is a classic symptom of marginal timing compliance on the host controller or bus side rather than a defect in the PCF85263A. Recommended debugging steps: - Scope the I²C bus at 400 kHz and capture SCL/SDA waveforms. Verify that Tlow ≥ 1.3 µs, Thigh ≥ 0.6 µs, Tr ≤ 300 ns, and Tf ≤ 300 ns during the RTC read transaction. Compare against the timing requirements in Table 68 of the PCF85263A datasheet. - Check AM6252 errata for any known I²C 400 kHz SCL low-period violation. If present, reduce the I²C clock to 375–384 kHz, which typically restores full margin while remaining near 400 kHz in practice. - Review pull-up resistor values in your schematic. If they are higher than ~2.2 kΩ, replace with 1 kΩ–2.2 kΩ and re-test at 400 kHz. - Verify single-access reads: The PCF85263A requires that all time registers be read in a single I²C access to prevent roll-over corruption.  BRs, Tomas
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i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl GTK4 Window Startup Delay (~10s) on i.MX8MP with Vivante GPU When using the default GTK4 GL renderer: gtk_window_present(window);​ takes approximately 9-10 seconds before the window becomes visible. The evidence (see attached file) strongly suggests that the startup delay is not caused by GTK application code. The delay appears correlated with a blocking Vivante /dev/galcore ioctl within the GL rendering path. Software rendering (GSK_RENDERER=cairo) avoids the issue. We are looking for guidance on known issues, debugging methods, configuration changes, or fixes for GTK4/OpenGL startup latency on i.MX8MP with the Vivante GPU stack. Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl Hi @jim777  Thank you for sharing such detailed information. Could you provide a minimal, reproducible GTK4 source code example? I need to conduct further testing in the NXP BSP. Best Regards, Zhiming Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl Hi Zhiming, Thanks for your quick response! Attached is a small skeleton but complete source file to test. and the environment variables set before running: #!/bin/sh export XDG_RUNTIME_DIR=/run/user/0 export WAYLAND_DISPLAY=wayland-1 export GDK_BACKEND=wayland export GSK_RENDERER=gl  the relevant from weston.ini: root@nitrogen8mp:~# cat /etc/xdg/weston/weston.ini [core] #gbm-format=argb8888 use-g2d=true repaint-window=16 idle-time=0 xwayland=true #enable-overlay-view=1 [shell] panel-position=none [libinput] touchscreen_calibrator=true #[output] #name=HDMI-A-1 #mode=1920x1080@60 #transform=rotate-90 #[output] #name=HDMI-A-2 #mode=off # WIDTHxHEIGHT Resolution size width and height in pixels # off Disables the output # preferred Uses the preferred mode # current Uses the current crt controller mode #transform=rotate-90 [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize #start-on-startup=true [input-method] path=/usr/libexec/ibus-wayland the running time for the gtk_window_present on a desktop w/o GPU support takes some hundreds msec (< 1sec); and on the i.mx8mp device takes 9970 ms : root@nitrogen8mp:~# gtk4-test A: activate: before _present: 47333 ms B: activate: after _present: 57303 ms, takes: 9970 ms C: activate: after idele_add: 57303 ms D: startup_task_cb: 57315 ms ^C root@nitrogen8mp:~# I have tried render: ngl, which leads to smear image/widgetrs/video, and Vulkan leads to critical errors: Loader Message: vkCreateDevice: Failed to validate extensions in list; Failed to realize renderer of type ‘GskVulkanRenderer’ for surface ‘GdkWaylandToplevel’: Could not find a Vulkan device with the required features. Since out app need GPU support, and the recommended renderer under wayland/weston is still gl (UG10159  11.3.2.1 GL renderer)   , I hope you can help to find a solution. Best regards, Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl Hi @Zhiming_Liu  Besides what shared already, is there anything I can help to resolve the issue? If there is any way to make it work - significantly reduce the startup time, such as configuration changes, env variable settings, different versions, or fixes/patches to the GPU driver, please let me know. Thanks, Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl Hi @jim777  The GPU team is checking this issue, this will take a little while. I'll let you know as soon as there's an update. Best Regards, Zhiming
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使用硬件时钟(400kHz 对比 100kHz)的 PCF85263A 在启动时出现间歇性 I2C 读取失败 NXP社区的各位朋友,大家好! 我们的定制板(使用 PCF85263A RTC 和 AM6252)在初始启动序列期间使用以下命令读取一次 RTC 时间: hwclock -u -s 我们遇到了一个间歇性问题,大约每 1000 次操作中会有 1 次无法获取 RTC 值。 (但是,如果读取失败,我们立即重试READ命令,则可以成功获取时间,没有任何问题。) 在故障排除过程中,我们在完全相同的条件下将 I2C 时钟频率从 400kHz 降低到 100kHz (400000 -> 100000)。经过这一改变,我们进行了近 6000 次测试迭代,系统运行完美,没有出现任何故障。 根据 PCF85263A 数据手册,它支持的最大 I2C 总线频率为 400kHz(快速模式)。 请问您能否提供以下建议: 关于 PCF85263A 在 400kHz 频率下间歇性 I2C 读取失败的问题,是否有任何已知的错误、勘误或类似的历史报告? 在保持 400kHz 时钟频率的同时解决此问题,您有什么具体的配置、总线电容/上拉电阻方面的考虑因素或调试步骤可以推荐吗? 感谢您提前给予的支持。 Re: Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz) 你好,伊势里 PCF85263A 本身在 400 kHz I²C 操作下没有已知的错误或已记录的硬件问题。该器件的规格和生产测试均达到 400 kHz,您所描述的行为是主机控制器或总线侧时序一致性不足的典型症状,而不是 PCF85263A 的缺陷。 建议的调试步骤: - 以 400 kHz 的频率示波 I²C 总线,并捕获 SCL/SDA 波形。在 RTC 读取事务期间,验证 Tlow ≥ 1.3 µs、Thigh ≥ 0.6 µs、Tr ≤ 300 ns 和 Tf ≤ 300 ns。与 PCF85263A 数据手册表 68 中的时序要求进行比较。 - 检查 AM6252 勘误表,查看是否存在已知的 I²C 400 kHz SCL 低电平期间违例。如果存在,请将 I²C 时钟频率降低到 375–384 kHz,这样通常可以恢复全部裕量,同时在实践中保持在接近 400 kHz 的频率。 - 检查原理图中上拉电阻的值。如果阻值高于约 2.2 kΩ,则替换为 1 kΩ–2.2kΩ,并在 400 kHz 下重新测试。 - 验证单次读取:PCF85263A 要求所有时间寄存器必须在一次 I²C 访问中读取完毕,以防止数据溢出损坏。 BRs,托马斯
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i.mx8mp GPU 和 GTK4 应用程序:GUI/窗口呈现延迟和阻塞 Vivante /dev/galcore ioctl 在配备 Vivante GPU 的 i.MX8MP 上,GTK4 窗口启动延迟约为 10 秒。 使用默认的 GTK4 GL 渲染器时: gtk_window_present(window);​ 大约需要9-10 秒才能看到窗口。 证据(见附件)强烈表明,启动延迟并非由 GTK 应用程序代码引起。 延迟似乎与 GL 渲染路径中的 Vivante /dev/galcore ioctl 阻塞有关。软件渲染(GSK_RENDERER=cairo)可以避免这个问题。 我们正在寻找有关 i.MX8MP 搭载 Vivante GPU 堆栈时 GTK4/OpenGL 启动延迟的已知问题、调试方法、配置更改或修复方案的指导。 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl 嗨@jim777 感谢您分享如此详细的信息。能否提供一个最小的、可复现的 GTK4 源代码示例?我需要对 NXP BSP 进行进一步测试。 此致, 志明 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl 嗨志明, 感谢您的快速回复! 附件是一个小型但完整的源文件框架,供测试使用。 以及运行前设置的环境变量: #!/bin/sh export XDG_RUNTIME_DIR=/run/user/0 export WAYLAND_DISPLAY=wayland-1 export GDK_BACKEND=wayland export GSK_RENDERER=gl 来自 weston.ini 的相关内容: root@nitrogen8mp:~# cat /etc/xdg/weston/weston.ini [core] #gbm-format=argb8888 use-g2d=true repaint-window=16 idle-time=0 xwayland=true #enable-overlay-view=1 [shell] panel-position=none [libinput] touchscreen_calibrator=true #[output] #name=HDMI-A-1 #mode=1920x1080@60 #transform=rotate-90 #[output] #name=HDMI-A-2 #mode=off # WIDTHxHEIGHT Resolution size width and height in pixels # off Disables the output # preferred Uses the preferred mode # current Uses the current crt controller mode #transform=rotate-90 [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize #start-on-startup=true [input-method] path=/usr/libexec/ibus-wayland 在没有GPU支持的台式机上,gtk_window_present的运行时间需要几百毫秒(< 1秒);而在i.mx8mp设备上,则需要9970毫秒: root@nitrogen8mp:~# gtk4-test A: activate: before _present: 47333 ms B: activate: after _present: 57303 ms, takes: 9970 ms C: activate: after idele_add: 57303 ms D: startup_task_cb: 57315 ms ^C root@nitrogen8mp:~# 我尝试过 render: ngl,但会导致图像/控件/视频模糊;而Vulkan 会导致严重错误:加载器消息:vkCreateDevice:验证列表中的扩展失败;无法为表面“GdkWaylandToplevel”实现类型为“GskVulkanRenderer”的渲染器:找不到具有所需功能的 Vulkan 设备。 由于我们的应用程序需要 GPU 支持,而 Wayland/Weston 下推荐的渲染器仍然是 GL(UG10159 11.3.2.1 GL 渲染器),希望您能帮忙找到解决方案。 此致, Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl 嗨@Zhiming_Liu 除了已经分享的信息之外,还有什么我可以帮忙解决这个问题的吗? 如果有什么方法可以显著缩短启动时间,例如更改配置、设置环境变量、使用不同的版本,或者修复/修补 GPU 驱动程序,请告诉我。 谢谢, Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl 嗨@jim777 GPU团队正在调查此问题,这需要一些时间。有最新消息我会第一时间通知你。 此致, 志明
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MCU P89C52X2BNフラッシュするにはどうすればいいですか? こんにちは、皆さん。 P89C52X2BNとP89C52RD2という2つの古いMCUをプログラムする必要があります。 P89C52RD2については、シリアル経由でISPをサポートしていると理解しています。しかし、ISP/IAPプロトコルをアクティブ化する方法はまだわかっていません。 P89C52X2BNの場合、どのようにファームウェアを書き換えればよいですか?並列プログラマが必要ですか?必要であれば、どのようなプロトコルを使用し、フラッシュモードをアクティブ化すればよいでしょうか? 主にこれら2つのチップ(特にX2BN)の公式プログラミングドキュメントを探しています。正しいフラッシュプログラミングインターフェースとタイミングを参照できるようにするためです。データシートのプログラミングに関するセクション、またはリンクをお持ちでしたら、ぜひ共有してください。 ありがとう! Re: How to Flash P89C52X2BN MCU? Hello ご不便をおかけし申し訳ありません。P89C52ファミリーは現在製造中止で、そのためサポートも終了しており、このファミリーに関する情報はもはや利用できません。 もしあなたに合うなら、89C51の情報があります;重要:この情報がいつ有効か確認・テストすることはできませんし、89C52の申請もできません。 89C51Rx+/Rx2/66xマイクロコントローラの回路内およびアプリケーション内プログラミング よろしくお願いいたします。 Re: How to Flash P89C52X2BN MCU? 申し訳ありませんが、XSP6100Nは非常に高価で、平均的な人の6~12か月分の給料に相当します。だから、ドキュメントを読んで、自分でフラッシュしてみようと思います。XSP6100Nできますが、払えません、ありがとう。 Re: How to Flash P89C52X2BN MCU? このANNはP89C5xRx2に使えますが、P89C5xX2が欠けています。このANは正しいタイプのドキュメントですが、P89C5xX2が欠けているだけです。ありがとう!
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i.mx8mp GPUとGTK4アプリ:GUI/ウィンドウ表示遅延とVivante /dev/galcore ioctlのブロック Vivante GPUを搭載したi.MX8MPでのGTK4ウィンドウ起動遅延(約10秒) デフォルトのGTK4 GLレンダラーを使用する場合: gtk_window_present(window);​ ウィンドウが表示されるまでには約9~10秒かかります。 証拠(添付ファイル参照)は、起動遅延がGTKアプリケーションコードによるものではないことを強く示唆しています。 この遅延は、GLレンダリングパス内のVivante /dev/galcore ioctlのブロッキングと関連しているようです。ソフトウェアレンダリング(GSK_RENDERER=カイロ)はこの問題を回避します。 Vivante GPUスタックを用いたi.MX8MPでのGTK4/OpenGL起動**レイテンシ**に関する既知の問題、デバッグ方法、設定変更、または修正方法について のガイダン スを探しています。 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは、 @jim777さん 詳細な情報を共有していただき、ありがとうございます。最小限で再現可能なGTK4のソースコード例を教えてもらえますか?NXP BSPでさらにテストを実施する必要があります。 よろしくお願いします、 志明 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは、志明さん 迅速なご対応ありがとうございます! テスト用の、骨組みは小さいながらも完全なソースファイルを添付しました。 実行前に設定された環境変数: #!/bin/sh export XDG_RUNTIME_DIR=/run/user/0 export WAYLAND_DISPLAY=wayland-1 export GDK_BACKEND=wayland export GSK_RENDERER=gl weston.ini からの関連情報: root@nitrogen8mp:~# cat /etc/xdg/weston/weston.ini [core] #gbm-format=argb8888 use-g2d=true repaint-window=16 idle-time=0 xwayland=true #enable-overlay-view=1 [shell] panel-position=none [libinput] touchscreen_calibrator=true #[output] #name=HDMI-A-1 #mode=1920x1080@60 #transform=rotate-90 #[output] #name=HDMI-A-2 #mode=off # WIDTHxHEIGHT Resolution size width and height in pixels # off Disables the output # preferred Uses the preferred mode # current Uses the current crt controller mode #transform=rotate-90 [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize #start-on-startup=true [input-method] path=/usr/libexec/ibus-wayland GPUサポートのないデスクトップでのgtk_window_presentの実行時間は数百ミリ秒(<1秒)かかります。そしてi.mx8MPデバイスでは9970ミリ秒かかります: root@nitrogen8mp:~# gtk4-test A: activate: before _present: 47333 ms B: activate: after _present: 57303 ms, takes: 9970 ms C: activate: after idele_add: 57303 ms D: startup_task_cb: 57315 ms ^C root@nitrogen8mp:~# render: nglを試しましたが、画像やウィジェット、動画のにじみが生じてしまい、 Vulkanが重大なエラーを引き起こす:ローダーメッセージ:vkCreateDevice:リスト内の拡張を検証できません;表面の「GdkWaylandToplevel」に対してタイプ「GskVulkanRenderer」のレンダラーを実装できません:必要な機能を持つVulkanデバイスを見つけられませんでした。 私たちのアプリにはGPUサポートが必要で、Wayland/Westonで推奨されているレンダラーはまだGL(UG10159 11.3.2.1 GLレンダラー)なので、解決策を見つける手助けをいただければ幸いです。 よろしくお願いします、 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは@Zhiming_Liu  すでに共有されたこと以外に、この問題を解決するために私にできることはありますか? もしうまくいく方法があれば、起動時間を大幅に短縮してください。例えば設定の変更、環境変数の設定、バージョンの違い、GPUドライバーの修正やパッチについて教えてください。 ありがとうございます。 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは@jim777  GPUチームがこの問題を調査中で、少し時間がかかります。最新情報が入り次第、お知らせします。 よろしくお願いします、 志明
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PCF85263Aをハードウェアクロック(400kHz vs 100kHz)で使用した場合、起動時にI2C読み取りエラーが断続的に発生する。 こんにちは、NXPコミュニティの皆さん、 当社独自のボード(PCF85263A RTCとAM6252を使用)は、初期起動シーケンス中に以下のコマンドを使用してRTC時刻を一度だけ読み取ります。 hwclock -u -s 約1,000回に1回の割合で、RTC値の取得に失敗するという断続的な問題が発生しています。 (ただし、もし失敗してすぐに読み取りコマンドを再試行した場合、問題なく時刻を取得できます。) トラブルシューティングの過程で、全く同じ条件下でI2Cクロック周波数を400kHzから100kHz(400000→100000)に下げました。この変更後、約6,000回のテストを繰り返し実施しましたが、システムは一度も故障することなく完璧に動作しました。 PCF85263Aのデータシートによると、最大I2Cバス周波数400kHz(ファストモード)をサポートしています。 何かアドバイスをいただけますか: PCF85263Aを400kHzで使用した場合に発生する、この断続的なI2C読み取りエラーに関して、既知の問題、エラー、または同様の過去の報告はありますか? 400kHzクロックを維持しつつ解決するために、特定の構成やバスの静電容量/プルアップ抵抗の考慮点、またはデバッグの手順があれば教えてください。 あらかじめサポートに感謝いたします。 Re: Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz) こんにちは、伊勢織さん。 PCF85263A自体には、400kHzのI²C動作において、既知の不具合や文書化されたハードウェアの問題はありません。この部品は400kHzまで仕様・生産テストされており、あなたが述べた挙動は、PCF85263Aの欠陥というよりも、ホストコントローラやバス側のタイミング準拠が限界的であることの典型的な症状です。 推奨されるデバッグ手順: - I²Cバスを400kHzでオシロスコープし、SCL/SDA波形をキャプチャします。RTC読み出しトランザクション中に、Tlow ≥ 1.3 µs、Thigh ≥ 0.6 µs、Tr ≤ 300 ns、および Tf ≤ 300 ns であることを確認してください。PCF85263Aのデータシートの表68に記載されているタイミング要件と比較してください。 - AM6252の正誤表を確認し、既知のI²C 400kHz SCL低周期違反がないか確認してください。I²Cクロックが存在する場合は、クロック周波数を375~384kHzに下げてください。これにより、通常は十分なマージンが回復し、実際には400kHz付近を維持できます。 回路図中のプルアップ抵抗の値を確認してください。抵抗値が約2.2 kΩより高い場合は、1 kΩ–2.2 に置き換えてください。kΩで測定し、400kHzで再測定する。 - シングルアクセス読み取りの検証:PCF85263Aはロールオーバー破損を防ぐために、すべてのタイムレジスタを単一のI²Cアクセスで読み取ることを要求しています。 BRs、トーマス
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i.MX93 パラレルダイアプリインターフェース こんにちは、 私はi.MX93(MIMX9332CVVXMAC)を搭載した基板を設計しており、並列インターフェースを持つRGBディスプレイを駆動する必要があります。設定ツールからは、R,G,Bチャネルを参照せずにデータ0-23のlebelledデータビットが割り当てられています。evb FRDMとTM050RDH03-41も調べてみましたが、残念ながらFRDMのデータは設定ツールと同じで、TM050RDH03-41の回路図は提供されていませんでした。 ピン配置を確認するための回路図を入手することは可能でしょうか? それとも、24ビットがR、G、Bのチャネル間で自由にマルチパクシングできるのか確認できますか? ありがとうございました。 エンリコ Re: i.MX93 parallel diaply interface こんにちは、 NXP Semiconductors製品にご関心いただきありがとうございます。 TM050RDH03-41ディスプレイコネクタの回路図をご覧ください。完全な回路図に興味がある場合は、技術CASEを作成してください。 JosephAtNXP_0-1789574219944.png よろしくお願いします。
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SE052 采用问题:EdDSA/X25519 可用性、非 FIPS 变体路线图、小程序限制 你好, 我们目前使用的是SE050E2 (小程序 7.2.0,在两个设计中,芯片报告为“SE051”(ATR,AppletConfig 0x3F9F),我们正在评估SE052,以用于下一个硬件版本。在做出决定之前,我们阅读了 SE052 数据表(修订版 1.5)、AN14028、AN14277、AN13904、AN12543(修订版 4.5)和 Plug & Trust MW 文档(AN13030 修订版 2.7),但有几点阻碍了我们做出决定。希望您能澄清一下。 我们的两个应用案例: 一个网状/传输节点(LoRa + 以太网),其标识为 X25519 + Ed25519 在 SE 内部生成和使用的密钥对(通过 ECDH) ECDH生成共享密钥 在 ID_ECC_MONT_DH_25519,通过以下方式签名 EdDSASign 和 ED25519PURE_SHA_512)。 使用签名设备 secp256k1 ECDSA (预先计算的摘要)和 Ed25519 针对不同的目标,使用受用户 ID 保护的会话。 问题: 变体。AN14277 指出 SE052F (OEF B501, FIPS 140-3) 是“唯一发布的变体”,其 GetInfo 显示没有 EDDSA / 没有 DH_MONT。是否有针对非 FIPS SE052 配置(相当于启用 CONFIG_EDDSA 和 CONFIG_DH_MONT 的 SE050E / SE051)的路线图?如果属实,大致时间范围和OEF是多少? 在 SE052F 上启用 EdDSA / Montgomery DH。由于 SetAppletFeatures 需要 RESERVED_ID_FEATURE (0x7FFF0204),而 RESERVED_ID_FEATURE 是 NXP 拥有的,那么客户是否有任何途径在 SE052F 上启用 Ed25519/X25519(例如,通过 EdgeLock 2GO 进行自定义配置),同时接受失去 FIPS 批准模式?或者说,无论小程序功能位如何,FIPS OS 版本都会阻止这些曲线? FIPS 和 EdDSA。FIPS 186-5 批准 EdDSA。未来是否有计划推出支持 Ed25519 和 X25519 且符合 FIPS 140-3 标准的未来 SE052 小程序/操作系统版本(通过 SEMS Lite 或新的 OEF)? APDU吞吐量限制。AN14028 §2.3.1 / AN13904 §8.4 描述了 1,000,000 APDU / 34 天的限制 (SW 66A6) 以及每 500,000 APDU 进行一次 FIPS 自检。这些是否仅与 FIPS 认证有关,在假设的非 FIPS SE052 变体中是否会缺失?通过 RST_N 重置是否足以清除计数器而不会对 NVM 产生影响? 针对签名用例的 Applet 功能路线图。我们在 AN12543 Rev 4.5 中找不到以下任何内容。7.2.x 版本有相关计划吗?一行代码还是未来的小程序? SE 内部强化了子密钥派生(标量加法 mod n,BIP32 风格),因此派生的私钥永远不会离开芯片。 secp256k1 上的 Schnorr 签名 (BIP340)。 确定性 ECDSA nonce(RFC 6979)和/或低 S 归一化。 预哈希 Ed25519 (Ed25519ph) 或流式 EdDSA 模式,因此长度超过 IFSC (0xFE) 的消息不依赖于 T=1 链接。 小程序 7.2.22 中的 UserID 行为。在 SE050E2 (7.2.0) 中,我们观察到,TAG_MAX_ATTEMPTS 耗尽的 UserID 对象无法再被删除(即使在 SCP03 平台上,DeleteSecureObject → 6986),并且尝试计数器属性始终显示为 0。AN14028 表 1 指出,属性现在显示最大尝试次数。2022年7月2日:(a)是否报告剩余/已用计数器?(b)SCP03 平台用户能否删除已耗尽的 UserID? ECDH NVM 磨损(也适用于我们目前的 SE050E2)。AN12543 §4.10.3 指出,当公钥作为字节数组(TAG_2)传递时,MONT_DH_25519 上的 ECDHGenerateSharedSecret 会在每次调用时写入 NVM,但当通过瞬态ECPublicKey 对象(TAG_3)传递时则不会写入 NVM。您能否确认这同样适用于带有 applet 7.2.0 的 SE050E,并且在调用之间使用 WriteECKey 更新瞬态对象的内容本身不会写入 NVM? 长寿。SE050E2 是否在恩智浦的产品生命周期计划范围内?是否有计划中的产品生命周期结束?这将决定我们下一次修订是否继续使用 SE050E2 版本。 提前谢谢您。 SE050 Re: SE052 adoption questions: EdDSA/X25519 availability, non-FIPS variant roadmap, applet limits 嗨@cvaldess , 感谢您的联系!让我逐一解答。 第一季度 — 非 FIPS SE052 变体路线图 正如您正确指出的那样,SE052F (OEF B501) 目前是唯一发布的 SE052 变体,其 AppletConfig 0x26F2 不包含 EdDSA 或 DH_MONT。我们不能在公共论坛上分享具体的路线图时间表,但我建议您联系当地的 Disti/NXP FAE,在签署保密协议 (NDA) 的情况下讨论您的需求,届时可以直接讨论路线图细节。 Q2 — 在 SE052F 上启用 EdDSA / Montgomery DH SE052F 上没有客户路径可以启用这些算法。 RESERVED_ID_FEATURE (0x7FFF0204) 是 NXP 拥有的对象,客户无法修改或删除它——EdgeLock2GO 不是启用它的机制。更根本的是,SE052F FIPS 140-3 OS 版本在认证配置中排除了操作系统/硬件级别的 Twisted Edwards (Ed25519) 和 Montgomery (Curve25519) 曲线支持。即使通过 SEMS Lite 加载自定义小程序也无法重新启用操作系统层中不存在的曲线——而且这样做无论如何都会使模块不符合 FIPS 标准,正如 AN14277 明确指出的那样。 第三季度——未来 SE052 小程序/OEF 将支持 FIPS 140-3 和 EdDSA。 FIPS 186-5(2023 年 2 月)确实批准了 EdDSA,因此标准基础是存在的。但是,任何在新 FIPS 140-3 证书下支持 Ed25519/X25519 的 SE052 OEF 都需要提交完整的 CMVP 重新认证申请。我们不便在公共场合确认相关计划或时间表。请与您当地的 Disti/NXP FAE 联系,就此问题进行保密协议 (NDA) 谈判。 第四季度 — APDU 吞吐量限制(SW 66A6) 是的,1,000,000 APDU / 34 天计数器和 500,000 APDU 定期自检是 FIPS 140-3 合规性要求,专门针对 SE052F。假设存在非 FIPS SE052 变体,则该变体不受这些限制。 关于 RESET:T=1oI2C 芯片 RESET(RST_N 切换或电源循环)是官方记录的恢复路径。APDU 计数器是会话驻留在 RAM 中的值——冷 RESET 时,如果没有 NVM 写入,它将被清除。Plug & Trust MW 包含一个 apdu_throughput_limit 演示,该演示使用 phNxpEse_reset 精确地演示了这种恢复。对于您的网状/传输节点用例,持续每分钟约 340 个 APDU,此限制在实践中应该不会造成问题,但请确保您的主机驱动程序能够通过自动重置优雅地处理 SW_66A6 。 Q5 — Applet 功能路线图(BIP32、Schnorr、RFC 6979、Ed25519ph) 您列出的特性——片上 BIP32 强化子密钥派生、Schnorr/BIP340、确定性 ECDSA nonce(RFC 6979)、低 S 归一化或 Ed25519ph——均未出现在 AN12543 Rev 4.5 或任何当前的 SE05x 文档中,并且在 7.2.x 版本中也没有任何关于这些特性的公开声明。线。我建议您通过您当地的 Disti/NXP FAE 提交正式的产品改进请求,以便我们的产品团队可以跟踪这些请求。 关于 Ed25519 的 T=1 链接问题:该小程序支持 IFSC (0xFE) 之外的 APDU 数据的多块 T=1 链接,因此消息长度在传输层处理,并且不是 EdDSA 操作的功能限制。 Q6 — 小程序 7.2.22 中的 UserID 行为 (a)计数器可读性: GetAttributes 响应返回配置的 TAG_MAX_ATTEMPTS 值(最大值),而不是剩余计数。当前小程序版本中,内部递减计数器并未作为直接可读属性公开。 (b)通过 SCP03 删除已耗尽的用户 ID:您在 7.2.0 版本中观察到的删除锁定用户 ID 时出现的 6986 错误是一个已知的限制。AN13904 没有明确记录在平台 SCP03 删除的背景下,7.2.22 的此行为发生了变化。我建议直接在 SE052F 评估硬件(或运行 7.2.22 的 SE051 样品)上验证这一点。作为一种变通方法,如果锁定的用户 ID 阻止了对象管理,则通过平台 SCP03 上的 RESERVED_ID_FACTORY_RESET 进行恢复出厂设置是已确认的路径——尽管这会清除所有用户对象,因此对象布局规划在这里很重要。 Q7 — ECDH NVM 磨损(SE050E,小程序版本 7.2.0) 确认的。AN12543 明确指出, ECDHGenerateSharedSecret on ID_ECC_MONT_DH_25519 仅当公钥作为字节数组 (TAG_2) 传递时才会导致每次调用写入 NVM。当公钥通过瞬态 ECPublicKey 对象 (TAG_3) 传递时,不会发生 NVM 写入。此行为适用于带有 applet 7.2.0 的 SE050E,因为 SE050E2 使用的是相同的 7.x applet 版本(SE051 芯片和 applet 系列,正如您的 GetInfo ATR 所确认的那样)。 WriteECKey 对瞬态对象进行写入操作时,仅写入 SRAM——在调用之间更新瞬态对象的内容不会造成 NVM 损耗。建议的节点模式是:在启动时分配一个持久的瞬态 ECPublicKey,在每次 ECDH 操作之前调用 WriteECKey (仅限 SRAM),然后调用 ECDHGenerateSharedSecret 并引用该瞬态对象 TAG_3。这样就完全避免了每次通话造成的非易失性存储器损耗。 Q8 — SE050E2 产品寿命 SE050E2于2022年发布。NXP 的产品寿命计划承诺,对于已注册的产品,自上市之日起至少可供货 10 或 15 年。有关 SE050E2 的最终注册状态和使用寿命期限,请查看NXP 产品使用寿命页面(完整表格需要登录)或请您的 NXP FAE 确认。 针对您的两个用例的总体建议 鉴于您的设计依赖于 Ed25519 (EdDSASign) 和 X25519 (MONT_DH_25519 上的 ECDHGenerateSharedSecret), SE052F 目前无法满足您的加密要求。在具有这些算法的 SE052 型号推出之前,SE050E2 / SE051 系列仍然是合适的选择。我们建议您向 NXP FAE 确认 SE050E2 的长期有效状态,并注册对非 FIPS SE052 等效产品的需求。 希望这能帮助您更好地做出决定。如果您还有其他问题,请告诉我。 祝你有美好的一天, 坎 ------------------------------------------------------------------------------- 笔记: - 如果此回复解答了您的问题,请点击“标记为正确答案”按钮。谢谢你! - 我们会持续关注帖子,从最后一条回复发出后持续7周,之后的回复将被忽略。 如果您之后有相关问题,请另开新帖并引用已关闭的帖子。 -------------------------------------------------------------------------------
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S32K358 高速スタンバイ こんにちは、 S32K358で高速スタンバイ機能をテストしたいです。S32DSでIPレイヤーのデモを作成しました。このプログラムは起動後5秒で高速スタンバイ状態に入り、3秒後にRTC-APIによって起動されます。これは問題なく動作します。 そこで、このプロジェクトを参照して、MCALレイヤーのデモを作成するためにEBプロジェクトを設定しましたが、失敗しました。高速スタンバイ状態になってから3秒後、電流が増加した。これはデバイスが起動したことを示唆しているが、メイン機能には移行しなかった。PE Microで接続した後、以下のエラーメッセージが表示されます。 割り込みコマンドを受信しました。執行を停止します。 UsageFault: 無効な EPSR.T または EPSR.IT フィールドで実行された命令。 バスフォールト:不正確な(非同期)データアクセスエラーが発生しました。 ハードフォールト:障害がハードフォールトにエスカレートしました。 ウェイクアップ後のベクトルテーブルを以下に示します。 1.png PCレジスタは0x0です。スタックの内容を確認すると、FastWkup_EntryAddressが入力されており、ハードフォールトはReset_Handlerにジャンプした後に発生します。 2.png 3.png 4.png FastWkup_EntryAddress に while(1) ループを追加しても、ハードフォルトは依然として発生します。 5.png スタンバイモードに入ると、単語が出てきます。 このプロジェクトでは、PMIC_PGOOD_HNDSHK_BYPが有効になっています。この基板には外部水晶発振器が搭載されていないため、コアクロックとしてFIRCが使用されています。 S32K358 RTD6.0.0 S32DS3.6.3 EB29.0 BR、 ジェイソン Re: S32K358 FAST STANDBY こんにちは、@Jason07 さん。 高速スタンバイ起動時、sBAFはVTORをカスタムベクターテーブルアドレスに設定します。 しかし、あなたのベクターテーブルには3つのエントリしか定義されていません。 初期SP、 リセットハンドラ (FastWkup_EntryAddress)、 NMIハンドラー。 つまり、ハードフォールトベクトルが抜けているのです。 何らかの故障が発生すると、CPUは定義されていないハードフォールハンドラーアドレスを取り出し、これがPC値の原因となる可能性があります。 この問題をさらにデバッグするには、ベクターテーブルに適切なハードフォルトハンドラを追加してください。それらが設定されると、ハンドラーが0x0にクラッシュする代わりに呼び出され、スタックされたPC、LR、そして元の故障の構成可能な故障状態レジスタ(CFSR/BFAR)にアクセスできます。 ありがとうございました。 BR、ダニエル
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正在寻找适用于 FRDM-IMX8MPLUS 板的 Robotics Edge Image 1.0.0 大家好, 我正在寻找适用于 FRDM-IMX8MPLUS 板(不是 IMX8MP-EVK)的 Robotics Edge Image 1.0.0 的发布包。 可以找到适用于 IMX8MP-EVK 或 IMX95EVK 的预编译镜像,但没有找到适用于 FRDM-IMX8MPLUS 的镜像。该开发板受支持( https://mcuxpresso.nxp.com/RoboticsEdgePlatform/latest/html/gsd/prebuilt-images.html )。 从源代码(Yocto)构建它简直是噩梦,因为它需要大约 1 TB 的空间,而且在此过程中会出现很多错误。 希望能得到满意的答复。 顺祝商祺! Re: Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board 好的,我的错,FRDM-IMX8MPLUS 文件打包在 IMX8M-EVK 压缩包里。 同一个名字,却涉及两个董事会。
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TapLinxを使っている人はいますか? 誰かNXPのTapLinx SDKを使ってMIFAREカードと連携していますか? 最小限のコンソールアプリの例に興味があります。サンプルアプリは、多数の機能を備えたGUIアプリなので、動作させるのに少し手間がかかります。 カードへのデータの読み書き、認証などを行うだけの、最小限の機能しか持たないコンソールアプリを探しています。 Kotlinの例であればなお良いですが、Javaの例でも構いません。 はじめに Re: Anyone using TapLinx? こんにちは、@reid88さん TapLinx SDKはMIFARE DESFire、Plus、Classic、Ultralight、NTAGなどに対応しています。デザインリソースは以下から確認できます: MIFARE、NTAG、ICODE、UCODE用のTapLinx SDK |NXPセミコンダクターズ
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Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board Hi everybody, I'm looking for a release package for a FRDM-IMX8MPLUS board (not IMX8MP-EVK) of Robotics Edge Image 1.0.0. It's possible to find a pre-built image for IMX8MP-EVK or IMX95EVK, but nothing was found for FRDM-IMX8MPLUS. The board is supported (https://mcuxpresso.nxp.com/RoboticsEdgePlatform/latest/html/gsd/prebuilt-images.html) Building it from source (Yocto) is a pure pain, as it takes around 1 TB of space and there are plenty of errors during the process. Hope to have a successful answer. Best regards, Re: Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board Ok, my bad, FRDM-IMX8MPLUS files are packaged in the IMX8M-EVK zip file.  A single name, but two boards addressed.
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S32K358 FAST STANDBY Hello, I would like to test Fast Standby on the S32K358. I created an IP-layer demo in S32DS where the program enters Fast Standby 5 seconds after startup and is woken up by RTC-API after 3 seconds. This works without any issues. Then I referred to this project and configured an EB project to create an MCAL-layer demo, but it failed. After 3 seconds in Fast Standby, the current increased, which suggests the device woke up, but it never entered the main function. After attaching with PE Micro, the error messages are as follows: Interrupt command received. Halting execution. UsageFault: An instruction executed with an invalid EPSR.T or EPSR.IT field. BusFault: An imprecise (asynchronous) data access error has occurred. HardFault: A fault has been escalated to a hard fault. The vector table after wake-up is shown below: 1.png The PC register is 0x0. Checking the stack contents, I can see that FastWkup_EntryAddress was entered, and the HardFault occurs after jumping to the Reset_Handler. 2.png 3.png 4.png If I add a while(1) loop in FastWkup_EntryAddress, the HardFault still occurs. 5.png If I enter standby mode, it word. In the project, PMIC_PGOOD_HNDSHK_BYP is enabled. Since the board does not have an external crystal oscillator, FIRC is used as the core clock. S32K358 RTD6.0.0 S32DS3.6.3 EB29.0 BR, Jason Re: S32K358 FAST STANDBY Hello @Jason07, On Fast Standby wakeup, the sBAF sets VTOR to your custom vector table address. However, your vector table only defines three entries: Initial SP, Reset Handler (FastWkup_EntryAddress), NMI Handler. So the HardFault vector is missing. When any fault occurs, the CPU fetches the not defined HardFault handler address, which could explain the observed PC value. To debug this further, please add a proper HardFault handler to the vector table. Once those are in place, the handler will be invoked instead of crashing to 0x0, giving you access to the stacked PC, LR, and the Configurable Fault Status Register (CFSR/BFAR) of the original fault. Thank you, BR, Daniel
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Zone Node Software & Hardware Environment 1 Table of Contents • Introduction • Required Software • Required Hardware • References • Conclusion 2 Introduction This article is part of the Zone Node series and describes the software and hardware environment used throughout the project. The purpose of this article is to describe the software and hardware setup required to follow the series and reproduce the results. Before examining communication routing, control logic, or integration challenges, it is important to understand the tools and platforms that support the development and execution of the zonal node application. This article introduces the software components used to develop, configure, and deploy the application, as well as the hardware platforms used to demonstrate the zonal controller functionality. This information provides the foundation required for the remaining articles in the series. Overview of the development flow The zonal node application presented in this series is developed using a combination of Model-Based Design tools, NXP software components, and automotive-grade hardware platforms. At a high level: Application modeling starts in MATLAB® and Simulink®, where communication routing and control logic are implemented graphically. Code generation converts the model into production-ready embedded software using the code-generation tools provided by MathWorks and NXP. Deployment compiles the generated software and loads it onto the target hardware, where it is used to demonstrate communication between multiple vehicle networks. This environment was selected to support rapid development, easier validation, and improved traceability between model design and generated software. By using a Model-Based Design approach, algorithm development, communication integration, and application verification can be performed within a common framework. The software and hardware presented here are used consistently throughout the series and will be referenced when discussing communication routing, system behavior, and integration scenarios. ㅤ Figure 1. Development flow diagram The workflow begins with application development in Simulink. Communication routing logic, control functions, and software configuration are implemented within the model. The NXP Model-Based Design Toolbox (MBDT) provides hardware-specific blocks that enable integration with S32K3 peripherals and communication interfaces. Following code generation, the application is compiled and deployed to the target hardware, where communication routing functionality can be validated. This article is intended for: Engineers interested in reproducing the zonal node demonstration Simulink users developing automotive communication applications Developers evaluating Model-Based Design workflows Engineers working with NXP automotive microcontrollers and evaluation boards By understanding the software and hardware environment early in the series, readers will be better prepared to follow the implementation details presented in subsequent articles. 3 Required Software The following software components are used throughout the project: MATLAB® and Simulink® – model development and simulation Embedded Coder® (required MATLAB toolbox) – automatic code generation from the model Simulink models – the zonal node routing application model referenced throughout the series NXP Model-Based Design Toolbox (MBDT) – S32K3 support and peripheral configuration NXP additional tools – FreeMASTER and S32 Design Studio for build, deployment, and debugging CAN analysis software – monitoring and validating CAN communication LIN analysis software – monitoring and validating LIN communication 3.1 MATLAB® and Simulink® MATLAB® and Simulink® form the foundation of the development environment. They are used to create the zonal node application, implement communication routing logic, configure software behavior, and perform model-based verification activities. The application described throughout this series is developed as a Simulink model and later translated into embedded software using automatic code-generation tools (Embedded Coder®). 3.2 NXP Model-Based Design Toolbox (MBDT) The NXP Model-Based Design Toolbox (MBDT) extends Simulink with hardware-specific support for NXP automotive microcontrollers. For this project, MBDT for S32K3 version 1.8.0 is used. The toolbox provides blocks and configuration interfaces for communication peripherals, timers, digital I/O resources, and other hardware modules available on the target device. It also integrates with the code-generation workflow, allowing Simulink models to be converted into software that can run directly on the S32K3 microcontroller. Note: Installation and configuration instructions are provided in the dedicated article series (How to install .MLTBX). Readers who have not yet installed the toolbox should complete that step before continuing with this series. 3.3 CAN Analysis Software CAN analysis tools are used during development and validation to observe CAN and CAN FD traffic exchanged between the zonal node and other network participants. Typical use cases include: Monitoring transmitted and received CAN frames Verifying CAN-to-CAN routing behavior Measuring message timing and bus utilization Troubleshooting communication issues Examples of commonly used software include PCAN-View, CANalyzer, and CANoe. 3.4 LIN Analysis Software LIN analysis tools are used to monitor communication between the zonal node and LIN-connected edge devices. Typical use cases include: Verifying LIN schedule execution Monitoring frame transmission and reception Validating signal timing and integrity Testing LIN-to-CAN routing scenarios Examples of commonly used software include PLIN-View and LINalyzer. 4 Required Hardware The following hardware components are used throughout the project: S32K344 automotive microcontroller – used to execute the zonal node application S32K344-WB Evaluation Board – used as the development and validation platform CAN analysis hardware – used to monitor and verify CAN/CAN FD communication LIN analysis hardware – used to monitor and verify LIN communication 4.1 S32K3 Microcontroller The S32K3 family provides: Arm® Cortex®-M7 processing cores CAN FD communication interfaces LIN communication support Safety-oriented automotive features Low-power operating modes Rich peripheral connectivity These capabilities make the device suitable for implementing communication aggregation and routing functions within the scope of this project. 4.2 Evaluation Hardware The zonal node application runs on the S32K344-WB Evaluation Board, a development platform based on the NXP S32K344 microcontroller. The board provides access to the communication interfaces and processing capabilities of the target device while offering an integrated platform for software development, debugging, and validation activities. Within the scope of this project, the board is used to execute the routing application and exchange messages with nodes connected through CAN and LIN networks. Its communication interfaces, debugging connectivity, and expansion capabilities make it suitable for evaluating zonal communication architectures and routing scenarios. ㅤ Figure 2. S32K344-WB evaluation board 4.3 Communication Networks The examples presented throughout this series use CAN and LIN networks to demonstrate message forwarding, routing, and protocol translation scenarios. These networks provide the communication backbone between the zonal node, central controller, and edge nodes, and are referenced throughout the upcoming routing and integration articles. 4.4 Network Analysis Hardware Additional hardware tools are used during development and validation to observe network traffic and verify communication behavior. CAN analysis interfaces can be connected to the network to monitor transmitted and received CAN/CAN FD frames, validate routing functionality, and troubleshoot communication issues. LIN analysis interfaces can be used to monitor LIN schedules, frame exchanges, and LIN-to-CAN routing scenarios. These tools provide visibility into network activity and support verification of the communication flows presented in later articles of this series. 5 References Model-Based Design Toolbox (MBDT) Embedded Coder® Documentation MATLAB® and Simulink® Documentation S32K3 Microcontrollers S32K344-WB Evaluation Board 6 Conclusion This article introduced the software and hardware environment used throughout the zonal node project. It presented the development tools, code-generation workflow, and target hardware that support the implementation of the communication routing application. The next article will build on this foundation by examining the internal logic control mechanisms used within the zonal node and how they contribute to communication handling across multiple networks.
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From Simulation to Vehicle Control: Real-Time Decision Making on the S32N55 1 Table of Contents • Introduction • Overview • Context • References • Conclusion 2 Introduction Modern vehicle development increasingly relies on digital validation before physical prototypes are available. Simulation enables rapid testing and iteration, but engineering teams also need to demonstrate how virtual behavior maps to real hardware. In the Hello World demonstrator, this connection is handled by the Main Node application running on the NXP S32N55. The Main Node acts as the central execution point of the demonstrator, transforming vehicle information generated inside MATLAB ® and Simulink ® into decisions and actions that can be observed on physical hardware. By combining Model-Based Design, CAN communication, and centralized decision making, the system creates a bidirectional link between the virtual vehicle and the physical demonstrator. This article explains how the Main Node converts simulation inputs into coordinated vehicle behavior while maintaining synchronization between the digital and physical domains. 3 Overview As introduced in the previous article, the S32N55 functions as the communication hub of the demonstrator, aggregating information from distributed modules and distributing commands throughout the system. Beyond communication, however, the Main Node also serves as the decision-making layer responsible for interpreting vehicle state and translating it into actionable control signals. Developed using the NXP Model-Based Design Toolbox (MBDT), the application is entirely modeled in Simulink and deployed directly onto the target hardware. This workflow enables engineers to focus on vehicle functionality and system behavior while leveraging automated code generation and integrated CAN communication support. The Main Node receives data from simulated and physical sources, maintains a coherent vehicle-state view, runs vehicle-level control logic, and sends commands to the actuator nodes that make up the demonstrator. This centralized architecture reflects the direction of modern software-defined vehicle platforms, where coordination moves from isolated ECUs toward higher-level compute nodes. Figure 1. Main Node overview showing how the S32N55 coordinates simulation inputs, vehicle-state processing, and commands to distributed hardware modules. 4 Context The Main Node is positioned between the virtual vehicle environment and the physical hardware modules that form the demonstrator. Driver inputs generated through the Driver-in-the-Loop simulation environment are transmitted over CAN and received by the S32N55, where they are processed alongside feedback arriving from multiple distributed nodes. Commands such as vehicle speed, steering angle, gear selection, braking requests, and lighting controls enter the Main Node from the simulation environment. These inputs are then evaluated by the application and translated into CAN messages that drive the corresponding hardware modules. This architecture enables the physical demonstrator to mirror the behavior of the virtual vehicle. When the simulated vehicle accelerates, the speed command is interpreted by the Main Node and forwarded to the motor control subsystem. Steering-wheel movements are translated into steering-angle commands for the steering module, while lighting commands activate headlights, fog lights, hazard lights, and turn indicators on the physical hardware. Figure 2. System context illustrating the Main Node as the bridge between the virtual vehicle environment and the physical demonstrator hardware. The Main Node can be driven either by the Driver-in-the-Loop simulation or by the External Control model. In both cases, the command source publishes the same DBC-defined CAN frames, so the S32N55 receives speed, steering, brake, gear, and lighting commands through the same interface. This allows the same deployed application to be exercised from two sources without changing the Main Node software. This approach is especially useful during integration, demonstrations, and incremental validation. Engineers can exercise the Main Node and the downstream actuator modules even when the complete virtual environment is not active, while still preserving the exact communication contract used by the full system. As a result, the application can be validated against two different input sources without changing the deployed software on the board. Rather than acting as a simple gateway, the Main Node continuously evaluates received information and executes vehicle-level decisions. One example is the processing of motor feedback data, where information from multiple motors is combined to derive a representative vehicle speed used throughout the system. Centralizing this functionality simplifies system coordination while ensuring consistency across all connected modules. Gear selection is handled as part of this centralized decision layer. The incoming gear command is interpreted as a driving mode that affects how the requested speed is applied: Park and Neutral block motion commands, Reverse changes the sign of the velocity reference, and Drive or Sport propagate the requested speed as a forward-driving command. This keeps speed-control behavior aligned with the selected driving mode while preserving the same driver-input signal set. The target-speed command is computed from the requested speed reference, the selected gear mode, the reported vehicle speed, and the effective brake command. Motor feedback is fused into a representative reported speed, which provides the actual-speed reference used during braking decisions. Under normal driving conditions, the requested target speed passes through the gearbox-aware logic and is converted into the motor-speed command sent over CAN. When braking is active, the Main Node bases the outgoing command on the detected speed and brake value, reducing the command until the vehicle is considered stopped. The Main Node also hosts the demonstrator's automated emergency braking functionality. Parking sensor nodes continuously report obstacle distances over CAN. The application evaluates these measurements and determines whether an object has entered a predefined safety zone. When this condition is met, the braking command issued by the driver can be overridden and replaced with an emergency braking request generated by the system. Figure 3. Parking sensors in action detecting nearby obstacles and providing distance feedback used by the Main Node to support emergency braking decisions. An important aspect of this implementation is that the braking behavior is reflected across both domains. The physical hardware responds to the braking request, while the simulation environment can receive corresponding vehicle-state updates through the same CAN-based loop. This closed-loop behavior demonstrates bidirectional interaction between simulation and embedded execution, allowing safety-related functionality to be validated in a realistic environment before a full vehicle prototype is available. Figure 4. Closed-loop emergency braking flow showing how parking sensor feedback can trigger an automated braking request across both the physical and simulated domains. CAN communication is the key enabler of this architecture. Every subsystem communicates through DBC-defined interfaces, allowing functionality to be distributed across multiple independent nodes while preserving a consistent and scalable communication framework. The shared DBC approach ensures that signal definitions remain synchronized across all parts of the demonstrator. To support this workflow, MathWorks Vehicle Network Toolbox ™ provides direct integration between MATLAB ® , Simulink ® , and CAN communication interfaces. DBC files can be used directly throughout the development process, simplifying signal management and ensuring consistency across the virtual vehicle, the Main Node, and all peripheral modules. As the demonstrator grows to include additional functionality, the same network definition can be reused across all participating systems, reducing integration effort and helping accelerate development. Note: The combination of NXP Model-Based Design Toolbox and MathWorks Vehicle Network Toolbox creates a workflow in which vehicle behavior, communication interfaces, and deployed software remain aligned from modeling through system integration. Figure 5. CAN and DBC workflow showing how shared signal definitions keep the virtual vehicle, Main Node, and distributed hardware modules synchronized. 5 References NXP Model-Based Design Toolbox (MBDT) NXP S32N Vehicle Super-Integration Processors Vehicle Network Toolbox ™ NXP Model-Based Design Toolbox Community 6 Conclusion The Main Node demonstrates how a centralized compute platform can act as more than a communication gateway. Running on the NXP S32N55, it combines signal aggregation, decision making, and command distribution into a single application that coordinates the entire demonstrator. By transforming simulation-generated inputs into physical vehicle behavior and feeding real-world information back into the virtual environment, the Main Node creates a practical closed-loop development platform. Together, NXP Model-Based Design Toolbox, MathWorks Vehicle Network Toolbox, and CAN-based communication enable rapid iteration, simplified integration, and efficient validation of vehicle functionality across simulated and physical domains.
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Zone Node Logic Control (Main model overview) 1 Table of Contents • Introduction • Black-Box Overview • Simulink Model Overview • Inputs • Algorithm • Outputs • References • Conclusion 2 Introduction This article explains the internal behavior of the Zone Node by opening the component "black box" and describing how information flows through the application. The objective is to provide a functional understanding of the model, starting from the incoming inputs, continuing through the internal processing logic, and concluding with the generated outputs. The Zone Node acts as an intermediary between the Central Controller and the Edge Nodes located within a vehicle zone. While previous articles introduced the component and the development environment, this article focuses on the application's behavior and the responsibilities performed by the embedded software. This article focuses on the functional behavior of the Zone Node and explains how information flows through the component. Detailed aspects such as CAN routing implementation, LIN scheduling mechanisms, peripheral configuration, and communication stack integration will be covered in dedicated articles later in the series. 3 Black-Box Overview From a system perspective, the Zone Node behaves as a communication gateway and data aggregation component. It receives information from different communication networks, processes that information according to predefined routing rules, and forwards the resulting data to other parts of the system. At a high level, the component can be represented as: ㅤ Figure 1. Black-Box Overview The Zone Node does not implement vehicle-level control strategies. Functions such as braking decisions, steering calculations, or vehicle state management remain the responsibility of higher-level controllers. Instead, the Zone Node focuses on: Receiving messages from the Central Controller Receiving messages from Edge Nodes Acquiring data from local LIN-connected devices Routing information between networks Aggregating and forwarding data Providing monitoring and diagnostic information The result is a reusable communication component that can be deployed in different vehicle zones while maintaining the same overall behavior. 4 Simulink Model Overview The Zone Node functionality is implemented as a Simulink model organized around communication, routing, scheduling, and diagnostic subsystems. From a model perspective, the application can be divided into four logical areas: Input handling Routing and processing Communication scheduling Outputs and diagnostics ㅤ Figure 2. Main Simulink Application The input layer receives information from CAN and LIN communication interfaces and makes it available to the application logic. The processing layer evaluates incoming messages and determines how they should be handled. The scheduling layer manages periodic communication activities, while the output layer is responsible for forwarding messages and generating diagnostic information. This separation helps keep the model modular and makes it easier to extend the application with additional communication paths or Edge nodes without changing the core routing behavior. 5 Inputs The Zone Node receives information from three main categories of inputs. 5.1 CAN Network Inputs CAN communication represents the primary source of information processed by the Zone Node. Messages can originate from: Central Controller Lighting modules Steering modules Motor control modules Other Edge Nodes within the zone Typical examples include: Vehicle commands Status reports Diagnostic information Fault indications Actuation requests The exact set of messages depends on the specific Edge Nodes connected to the zone. 5.2 LIN Device Inputs The Zone Node also acquires information from LIN-connected devices. In the reference implementation, LIN communication is used to retrieve parking sensor information. The Zone Node periodically requests data from the LIN device and receives measurement values in response. Examples include: Front parking distances Rear parking distances Other LIN-based sensor information From the perspective of the Zone Node, LIN data behaves similarly to any other external input source. 5.3 Configuration Inputs Before normal operation begins, the Zone Node initializes its communication interfaces and loads the required configuration information. Examples include: CAN interface configuration LIN interface configuration Communication schedules Routing rules These parameters define how the application interacts with the surrounding networks. 6 Algorithm Internally, the Zone Node performs three main processing activities. 6.1 Message Reception The first step consists of collecting incoming communication data. Whenever a message arrives, the application captures: Communication source Message identifier Data payload Message length This information becomes available to the routing and aggregation logic. ㅤ Figure 3. CAN Reception Pipeline 6.1.1 Model Representation of Message Reception Within the Simulink model, message reception is implemented using communication interface blocks and dedicated processing subsystems that capture incoming network events and make the received information available to the rest of the application. ㅤ Figure 4. CAN Reception Main Flow ㅤ Figure 5. CAN Reception Subsystem At a high level, the reception subsystem performs three actions: Detects incoming communication events Stores the received information Makes the information available to the routing logic This allows the routing algorithm to operate independently from the physical communication interface. 6.2 Message Routing Message routing represents the primary responsibility of the Zone Node. The routing logic determines the origin of each incoming message and forwards it to the appropriate communication interface. The behavior can be simplified as: ㅤ Figure 6. Bidirectional CAN Routing Messages received from the Central Controller are forwarded toward the Edge Nodes, while messages originating from Edge Nodes are routed back toward the Central Controller. The routing mechanism remains independent of the actual application payload, allowing the same software architecture to support different message sets and vehicle functions. 6.2.1 Model Representation of Routing Logic The routing functionality is implemented as a dedicated subsystem responsible for deciding where each received message should be forwarded. ㅤ Figure 7. Message Routing Main Flow ㅤ Figure 8. Message Routing Subsystem The routing subsystem evaluates the origin of the received message and selects the appropriate destination interface. At this level, the application does not interpret individual signal meanings; it simply ensures that information reaches the correct communication network. This approach keeps the routing layer independent from application-specific functionality and allows the same architecture to be reused across different deployments. 6.3 LIN Scheduling and Data Acquisition In parallel with CAN routing, the Zone Node periodically acquires data from LIN-connected devices. The sequence follows a simple request-response model: ㅤ Figure 9. LIN Parking Acquisition Cycle This mechanism allows information originating on a LIN network to become available to the rest of the vehicle through CAN communication. 6.3.1 Model Representation of LIN Scheduling Periodic LIN communication is implemented using a dedicated scheduling subsystem. ㅤ Figure 10. LIN Scheduling Main Flow The scheduler periodically requests data from LIN-connected devices, waits for a response, and updates the application data used by the rest of the system. Depending on the communication requirements, the scheduler may manage one or more request-response sequences while maintaining a deterministic execution pattern. 6.4 High-Level Data Flow The internal data flow implemented by the Zone Node can be summarized as follows: ㅤ Figure 11. Zone Node Data Flow 7 Outputs The Zone Node produces several categories of outputs that are consumed by different parts of the vehicle architecture and by development tools used during validation and debugging. 7.1 Routed CAN Messages The primary outputs of the Zone Node are CAN messages forwarded between communication networks. Examples include: Commands sent from the Central Controller to Edge Nodes Status information returned from Edge Nodes Diagnostic messages Fault reports Configuration updates By routing these messages between communication domains, the Zone Node maintains communication between the central controller and the devices located within its assigned vehicle zone. 7.2 Aggregated Device Data In addition to forwarding CAN traffic, the Zone Node generates CAN messages containing information acquired from locally connected devices. One example is parking sensor data collected through a LIN interface and republished on CAN. This allows the Central Controller to access the information without requiring direct interaction with the LIN-connected device. The process can be summarized as: ㅤ Figure 12. LIN-to-CAN Data Path This approach creates a unified communication interface while hiding the complexity of the underlying network topology. 7.3 Diagnostic Outputs The Zone Node generates diagnostic information that is useful during development, system integration, and troubleshooting activities. Examples include: Communication counters Status variables Network activity indicators Communication statistics Device data used for monitoring purposes These outputs provide insight into the current behavior of the application and can be accessed through development tools such as FreeMASTER. 7.4 Visual Indicators In addition to communication outputs, the Zone Node drives visual indicators available on the evaluation hardware. The on-board LEDs provide immediate feedback regarding: Message reception activity Message transmission activity LIN communication activity Application execution status Although these indicators are not used by the vehicle itself, they simplify application bring-up and validation by providing a quick visual confirmation that the software is operating correctly. 7.5 Output Destinations The outputs generated by the Zone Node are consumed by several different system components. Central Controller Receives: Status information from Edge Nodes Aggregated sensor data Diagnostic information generated within the zone Edge Nodes Receive: Commands originating from the Central Controller Configuration and control messages forwarded through the Zone Node Local Devices Receive: Periodic requests issued by the Zone Node Communication messages required to acquire local measurements Development Tools Receive: Monitoring variables Communication statistics Diagnostic information used for debugging and validation 7.6 High-Level Output Flow ㅤ Figure 13. System Topology This output structure allows the Zone Node to act as a communication intermediary while simultaneously providing visibility into the behavior of the system during development and validation. 8 References NXP Model-Based Design Toolbox (MBDT) S32K3 Microcontroller Documentation S32K344-WB Evaluation Board Documentation 9 Conclusion This article described the internal behavior of the Zone Node by examining its inputs, processing logic, and outputs. By presenting the component as a functional black box, it explained how information is received, routed, aggregated, and distributed throughout the system without focusing on implementation-specific details. The next articles in the series will build upon this foundation by examining individual communication paths in more detail, including CAN-to-CAN routing, LIN-to-CAN routing, and the techniques used to validate and troubleshoot communication behavior.
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