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Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz)

Hello NXP Community,

Our custom board (using the PCF85263A RTC and AM6252) reads the RTC time exactly once during the initial boot sequence using the following command:

hwclock -u -s

We are experiencing an intermittent issue where it fails to fetch the RTC value approximately 1 out of 1,000 times.

(However, if it fails and we immediately retry the read command, it successfully fetches the time without any issues.)

During our troubleshooting, we lowered the I2C clock frequency from 400kHz to 100kHz (400000 -> 100000) under the exact same conditions. After this change, we conducted nearly 6,000 test iterations and the system operated perfectly without a single failure.

According to the PCF85263A datasheet, it supports a maximum I2C-bus frequency of 400kHz (Fast-mode).

Could you please advise:

Are there any known issues, errata, or similar historical reports regarding this intermittent I2C read failure with the PCF85263A at 400kHz?

Are there any specific configurations, bus capacitance/pull-up resistor considerations, or debugging steps you would recommend to resolve this while maintaining the 400kHz clock?

Thank you in advance for your support.

Re: Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz)

Hello Iseori,

There are no known errata or documented hardware issues with the PCF85263A itself at 400 kHz I²C operation. The part is specified and production-tested up to 400 kHz, and the behavior you describe is a classic symptom of marginal timing compliance on the host controller or bus side rather than a defect in the PCF85263A.

Recommended debugging steps:

- Scope the I²C bus at 400 kHz and capture SCL/SDA waveforms. Verify that Tlow ≥ 1.3 µs, Thigh ≥ 0.6 µs, Tr ≤ 300 ns, and Tf ≤ 300 ns during the RTC read transaction. Compare against the timing requirements in Table 68 of the PCF85263A datasheet.

- Check AM6252 errata for any known I²C 400 kHz SCL low-period violation. If present, reduce the I²C clock to 375–384 kHz, which typically restores full margin while remaining near 400 kHz in practice.

- Review pull-up resistor values in your schematic. If they are higher than ~2.2 kΩ, replace with 1 kΩ–2.2 kΩ and re-test at 400 kHz.

- Verify single-access reads: The PCF85263A requires that all time registers be read in a single I²C access to prevent roll-over corruption.

BRs, Tomas