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从 SPI NOR 闪存中的其他位置启动 T1022 大家好, 我有一个定制的 T1022 子板,其中处理器从存储在 SPI NOR Flash 中的 uboot 启动。我计划在所述 NOR 闪存中存储多个 uboot,以便处理器根据安装该子板的母板启动。所以我的问题是: 1)可以这样做吗?(目前我已经尝试在不同位置之间复制 uboot,但是速度太慢了) 2) 根据.cmm文件中,uboot总是存储在位置0,这是为什么呢?我们可以将这个位置改变到某个地方,以便它向用户询问 uboot 的位置吗? 欢迎就此提出任何建议。 感谢并致意 苏维克 回复:从 SPI NOR 闪存中的其他位置启动 T1022 不客气。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 好的。谢谢你的帮助。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 因为您必须从 IFC NOR 获取不同的 RCW,所以您必须操纵通向 IFC NOR 的地址线。示例 - IFC NOR 分为多个虚拟银行,并且我们选择特定银行有其逻辑。您可以为此浏览一次硬件设计指南。因此,您需要一个 CPLD 或一个外部控制器来切换 IFC NOR 中的存储体。因此,PBL 可以使用该逻辑获取不同银行中存在的不同 RCW。所以这需要修改硬件设计。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 正在调查。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 好的 。谢谢。我明白了方法。 最后一个问题。我们如何确保 PBL 从 IFC NOR 的不同位置获取?我找不到任何可以设置获取位置的字段。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 您想更改子板的 gpio 和 serdes 配置吗?那么您必须在子板的 IFC NOR 上保留 3 个不同的 RCW。 RCW 由 PBL 获取。Uboot 比 PBL 阶段晚,因此 Uboot 无法处理此问题 回复:从 SPI NOR 闪存中的其他位置启动 T1022 会回到你身边 回复:从 SPI NOR 闪存中的其他位置启动 T1022 在这种情况下,我们必须将 IFC NOR FLASH 保留在母板上,而不是子卡上。我说得对吗? 如果我们将 NOR 闪存保留在子卡上,我们如何确保 RCW 从不同的分区加载?可以将分区位置写入存储在 SPI 闪存中的 uboot 上吗? 回复:从 SPI NOR 闪存中的其他位置启动 T1022 因此,您需要的是:- RCW 具有 gpio 和 serdes 配置。因此,根据 3 个父卡的不同,您需要 3 个具有所需配置的不同 RCW。 上电复位时,PBL[预引导加载程序] 会从所需的非易失性源(IFC NOR、eSDHC、NAND 闪存)之一获取此 RCW,并加载此配置。一种可能的解决方案是使用 IFC NOR 作为源。 IFC NOR 将在 3 个不同的内存分区中存在 3 个不同的 RCW。 父卡必须设计成 当子板连接到父卡 A 时,RCW 将从 IFC NOR 中的分区 A 获取。 当子板连接到父卡 B 时,RCW 将从 IFC NOR 中的分区 B 获取。 第三张家长卡也是如此。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 将与 AE 团队讨论。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 当您说“您可以使用该特定的 DTB 加载映像”时,您的意思是父卡保留各自的 DTB,并在处理器启动时加载存储在父卡中的 DTB 吗?如果我的理解正确,那么如果 DTB 能够更改 SERDES 配置,这可能是一种可行的解决方案。 就我而言,考虑一个父卡 A,其中我们需要 SRDS_PRTCL 为 0x86,另一个父卡 B,其中 SRDS_PRTCL 需要为 0x81,并且我们有一个单处理器子卡。我们如何确保处理器按照每个主板的 SRDS_PRTCL 启动。我认为,dtb 提取是在 uboot 执行后开始的。但我需要根据母卡更改 uboot。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 你能不能制作3个不同的设备树二进制文件,根据父卡的不同,分别配置不同的GPIO?这样,当需要时,你就可以用特定的DTB加载你的镜像了。 这 3 个父卡是由同一个应用处理器构建的吗? 回复:从 SPI NOR 闪存中的其他位置启动 T1022 知道了。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 请参阅 AE 团队的以下更新。 关于 NOR 闪存中的多个 Uboot。您能否告诉我们更多关于为什么需要在 NOR 闪存中安装 2 个 Uboot 的要求?“处理器根据安装该子板的母板启动”——请详细说明。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 我已将此案例上报给 AE 团队,现在正在等待他们的反馈。 回复:从 SPI NOR 闪存中的其他位置启动 T1022 与 AE 团队讨论。
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Libraries support options in DS Hi, I am trying to use print trace to debugger console with the function of printf in S32G-VNP-RDB3 project. Noticed that "newlib Debugger Console" should be chosen for the item of  Libraries support in Target Processer page. But in my project, there is such a option with console. What else should be set?  Re: Libraries support options in DS Got, thanks! Re: Libraries support options in DS Hi @Liuliyuan,  Thank you for contacting NXP Support. Based on the following community post Semihosting printf with S32G274A - NXP Community By now, "printf" using the S32 Debugger is an unsupported feature. Therefore, we suggest you use a UART interface to implement a "printf" capability. I hope this information will be helpful. Have a great day!
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difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello ,  I was going through the Gold VIP user manual "GoldVIP-S32G3-1.11.0-User-Manual.pdf", Here i dnt understand the significance of GoldVIP Real-time Bootloader image (Slot A) (Slot B),or GoldVIP Real-time Gateway application image (Slot A) (Slot B). what are these different slots , i can see when this software is flashed to Nor flash it will be using Slot A in both the case .  I don't see anywhere the slot 2 is used what is the exact use case of this slot 2 Regards Karthik Mallya M GoldVIP Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello @Bio_TICFSL  Thank you for the response , To be clear my quetion is in current GoldVIP-S32G3-1.11.0 package ,is this space is in use or not ?, because even we will not load any application to this area while flashing  we are using only Slot A  i am asking becasue i am planning to use this area for other memory allocation like NvM area, before doing that i wanted to confirm Regards Karthik  Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello, There is no linker because we have no any example of it, but you can modify current linker file and add a memory through QSPI or a sensor, etc. Regards Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello @Bio_TICFSL , Could you Brief me what kind of application ,because I don't see any linker assignment for these slot Re: difference between GoldVIP Real-time Gateway application image (Slot A) (Slot B) Hello, The SLOT B it uses for application. Regards
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SPI NORフラッシュの他の場所からT1022を起動する 皆さん、こんにちは。 私はカスタムT1022子ボードを持っており、プロセッサはSPI NORフラッシュに保存されているubootから起動します。上記のNORフラッシュに複数のubootを保存して、この子ボードがマウントされている親ボードに従ってプロセッサが起動するようにする予定です。だから私の質問は: 1) 可能ですか?(現在、場所間でubootをコピーしてみましたが、遅すぎます) 2) .cmm によるファイルの場合、uboot は常に 0 の場所に格納されます。それはどうしてですか。この場所をどこかで変更して、ユーザーにubootの場所を尋ねることはできますか? これに関する提案は大歓迎です。 よろしくお願いいたします。 スービック Re:SPI NORフラッシュの他の場所からT1022を起動します どういたしまして。 Re:SPI NORフラッシュの他の場所からT1022を起動します よろしくお願いします。 Re:SPI NORフラッシュの他の場所からT1022を起動します IFC NORとは異なるRCWをフェッチする必要があるため、IFC NORに向かうアドレス行を操作する必要があります。例 - IFC NORは仮想銀行に分割されており、特定の銀行を選択するためのロジックがあります。これについては、ハードウェア設計ガイドを一度確認できます。そのため、CPLDまたはIFC NORでバンクを切り替えるための外部コントローラーが必要になります。そのため、異なるバンクに存在する異なる RCW は、そのロジックを使用して PBL でフェッチできます。そのため、ハードウェア設計の変更が必要です。 Re:SPI NORフラッシュの他の場所からT1022を起動します 偵知。 Re:SPI NORフラッシュの他の場所からT1022を起動します わかりました。ありがとうございます。道筋がわかりました。 最後の質問。PBL が IFC NOR の別の場所からフェッチされるようにするには、どうすればよいですか?フェッチ場所を設定したフィールドが見つかりませんでした。 Re:SPI NORフラッシュの他の場所からT1022を起動します チャイルドボードのGPIOとSERDESの構成を変更したいですよね?次に、子ボードのIFC NORに3つの異なるRCWを保持する必要があります。 RCWはPBLによって取得されます。UbootはPBLステージより遅れて来るため、Ubootはこれを処理できません Re:SPI NORフラッシュの他の場所からT1022を起動します あなたに戻ってきます Re:SPI NORフラッシュの他の場所からT1022を起動します この場合、IFC NOR FLASHを子カードではなく親ボードに保持する必要があります。私は正しいですか? 代わりに子カードにNORフラッシュを保持している場合、RCWが異なるパーティションからロードされるようにするにはどうすればよいでしょうか。パーティションの場所は、SPIフラッシュに保存されているubootに書き込むことができますか? Re:SPI NORフラッシュの他の場所からT1022を起動します だからここにあなたが必要とするものがあります:- RCW には gpio と serdes の設定があります。したがって、3つの親カードに応じて、目的の構成を持つ3つの異なるRCWが必要です。 パワーオン リセット時に、PBL[Pre-bootloader] は、目的の不揮発性ソース [IFC NOR、eSDHC、NAND フラッシュ] の 1 つからこの RCW をフェッチし、このコンフィギュレーションをロードします。考えられる解決策の1つは、IFC NORをソースとして使用することです。 IFC NORには、3つの異なるメモリパーティションに3つの異なるRCWがあります。 親カードは、次のように設計する必要があります。 子ボードが親カードAに接続されている場合、RCWはIFC NORのパーティションAからフェッチされます。 子ボードが親カードBに接続されている場合、RCWはIFC NORのパーティションBからフェッチされます。 3枚目の親カードも同様です。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームと話し合います。 Re:SPI NORフラッシュの他の場所からT1022を起動します 「その特定のdtbでイメージをロードできる」と言うとき、親カードはそれぞれのdtbを保持し、プロセッサが起動すると親カードに保存されているdtbをロードするということですか?私が理解したことが正しければ、dtbがserdesの設定を変更することができる場合、これは可能な解決策の代替手段になる可能性があります。 私の場合、親カードAがあり、SRDS_PRTCLが0x86である必要があり、別の親カードBがあり、SRDS_PRTCLが0x81する必要があり、プロセッサの子カードが1つあるとします。プロセッサが各ボードのSRDS_PRTCLsに従って起動することをどのように確認できますか。私の意見では、dtbのフェッチはubootが実行された後に開始されます。ただし、親カードに従ってubootを変更する必要があります。 Re:SPI NORフラッシュの他の場所からT1022を起動します 親カードによってGPIO構成が異なる3つの異なるデバイスツリーバイナリを作成することはできませんか?また、必要に応じて、その特定のdtbで画像をロードできます。 これらの3つの親カードは、同じアプリケーションプロセッサで構築されていますか? Re:SPI NORフラッシュの他の場所からT1022を起動します わかりました。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームからの以下の最新情報をご参照ください。 NORフラッシュ内の複数のUbootについて。NORフラッシュに2つのUbootが必要な理由について、要件についてもう少し詳しく教えてください。「プロセッサは、この子ボードがマウントされている親ボードに従って起動します」 -- これについて詳しく教えてください。 Re:SPI NORフラッシュの他の場所からT1022を起動します 私はこのケースをAEチームにエスカレーションしましたので、今彼らからのフィードバックを待っています。 Re:SPI NORフラッシュの他の場所からT1022を起動します AEチームと話し合う。
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Linker script section alignment exceeds memory region size (RTD, AR: 4.7.0, SW: 2.0.0) Hello, I have installed the S32DS v3.5.12 together with the latest RTD (AR: 4.7.0, SW: 2.0.0) for an S32k148 MCU. I have generated the FreeRTOS example project for the S32K148 MCU as shown in the image below. I have studied the Linker file linker_flash_s32k148.ld and think I found an error in the generated file. First, examine the memory definition. According to the file 1024 bytes are reserved for the interrupt table inside the flash memory and then additional 16 bytes for the flash configuration flags/bits, etc. MEMORY { int_flash_interrupts : ORIGIN = 0x00000000, LENGTH = 0x00000400 /* 1K */ /* Do not change this section */ int_flash_config : ORIGIN = 0x00000400, LENGTH = 0x00000010 /* 16bytes */ /* Do not change this section */ int_flash : ORIGIN = 0x00000410, LENGTH = 0x0017FBF0 /* ~1.5MB */ int_sram_results : ORIGIN = 0x1FFE0000, LENGTH = 0x00000100 /* 256bytes */ int_sram : ORIGIN = 0x1FFE0100, LENGTH = 0x0003DF00 /* ~248K */ int_sram_stack_c0 : ORIGIN = 0x2001E000, LENGTH = 0x00001000 /* 4K */ ram_rsvd2 : ORIGIN = 0x2001F000, LENGTH = 0 /* End of SRAM */ }  If you continue analyzing the section definition at the beginning SECTIONS { .flash_interrupts : { . = ALIGN(2048); __interrupts_rom_start = .; KEEP(*(.intc_vector)) . = ALIGN(4); __interrupts_rom_end = .; } > int_flash_interrupts you see that the memory region int_flash_interrupts, which has an assigned size of 1024 bytes contains a 2048 byte alignment instruction, which exceeds the defined region size. Am I correct? If not, can you explain, what I am missing here. Best regards, M_SCH S32 SDK for S32K1 Re: Linker script section alignment exceeds memory region size (RTD, AR: 4.7.0, SW: 2.0.0) Hi @M_SCH  The ALIGN(n) instructs the compiler to align a variable on an n-byte boundary starting from the ORIGIN address. This just limits the location of a memory region to a certain n-byte size, this should not interfere with other memory regions as the memory region size does not exceed the n-byte boundary. B.R. VaneB
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Boot T1022 from other locations in SPI NOR flash Hello All, I have a custom T1022 child board wherein the processor boots up from the uboot stored in SPI NOR Flash. I am planning to store multiple uboot(s) in the said NOR flash so that the processor boots up according to the parent board in which this child board is mounted. So my questions are: 1) Is it possible to do so? (Currently I have tried copying uboot between locations, but it is too slow) 2) As per the .cmm file, the uboot is always stored at location 0. Why is that? Can we change this location somewhere so that it asks the user for the uboot location? Any suggestions regarding this is welcome. Thanks and Regards, Souvik Re: Boot T1022 from other locations in SPI NOR flash You are welcome. Re: Boot T1022 from other locations in SPI NOR flash Ok. Thank you for your help. Re: Boot T1022 from other locations in SPI NOR flash Because you have to fetch different RCW from IFC NOR, you would have to manipulate the address lines going towards the IFC NOR. Example - IFC NOR is divided into virtual banks, and there is a logic with which we select a particular bank. you can go through the hardware design guide once for this. So you would need either a CPLD or an external controller that lets you switch the banks in the IFC NOR. So that different RCW present in different banks can be fetched by the PBL using that logic. So this needs a hardware design modification. Re: Boot T1022 from other locations in SPI NOR flash Investigating. Re: Boot T1022 from other locations in SPI NOR flash Ok . Thank you. I understood the way. Last question. How can we ensure that PBL fetches from a different location of the IFC NOR? I couldn't find any field wherein we set the fetching location. Re: Boot T1022 from other locations in SPI NOR flash you want to change the gpio and serdes configuration of child board right ? then you have to keep 3 different RCW on IFC NOR of child board. RCW is fetched by the PBL. Uboot comes later than the PBL stage so Uboot will not be able to handle this Re: Boot T1022 from other locations in SPI NOR flash Will back to you Re: Boot T1022 from other locations in SPI NOR flash In this case, we have to keep the IFC NOR FLASH on the parent boards instead of the child card. Am I correct? If we keep the NOR flash on the child card instead, how can we ensure that the RCW loads from different partitions? Can the partition locations be written on the uboot stored in SPI flash? Re: Boot T1022 from other locations in SPI NOR flash So here's what you would need :- RCW has the gpio and serdes configuration. So depending upon the 3 parent cards, you need 3 different RCW having the desired configuration. At power-on reset, PBL[Pre-bootloader] fetches this RCW from one of the desired non-volatile sources[IFC NOR, eSDHC,NAND flash] and loads this configuration. One of the possible solutions is to use IFC NOR as a source. IFC NOR would have 3 different RCWs present in 3 different memory partitions. The parent card has to be designed in such a way that when the child board is connected to Parent card A, the RCW gets fetched from partition A in the IFC NOR. when the child board is connected to Parent card B, the RCW gets fetched from partition B in the IFC NOR. similarly for the third Parent card. Re: Boot T1022 from other locations in SPI NOR flash Will discuss with the AE team. Re: Boot T1022 from other locations in SPI NOR flash When you say "you could load your image with that specific dtb.", do you mean that the parent cards keep their respective dtbs and when the processor boots up it loads the dtb stored in the parent card? If what I have understood is correct, this could be a possible solution alternative if the dtb is able to change the serdes configuration. In my case, consider a parent card A wherein we need the SRDS_PRTCL to be 0x86 and another parent card B wherein the SRDS_PRTCL is required to be 0x81 and we have a single processor child card. How can we ensure that the processor boots up as per the SRDS_PRTCLs for each board. In my opinion, dtb fetching starts after uboot has executed. But I need the uboot to be changed as per the parent card. Re: Boot T1022 from other locations in SPI NOR flash Can you not make 3 different device tree binaries that will have different gpio configurations depending upon the parent card? And when needed, you could load your image with that specific dtb. these 3 parent cards are built out of same application processor? Re: Boot T1022 from other locations in SPI NOR flash Got it. Re: Boot T1022 from other locations in SPI NOR flash Hello, I have designed a T processor child card. Currently, I have 3 different parent cards onto which this child card is to be mounted. Now, these 3 cards have different SRDS_PRTCL, different GPIO configurations, etc. I was thinking if we could by any change have a card-dependent boot-up instead of programming uboot multiple times whenever we change the parent board. Hence the requirement. Hope I am clear in my requirement. Thanks, Souvik Re: Boot T1022 from other locations in SPI NOR flash Please refer to the following update from the AE team. Regarding multiple Uboot(s) in the NOR flash. Can you please tell us a bit more about the requirement as to why you would need 2 Uboot in the NOR flash? "the processor boots up according to the parent board in which this child board is mounted" -- please elaborate on this. Re: Boot T1022 from other locations in SPI NOR flash I have escalated this case to the AE team, am waiting for the feedback from them now. Re: Boot T1022 from other locations in SPI NOR flash Hello, Any help with this?  Re: Boot T1022 from other locations in SPI NOR flash Discussing with the AE team.
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カーネルドライバのIIO ADCサンプルコード S32G2 のカーネル ドライバーを使用して、いくつかの IIO ADC 入力チャネルを設定しようとしています。私が従うことができる例があるかもしれないと思っていましたか? 「include / linux / iio」ディレクトリの下の消費者機能を使用してADCのチャネルを要求および設定する必要があるかどうかわかりませんか?チャンネルが設定されると、 ポーリングまたは割り込みを通じて定期的に値をキャプチャし、その値をsysfsドライバーノードに書き込む必要があります。 なお、NXPコミュニティフォーラムやカーネルドキュメント(カーネルバージョン5.15)には、S32Gの例が見つかりませんでした。 どんな援助もありがとう。 Re:カーネルドライバのIIO ADCサンプルコード 提案に従って、NXPの「s32cc_adc.c」のADCコードの一部を実装することにしましたLinuxドライバーを新しいドライバーに。 Re:カーネルドライバのIIO ADCサンプルコード BSP 39.0 とカスタム ボードを使用しています。 また、いくつかのドキュメントを見ると、iio_channelを取得するには、確立されたiio_mapが必要ですか?iio_mapはすでにYoctoで生成されていますか、それともボードのdtsファイルで設定する必要があるものですか?
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内核驱动程序的 IIO ADC 示例代码 我正在尝试通过 S32G2 上的内核驱动程序设置多个 IIO ADC 输入通道。我想知道是否有一个我可以效仿的例子? 我不确定是否需要使用“include/linux/iio”目录下的消费者功能来请求和设置 ADC 的通道?一旦建立频道, 我希望通过轮询或中断定期捕获值,然后将这些值写入我的 sysfs 驱动程序节点。 请注意,我在任何 NXP 社区论坛或内核文档(内核版本 5.15)中都找不到 S32G 的任何示例。 感谢您的帮助。 回复:内核驱动程序的 IIO ADC 示例代码 根据建议,我决定从 NXP 的“s32cc_adc.c”中实现一些 ADC 代码Linux 驱动程序合并到我的新驱动程序中。 回复:内核驱动程序的 IIO ADC 示例代码 我正在使用带有定制板的 BSP 39.0。 另外,查看一些文档,为了获得 iio_channel,需要建立 iio_map?iio_map 是否已在 Yocto 中生成,或者这是否需要在 board dts 文件中设置?
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LPC5536 CTIMER0 confusion Ladies and Gentlemen, I am trying to set up CTIMER0 for a periodic interrupt. Unfortunately it doesn't work and I'm getting confused. My questions are: 1- In the Reference Manual -> SYSCON capital, page 223, AHBCLKCTRL1 register has bit26, called TIMER0. Is this bit the clock enable for CTIMER0? Is TIMER0 and CTIMER0 the same thing? 2- when I turn AHBCLKCTRLSET[1], bit26 to 1, I immediately loose the connection between MCUXpresso and MCULINK PRO. That means, I cannot debug anymore. I have to close the debug perspective and open it again. 3- There's another enable bit: SYSCON->CTIMERGLOBALSTARTEN, bit0. Here I can also enable CTIMER0 CLK. Are both enables necessary? 4- In case I don't turn AHBCLKCTRLSET[1], 26 bit to 1, I can debug the chip, but all the instructions to set in the CTIMER0 section, they have no effect at all. I single step through them, but there's no change in the registers. 5- I also can't set to 0 the CTIMERCLKDIV[0] register - I'd like to enable the clock divider 6- CTIMERCLKSEL[0] also cannot select FRO1M, if I try to write this register 0x04, there's no effect. Since CTIMER0 doesn't work, of course, I don't get any interrupt on it. Here's the part of my code, which must configure CTIMER0: // Set up Ctimer0 to generate a periodic interrupt SYSCON -> CLKUNLOCK =0x01 ; // enables configuration of clocks SYSCON -> CLOCK_CTRL |= FRO1MHZ_CLK_ENA ; // enable the 1MHz RC oscillator SYSCON -> AHBCLKCTRLSET[1] |= TIMER0_CLK_EN ; // SYSCON -> CTIMERCLKDIV[0] = 0x0 ; // ** divider clock runs, division by 1 SYSCON -> CTIMERCLKSEL[0] = FRO1M; // ** CTimer0 clock is 1MHz from FRO SYSCON -> CLKUNLOCK = 0x00 ; // disables configuration of clocks SYSCON -> PRESETCTRLCLR[1] |= TIMER0_RST; // reset timer 0 SYSCON -> CTIMERGLOBALSTARTEN |= CTIMER0_CLK_EN; // Ctimer 0 gets clock CTIMER0 -> TCR |= CEN ; // CTIMER0 Counter enable CTIMER0 -> PR = 1000U ; // Prescaler set to 1000. 1MHz : 1000 = 1kHz to timer0 CTIMER0 -> MSR[0] = 1000U ; // Match shadow register, also 1000, results in 1sec timer0 CTIMER0 -> MR[0] = 1000U ; // beginning value CTIMER0 -> MCR |= MR0S | MR0RL | MR0I ; // stop on match, reload MR0 from shadow, generate IT NVIC -> ISER[0] |= 1U<<10 ; // Enable Interrupt No 10 (Timer0) 7- I got bit 10 from the file LPC5536.h, line 93. I didn't find any other documentation, if this interrupt is really from CTIMER0. Is it right? Other parts of my - at the moment still primitive - code are properly working, I can debug them - whenever the debugger works. Re: LPC5536 CTIMER0 confusion It does work! Your solution works in my EVK board. Thanks. Re: LPC5536 CTIMER0 confusion Hi, I have tried to run the void CTimerInit(void) code on my LPC5536-EVK board based on MCUXPrresso tools step by step, I have not problem. Maybe it is related to probe BR XiangJun Rong Re: LPC5536 CTIMER0 confusion Dear XiangJun Rong, Thank You very much, the code, You sent seems to work perfect. Shall I give another question please? When I let the code run in debug perspective on full speed, it is OK. But, when I try to single step, at the moment I enable the clock for CTimer0, debugging is not more possible. The connection between MCUXpresso and MCU-Link Pro is broken: It only happens when I try to watch the CTimer0 registers. Is this the normal behavior of this setup, or there's still something wrong? Re: LPC5536 CTIMER0 confusion Hi, Pls try the following code, it works on my EVK board #define TIMER0_RST 1<<26 #define TIMER0_CLK_EN 1<<26 #define FRO1MHZ_CLK_ENA 1<<6 #define FRO1M 0x04 void CTimerInit(void) { // Set up Ctimer0 to generate a periodic interrupt SYSCON->PRESETCTRLSET[1] = TIMER0_RST; // reset timer 0 SYSCON->PRESETCTRLCLR[1] = TIMER0_RST; // reset timer 0   //SYSCON->CLKUNLOCK =0x01 ; // enables configuration of clocks SYSCON->CLOCK_CTRL |= FRO1MHZ_CLK_ENA ; // enable the 1MHz RC oscillator SYSCON->AHBCLKCTRLSET[1] |= TIMER0_CLK_EN ; // SYSCON->CTIMERCLKDIV[0] = 0x0 ; // ** divider clock runs, division by 1 SYSCON->CTIMERCLKSEL[0] = FRO1M; // ** CTimer0 clock is 1MHz from FRO //SYSCON->CLKUNLOCK = 0x01 ; // disables configuration of clocks     CTIMER0->PR = 1000U ; // Prescaler set to 1000. 1MHz : 1000 = 1kHz to timer0 CTIMER0->MSR[0] = 1000U ; // Match shadow register, also 1000, results in 1sec timer0 CTIMER0->MR[0] = 1000U ; // beginning value CTIMER0->CTCR=0x00; CTIMER0->EMR=0x00; CTIMER0->PWMC=0x00; CTIMER0->MCR |= 1<<24|3<<0; // stop on match, reload MR0 from shadow, generate IT NVIC->ISER[0] |= 1U<<10 ; // Enable Interrupt No 10 (Timer0) NVIC->ICPR[0] |= 1U<<10 ; NVIC->IPR[10]=0x00; //SYSCON->CTIMERGLOBALSTARTEN |= CTIMER0_CLK_EN; // Ctimer 0 gets clock CTIMER0->TCR |= 0x01; // CTIMER0 Counter enable }     void CTIMER0_IRQHandler(void) { //clear flag CTIMER0->IR|=1<<0; GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN); } Hope it can help you Re: LPC5536 CTIMER0 confusion Another experience: Whether the clock is enabled to CTIMER0 in AHBCLKCTRL[1], or it is not enabled, I cannot modify SYSCON-> CTIMERCLKDIV, cannot set the HALT bit to zero. Also, CTIMERCLKSEL remains 0x07 (no clock), even if my code sets it to 0x00 (main clk). When CTIMER0 clock is enabled in SYSCON->AHBCLKCTRL1, and I try to modify any registers in CTIMER0 domain, I loose the connection between MCUXpresso and MCU-Link pro. Why I cannot select the clock source for CTIMER0? Is there any restriction to SYSCON->CTIMERCLKSEL0 ? Re: LPC5536 CTIMER0 confusion Dear xiangjun_rong, I tried to implement Your code. The only modification is, I modified to CTIMER0 instead of CTIMER4. When the clock of CTIMER0 is enabled, line 128, I immediately loose the connection between MCUXpresso and MCU-LINK Pro. I cannot find out, how to resolve this problem: The only workaround is not to enable the clock for CTIMER0, by commenting line 128 out - see the screenshot please. Of course, without clock, it is not possible to configure and run the CTIMER0. But, there's no loss of connection, the other parts of my code works. I don't know what to do. Please recommend me a solution. Re: LPC5536 CTIMER0 confusion Hi, Pls refer to SDK example of CTimer. You can download SDK from the link: https://mcuxpresso.nxp.com/en/welcome I suppose that the CTimer registers writing has to follow up a sequence. After you enable the CTimer gated clock and set up the CTimer clock source, then follow up the sequence.  CTIMER4->CTCR=0x00; CTIMER4->PR=0x00; CTIMER4->MCR=0x03; CTIMER4->PWMC=0x00; CTIMER4->MR[0]=0x2000; CTIMER4->MSR[0]=0x2000; Pls have a try BR XiangJun Rong Re: LPC5536 CTIMER0 confusion Dear XiangJun Rong, I discovered, that there's an error in the attached code. I corrected already from line 113 to 117, I access CTIMER0 now. Now, my code compiles properly, runs until line 103 properly. From line 103 I single step. When I reach line 113 (CTIMER0->TCR |= CEN 😉 the connection breaks between MCUXpresso and MCU-LINK Pro. See the screenshot please. In case I don't single stem but run at full speed, the connection also breaks. I only try to watch a variable, CheckTimer. No other registers are watched. How can I debug this code? Is it impossible? Re: LPC5536 CTIMER0 confusion My questions are: - How can I be sure, that CTIMER0 is properly configured and it counts? - How can I avoid the lost of connection between MCUXpresso and MCU-LINK Pro? Re: LPC5536 CTIMER0 confusion Dear XiangJun Rong, thank You for the suggestions. Unfortunately, I am still in trouble. As I understand Your answer, CTIMER0 and TIMER0 are the same thing, only the terminology is different in the documentation. It's OK then. The root of my problem is: I need to have a periodic interrupt in about every second. I try to set it up, but without a success. My idea is: CTIMER0 runs, counts about 1 sec long and generates the necessary interrupt and starts all over again. This interrupt doesn't happen, and I am trying to find out why. Maybe the counter doesn't work, maybe it is misconfigured, maybe I set the interrupt the wrong way or something else? First, I try to check the counter. TIMER0_CLK_EN is defined as 26 in a header file, it is not a problem. My code runs until the breakpoint in line 103 without any problem. The first instruction is in line 77, there are only includes and comments before. The IRQ service routine is at the end of my code. As I try to debug my code, I single step after line 103. Everything is fine, until I try to see the CTIMER0 registers. When the command in line 108 turns the clock ON, I immediately loose the connection between MCUXpresso and MCU-LINK PRO. In case I don't watch the CTIMER0 registers in debug perspective, than I am able to single step through my code (IRQ doesn't come whether I single step or I let it run full speed). If I stop the clock to CTIMER0 later in the code, I am able to look into the register-bank of CTIMER0, but I only see all zeroes there, like it wouldn't be configured at all. Re: LPC5536 CTIMER0 confusion Hi, I suppose that the line is incorrect. #define TIMER0_CLK_EN 1<<26 SYSCON -> AHBCLKCTRLSET[1] |= TIMER0_CLK_EN ; You can write it as: SYSCON -> AHBCLKCTRLSET[1] = TIMER0_CLK_EN ; or SYSCON -> AHBCLKCTRL[1] |= TIMER0_CLK_EN ; After you set the bit 26 of SYSCON -> AHBCLKCTRL[1] , you can access the CTimer0 register. The target of SYSCON->CTIMERGLOBALSTARTEN register is that all the CTimer modules can synchronize if they use the same clock as tick. Ctimerx clock diagram for LPC553x: Hope it can help you BR XiangJun Rong
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FRDM i.MX93 debian fails to boot Hi all, I created a debian image: flex-installer -i auto -d /dev/mmcblk0 -m imx93frdm but when I try to boot it I got the following: U-Boot SPL 2024.04-00004-g3c3ab3b0050 (Dec 16 2024 - 03:43:34 +0100) SOC: 0xa1009300 LC: 0x2040010 PMIC: PCA9451A PMIC: Over Drive Voltage Mode DDR: 3733MTS DDR: 3733MTS found DRAM 2GB DRAM matched M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x58800 by ROM_API NOTICE: TRDC init done NOTICE: BL31: v2.10.0 (release):lf-6.6.36-2.1.0 NOTICE: BL31: Built : 03:43:39, Dec 16 2024 U-Boot 2024.04-00004-g3c3ab3b0050 (Dec 16 2024 - 03:43:34 +0100) Reset Status: POR CPU: NXP i.MX93(52) Rev1.1 A55 at 1700 MHz CPU: Industrial temperature grade (-40C to 105C) at 41C Model: NXP i.MX93 11X11 FRDM board DRAM: 2 GiB optee optee: OP-TEE api uid mismatch TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C2 0x52] TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C2 0x50] Core: 225 devices, 32 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment [*]-Video Link 0fail to find output device probe video device failed, ret -19 [0] lcd-controller@4ae30000, video fail to find output device probe video device failed, ret -19 In: serial Out: serial Err: serial BuildInfo: - ELE firmware version 2.0.0-64d8ef47 switch to partitions #0, OK mmc1 is current device UID: 8113698833b24e53b83dc4ac5ea9ee53 flash target is MMC:1 Net: Warning: ethernet@428a0000 (eth1) using random MAC address - 0e:5e:34:1a:a9:5b Warning: ethernet@42890000 (eth0) using random MAC address - 5a:85:5e:b5:39:85 eth0: ethernet@42890000, eth1: ethernet@428a0000 [PRIME] Fastboot: Normal Normal Boot Hit any key to stop autoboot: 0 Working FDT set to 83000000 libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... 47856 bytes read in 2 ms (22.8 MiB/s) optee optee: OP-TEE api uid mismatch Unable to open OP-TEE session (err=-19) mm_communicate failed! Error: Cannot initialize UEFI sub-system, r = 3 switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Error: Cannot initialize UEFI sub-system, r = 3 starting USB... Bus usb@4c100000: tcpc_setup_ufp_mode: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = -62 Port not available. Bus usb@4c200000: USB EHCI 1.00 scanning bus usb@4c200000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Device 0: unknown device Running BSP bootcmd ... switch to partitions #0, OK mmc1 is current device Can't set block device Can't set block device Booting from net ... ethernet@428a0000 Waiting for PHY auto negotiation to complete.... done BOOTP broadcast 1 DHCP client bound to address 192.168.178.117 (8 ms) Using ethernet@428a0000 device TFTP from server 192.168.178.1; our IP address is 192.168.178.117 Filename 'Image'. Load address: 0x80400000 Loading: * What am I missing? Re: FRDM i.MX93 debian fails to boot Thank you @Chavira.  I followed your instructions and now I have debian running on my FRDM i.MX93. Re: FRDM i.MX93 debian fails to boot Hi @ieio74! Thank you for contacting NXP Support! I am not facing the error by my side. Try deleting all of the partitions using gparted and try the next commands: $ sudo flex-installer -i pf -d /dev/mmcblkx $ sudo flex-installer -i auto -d /dev/mmcblkx -m imx93frdm Change the x with the number of your device. Best Regards! Chavira
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SJA1124 driver installation for S32DS failed I am trying to install the drivers for the SJA1124 but I am getting the following error: It seems that the SJA1124 drivers are already partwise installed: But I cannot see any SJA1124 Examples anymore, even though they have been there before. How can the examples disappear and how do I get them back? Best regards, Markus Activation | Installation | Licensing | Installer Download SDKs Re: SJA1124 driver installation for S32DS failed After I deinstalled the package and installed it again, I got the examples back: I am still wondering, when and why they got removed in the first place, but at least I got them back now.
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Bit field descriptions for the Protected Flash Region Hi, In the LPC55S69 user manual UM11126 page 252, it is written "Note: For bit field descriptions, see the attached Protected Flash Region.xls for further details."  Where can I find this excel file? In the MCUXpresso Secure Provisioning tool, some information is given for the bitfield but it is not detailed. For instance, in the location CMPA:SPI_FLASH_CFG, the bit field "SPI_RECOVERY_BOOT_EN" is 5-bit with no explanation. In the user manual, the same bitfield is said to have only 4-bit. Obviously the protected Flash bit fields are updated faster than the user manual. Perhaps for designers with NXP device experience, most of these details are obvious. But for a new comer like me, I stumble a lot trying to understand this device. Thanks LPC55xx Re: Bit field descriptions for the Protected Flash Region Hello @gvellet  I'm sorry for the inconvenient to you. I have submitted request to add this. I send you the Rev.2.5 for reference. Please see my attachment. Thanks. BR Alice Re: Bit field descriptions for the Protected Flash Region The attachment is no longer in the latest PDF release. See my Tuesday july 2nd reply for details Re: Bit field descriptions for the Protected Flash Region Hi Alice, In the current UM11126 file, there is no attachment. Can you attached the xls file to this message thread? Thanks, Gilbert Vellet Re: Bit field descriptions for the Protected Flash Region Hello @gvellet  Please open the attachment in UM11126, you will find the "Protected Flash Region.xls". As below: Please contact us if still have any issue. BR Alice
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MK53DN512ZCLQ10 and MK53DN512CLQ10 difference hi, we have been using since long time kinetis micro MK53DN512ZCLQ10 without problem.  On last production batch, instead that reference, it has been assembled MK53DN512CLQ10, which only diference is the silicon revision I can flash the firmware inside but boards does not work at all. So, which are the differences between both?, by datasheet i can not find any... Will, in theory, the MK53DN512ZCLQ10 firmware be 100%compatible to MK53DN512CLQ10' including also the flash tool/setup ? thanks in advanced for your help. ignacio Re: MK53DN512ZCLQ10 and MK53DN512CLQ10 difference Hi Pablo, thanks for your quick reply. Understood. Thanks for the confirmation! this product is at the end of his life, so i think will be easy if i purchase the old one for a while and then thats it.. thanks! Re: MK53DN512ZCLQ10 and MK53DN512CLQ10 difference Hi @ign, The MK53DN512ZCLQ10 is rev1.x 100MHz silicon while MK53DN512CLQ10 is rev 2.x 100MHz. So they are different. That's why the old rev1.x silicon product is not recommended for new design. This newer version is not 100% compatible with older version, this because new functionalities are added with the update. If you want you can check this by comparing both references manual and header files. We recommend you to generate a new project with the MK53DN512CLQ10 in order to have the updated header files. An apology for the inconvenience. Best Regards Pablo
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Termination of unused IOs pins in IMXRT500 Hi there,  In the technical Datasheet, it was mentioned there in the Termination of Unused IO pins Title that all high-speed PIOn pins if not used should be pulled internally or externally to the ground. so, my question is which pins are considered high-speed pins and which are not? also what are the pins that should be pulled down externally, and What is the effect that will happen if lifted floating? keeping in mind that I am using the FOWLP249 package.  also it was mention in the note 2 that these pins also should be pulled down internally from the software side, are they same as the previous picture or extra.  Re: Termination of unused IOs pins in IMXRT500 Hello @Saleh_94, The RT595 provide two GPIO architectures, where are called pads in the RM. These pads are called Fail Safe and high Speed, in addition, the main difference in the structure of these two pads is that the High-Speed pads have diodes to VDD and VSS, while the Fail-Safe pads only have diodes to VSS. As mentioned in the chapter 12 called "IO PAD Controller (IOPCTL)" in the RM. If you need more information about the architecture, you can consult the mentioned chapter.    Also, in the next images shows the architectures of all GPIO pins that were obtained in the chapter 1.5 called "Power supply for pins" in the datasheet: Also, if you experience any issue, do not hesitate to let me know. BR Habib.
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[S32K11x] Does Clamp diodes exist on each pin for S32K11x Hello Experts, I just want to clarify that does Clamp diodes exist on each pin for S32K11x as the following picture show? If yes, where can I can such information from RM or DS? If no full cover each pin, which pins have the clamp diodes? Thanks, Gavin Re: [S32K11x] Does Clamp diodes exist on each pin for S32K11x Hi Julián, Thanks your comfirm. Regards, Gavin Re: [S32K11x] Does Clamp diodes exist on each pin for S32K11x Hi @GavinLi1, Yes, all IOs are internally clamped to VDD and VSS. It is specified by the Injection current +- 3mA per a single pin and the ESD handling ratings.  Best regards, Julián Re: [S32K11x] Does Clamp diodes exist on each pin for S32K11x Hi Julián, Thanks for your quick reply. I want to further confirm that the protection diode does real exist not  the equivalent diode or parasitic diode, right? Thanks in advance! Gavin Re: [S32K11x] Does Clamp diodes exist on each pin for S32K11x Hi @GavinLi1, All pins implement protection diodes that protect against electrostatic discharge (ESD). These internal ESD diodes of the microcontroller are designed just for short discharge pulses only, and these do not sustain a constant current over time. You can find the ESD and latch-up protection characteristics in chapter 4.8 from the S32K1xx's Data Sheet. Best regards, Julián
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PN7642ベースのPegodaスマートカード・リーダー こんにちは、 Pegoda Smart Card Readerのファームウェアソースコードを入手できますか? リーダーベースのPegodaスマートカードリーダーを設計したいと思います。 また、ドライバー、ファームウェア更新ユーティリティ、プログラミングインターフェイスガイダンス、サンプルコードを含むSDKは準備ができていますか?オペレーティングシステムはWindowsとLinuxです。 ありがとうございます エリック・フー 日時:PN7642に基づくPegodaスマートカードリーダー こんにちはケリー、 ありがとうございます。PN7642自体の共有SDKとファームウェアはどうですか(Pegodaの話ではない)共有のSDKとファームウェアを使用し、USBが含まれているかどうかを確認したいと考えています。はい、共有SDKにCCID関連のサンプルコードがあることを確認した後、はいだと思います。その確認にお役立てください。 ありがとうございます エリック・フー 日時:PN7642に基づくPegodaスマートカードリーダー PN7642で対応可能なLinux用CCIDドライバについて、ファイルやリンクを共有してもらえますか? 回答:LinuxのCCIDドライバーは標準であり、別途提供する必要はありません。自分でインストールできます。 日時:PN7642に基づくPegodaスマートカードリーダー こんにちは@Eric12285  PN7642は、NFCフォーラム認定ソリューションです。USBインターフェースが認証された構成に含まれているかどうかを確認できますか?また、Webサイト上の共有ファームウェアはこれをカバーしていますか? 回答:Pegoda 3はNFCフォーラム認定を受けており、Pegoda3は完全なスタンドアロン製品であり、USBが含まれています。 日時:PN7642に基づくPegodaスマートカードリーダー すみません、私の質問を修正します。 PN7642は、NFCフォーラム認定ソリューションです。USBインターフェースが認証された構成に含まれているかどうかを確認できますか?また、Webサイト上の共有ファームウェアはこれをカバーしていますか? PN7642で対応可能なLinux用CCIDドライバについて、ファイルやリンクを共有してもらえますか? ありがとうございます エリック・フー 日時:PN7642に基づくPegodaスマートカードリーダー ありがとう、ケリー PN7642は、NFCフォーラム認定ソリューションです。USBインターフェースが認証された構成に含まれているかどうかを確認できますか?また、Webサイト上の共有ファームウェアはこれをカバーしていますか? CCIDインターフェイスプロトコルについて、共有ファームウェアはWindowsとLinuxの両方でこれをカバーしていますか? ありがとうございます エリック・フー 日時:PN7642に基づくPegodaスマートカードリーダー こんにちは@Eric12285  Pegoda Smart Card Readerのファームウェアソースコードは、ユーザーが利用できないはずです。ただし、PN7642 SDKはオープンソースであり、製品ページからダウンロードできます。 高性能 NFC リーダー、カスタマイズ可能な MCU、Security Toolbox を搭載したシングルチップ・ソリューション |NXPセミコンダクターズ
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imx8qm MEK CPU 板中的 GIC 内存映射 我对理解 GIC-500 IC 中的 ITS 地址有些困难。 在imx8qm参考手册中,我得到GIC映射到0x51a00000中的信息。然后检查GIC-500的内存映射,我假设ITS内存映射地址是0x51a20000。但是,当我尝试从 ITS 访问一些寄存器时,执行停止了。 我检查了一些设备树,一些区域被映射到0x52000000地址的中断控制器节点中。也许这就是 ITS?参考手册中没有关于该地址的信息。 你能帮助我理解正确的 ITS 基址吗?
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GIC memory map in the imx8qm MEK CPU board I am having some difficulties understanding the address of the ITS in the GIC-500 IC. In the imx8qm reference manual, I get the information that GIC is mapped in the 0x51a00000. Then checking the memory mapping of the GIC-500, I assume that the ITS memory map address is 0x51a20000.  However, when I try to access some registers from the ITS the execution stops. I checked some device trees, and some regions are mapped in the interrupt controller node at the 0x52000000 address. Maybe this is the ITS? There's no information about this address in the reference manual. Can you help me understand the correct ITS base address? Re: GIC memory map in the imx8qm MEK CPU board Hello @carloscs11  You can refer to imx8qm.dtsi to see the address of GIC (0x51a00000 as described in reference manual). I hope this can helps to you. Best regards, --... ...-- Salas.
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基于PN7642的Pegoda智能卡读卡器 您好,先生, 我们可以获得 Pegoda 智能卡读卡器的固件源代码吗? 我们想设计一款基于读卡器的 Pegoda 智能卡读卡器。 此外,SDK 是否包括驱动程序、固件更新实用程序、编程接口指南和示例代码?操作系统为WIndows和Linux。 谢谢! 傅家俊 回复:基于 PN7642 的 Pegoda 智能卡读卡器 嗨,凯利, 谢谢。PN7642 本身的共享 SDK 和固件怎么样(不谈论 Pegoda)?我们想使用共享的 SDK 和固件,并想确保是否包含 USB。我检查了一下共享 SDK 中是否有 CCID 相关的示例代码,然后我猜是的。请帮忙确认一下。 谢谢! 傅家俊 回复:基于 PN7642 的 Pegoda 智能卡读卡器 关于PN7642可以支持的Linux版CCID驱动程序,您可以共享文件和链接吗? Ans:Linux下的CCID驱动是标准的,不需要单独提供。您可以自行安装。 回复:基于 PN7642 的 Pegoda 智能卡读卡器 你好@Eric12285 PN7642 是经过 NFC 论坛认证的解决方案。我可以检查一下认证配置中是否包含 USB 接口吗?网站上共享的固件是否涵盖了这一点? 答:Pegoda 3 经过 NFC Forum 认证,Pegoda3 是一款完整的独立产品,其中包含 USB。 回复:基于 PN7642 的 Pegoda 智能卡读卡器 抱歉,纠正我的问题。 PN7642 是经过 NFC 论坛认证的解决方案。我可以检查一下认证配置中是否包含 USB 接口吗?网站上共享的固件是否涵盖了这一点? 关于PN7642可以支持的Linux版CCID驱动程序,您可以共享文件和链接吗? 谢谢! 傅家俊 回复:基于 PN7642 的 Pegoda 智能卡读卡器 谢谢,凯利 PN7642 是经过 NFC 论坛认证的解决方案。我可以检查一下认证配置中是否包含 USB 接口吗?网站上共享的固件是否涵盖了这一点? 关于 CCID 接口协议,共享固件是否涵盖 Windows 和 Linux? 谢谢! 傅家俊 回复:基于 PN7642 的 Pegoda 智能卡读卡器 你好@Eric12285 Pegoda 智能卡读卡器的固件源代码不应提供给用户。但PN7642 SDK是开源的,您可以在产品页面下载。 具有高性能 NFC 读取器、可定制 MCU 和安全工具箱的单芯片解决方案 | NXP 半导体
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how to check image CRC I have an image built using the MCUXpresso Secure Provisioning Tool. It's a plain image with a CRC, and the offsetToExtendedHeader field(address 0x00000028) contains the 4bytes CRC checksum value. Now, I want to check the CRC before writing it to flash. I tried to calculate it using these settings, but I cannot match the CRC with the offsetToExtendedHeader field. (ref: Kinetis Bootloader v2.0.0 Reference Manual) Is there any tool available to calculate the image CRC (like nxpimage and blhost)? Alternatively, where can I find more details about calculate the image CRC? Boot ROM|Booting | Flash MCXA 回复: how to check image CRC Hi Marek I found the Mbi_ExportMixinCrcSign function and the CRC algorithm in the nxpimage tool, which is part of SPSDK. Based on the above algorithm, I created a python program to verify the image CRC, and it works. Thanks for your support. Re: how to check image CRC Hi Victor, SEC tool uses SPSDK application nxpimage to build a CRC bootable image. You can see generated build script to find, how the nxpimage tool is used. See main menu > Help > SPSDK Online Documentation for nxpimage documentation. SPSDK is opensource, so you can find implementation details in GitHub.
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