******************************************************************************** * Detailed Description: * Example shows how to use original eTPU sets available over eTPU Function * Selector ( https://www.nxp.com/webapp/etpu/ ) and integrate them into * S32 Design Studio Integrated Development Platform. Example is based on * Software Development Kit (SDK) startup, in the main function adds necessary * configuration to get eTPU run. * eTPU application itself is simple PWM configured with eTPU Graphical * Configuration Tool. Target CPU is 'Generic CPU with eTPU2', eTPU clock 100MHz. * User can shows PWM waves over pins PH[10] and PH[11]. *   * Tip: AN4687 may be used as reference with note the different compiler is used. * References: http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf *            https://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176DC Rev.A2 + MPC57xx MOTHER BOARD Rev.C * MCU:             SPC5743RMLU5 QCO1640 1N83M FEAEQL * Target:          Debug_FLASH * EVB connection:  ETPU0_A (Port PH[10]) --> scope *                  ETPU1_A (Port PH[11]) --> scope * Compiler:        S32DS.Power.2017.R1 * SDK release:     S32_SDK_S32PA_EAR_1.8.0 * Configurator:    eTPU Graphical Configuration Tool 1.4.0.4 * Debugger:        Lauterbach Trace32 ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Apr-04-2019  David Tosenovjan  Initial version *******************************************************************************/

Detailed Description: Demo application performs I2C communication with externally connected external real time clock/calendar PCA8565. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Date and time may be set up by demo board’s buttons (SW2-SW6). Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. I2C communication is managed with using of own two layer driver where low-level driver consisting of I2C_0.c and I2C_0.h - these can be used for any device connected to I2C_0 module. Middle-level driver layer consist of I2C_PCA8565.c and I2C_PCA8565.h and it is specific to PCA8565 device. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:   For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * * ------------------------------------------------------------------------------ * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Maskset:  0N75H * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration *******************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates PMC Single VD self-test configuration and execution * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N15P and 0N15P * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference *            ******************************************************************************** Revision History: 1.0     Apr-04-2016     b21190(Vlna Peter)  Initial Version 1.1     Apr-20-2017     b21190(Vlna Peter)  added software PMC self-test 1.2     Aug-31-2017    b21190(Vlna Peter)  added PMC self-test configuration fix *******************************************************************************/

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_0 error injection *  capability on XBAR_0. The fault is generated on Core access to SRAM. *  After fault generation it is propagated to FCCU unit as NCF[38]. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     16MHz IRC * ********************************************************************************

******************************************************************************** * Detailed Description: * The example performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI_M1 is configured as master and for DSI function to serialize eTPU channels' * outputs. eTPU to DSI routing is done by SIU configuration. * User can see SPI waveform on the scope or logic analyzer. * ------------------------------------------------------------------------------ * Test HW: MPC5746R-252DC, MPC57xx Motherboard * MCU: SPC5746RMMT5 CTQG1740 1N83M HKBGCTB * Fsys: PLL 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: connect following pins to scope or logic analyzer * PA7: DSPI_M1 SOUT (motherboard pin PP[7]) * PA9: DSPI_M1 SCLK (motherboard pin PP[9]) * PA13: DSPI_M1 CS0 (motherboard pin PP[13]) ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals. * * This example shows, how to use some of ETimer modes. Channel 0 is set to * Fixed-Frequency PWM Mode and generates PWM signal with approximate frequency * 507Hz. This signal is routed to the UserLED1. * * Channel 1 is set to Count mode and generates 0,25 second interrupt. * In the interrupt service routine, duty cycle is increased from 0% to 100% * with step 6.25%. This shows for example, how can be controlled the brightness * of the LED. * * Channel 2 is set to Variable-Frequency PWM Mode and generates PWM signal with * frequency 10KHz. This signal is routed to the UserLED2. * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Terminal: * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  UserLED1 connected to P19.0 *                     UserLED2 connected to P19.2 * * ********************************************************************************

******************************************************************************** * Detailed Description: * This example demonstrates how to configure (CGM) clock generation module * and supply by clock all main peripherals. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5746R_176DC minimodule, MPC5746R * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Oct-19-2015     b21190(Vlna Peter)  Initial Version 1.1    Nov-11-2015    b21190(Vlna Peter)  Added PPL0 200MHz as system clock 1.2    Dec-02-2015    b21190(Vlna Peter)  Added Flash controller init 1.3    Dec-02-2015    b21190(Vlna Peter)  Fixed system clock init 1.4    Feb-07-2017    b21190(Vlna Peter)  SWT0 and SWT1 disabled in startup *******************************************************************************/

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user can choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5675K architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * Example also shows impact of enabled cache (macro OPTIMIZATIONS_ON). * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Example demostrates MCU behaviour when single bit RAM ECC error occurs by * intentional ECC error injection. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * * Purpose of the example is to show how to intentionally generate FCCU fault * causing reset either directly or by FOSU (simulating by non-handled FCCU * fault). Example configures FCCU, then an error is injected with using of * Noncritical Fault Fake register and after re-booting reset cause is evaluated. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configures LinFlex and eDMA modules and then periodically sends notice * to the terminal window (19200-8-no parity-1 stop bit-no flow control). * * ------------------------------------------------------------------------------ * Test HW:         MPC5607BEVB * Target :         internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * Fsys:            40 MHz PLL with 8 MHz crystal reference * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * * PIT channel 0 is used to generate 1sec interrupt where PA0 pin is toggled. * * ------------------------------------------------------------------------------ * Test HW:  MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset:  0N78H * Target :  RAM, internal_FLASH * Fsys:     600 MHz PLL1 with 40 MHz crystal reference *               core2 at 200MHz generated from PPL1 * Terminal: None ********************************************************************************

* Example of eMIOS configuration for shifted PWM mode ******************************************************************************** * Test HW: MPC5746C minimodule + MPC57xx Motherboard * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Jun-06-2017 b21190(Vlna Peter) eMIOS example with shifter PWM *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * ------------------------------------------------------------------------------ * Test HW:        XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU:             PPC5607BMLUAM03Y * Fsys:             64/48 MHz * Debugger:      Lauterbach Trace32 *                      PeMicro USB-ML-PPCNEXUS * Target:           RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW:   XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:       PPC5674FMVYA264 * Terminal:  19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:      264/200/150/60 MHz * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:              MPC5688EVB * MCU:                   SPC5668GMMG 0N61C * Terminal:              19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:                   116 MHz * Debugger:             Lauterbach Trace32 *                             PeMicro USB-ML-PPCNEXUS * Target:                  RAM, internal_FLASH * EVB connection:   User LED 4 connected to pin P28-10 * *

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW:  MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset:  0N32E * Target :  internal_FLASH * Fsys:     16MHz IRC as system clock ******************************************************************************** Revision History: 1.0     Mar-13-2017     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrate DMA transfer triggered by eTimer module compare * event CMPLD1 load into COMP1. Used is eTimer_0 channel_5. * It is necessary to configure DREQ[x] register according to channel_5 of * eTimer_0. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  0N89D * Target :  SRAM * Fsys:     120 MHz PLL * ******************************************************************************** Revision History: 1.0     Apr-08-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/