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******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:         This example demonstrate SWT functionality *                   On SWT timeout it sent signal to FCCU where is short *                   functional reset reaction on SWT timeout configured *                   FCCU then sent signal to RGM module which triggers short *                   functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-24-2015       b21190(Vlna Peter)  Added SWT short reset *******************************************************************************/
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******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0 and TSENS1 are read from Test Flash and * ADC0/ADC1 is set to measure Vbg and TSENS outputs. * Calculated internal temperature can be desplayed on the Terminal. * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). You should get following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from Test Flash * * TSENS0                           TSENS1 * * K1 = 429                         K1 = -220 * K2 = -5785                       K2 = -5767 * K3 = -12800                      K3 = -12736 * K4 = 45                          K4 = 45 * *      K1 * Vbg_code * 2^-1 + K2 * TSENS_code * 2^3 * T = ------------------------------------------------------------------------- / 4 - 273.15 [degC] *     [K3 * Vbg_code * 2^2 + K4 * TSENS_code] * 2^-10 * * Vbg0_code      = 1502               Vbg1_code      = 1502 * TSENS0_code = 2002               TSENS1_code = 1988 * * TSENS0 temp = 34.57 degC         TSENS1 temp = 36.78 degC * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction/data cache and enabling of branch prediction. * Example suppose MCU is configured for LSM (Lock-step mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************
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******************************************************************************** * Detailed Description: * Test HW:  MPC57xx + S32R274RRUEVB * Maskset:  1N58R * Target :  internal_FLASH * Fsys:     240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0     Apr-02-2019     b21190(Vlna Peter)  Initial Version 1.1    Apr-03-2019     b21190(Vlna Peter)  Added SWT reset reaction *******************************************************************************/ This example demonstrated the reset trigger on first SWT_2 timeout. Following screens shows the reset source after code execution in standalone mode and debugger connection afterwards:
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This session will explain how Freescale can enable customers to develop 76-81 GHz short and long range radar applications using the MPC577xK MCU, it will explain the concepts of the radar algorithms, including practical aspects such as SDADC or MIPI CSI sampling, Chirp Generation, Data Compression, R,V FFT, Detection and Tracking algorithms, and the benefits of the new Freescale IP that can allow them to improve their system resolution and accuracy. In this session customers will take away a detailed understanding of how to develop fast modulation radar systems using the MPC577xK MCU including the BOM cost advantages it also brings.
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******************************************************************************** * Detailed Description: * This example shows, how to initialize FlexCAN modules for simple transmission * and reception using RX interrupt. Both modules are configured for 100kbit/s * bit rate. CAN_0 module transmits message using MB0. CAN_1 module receives * message using interrupt via MB0. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5748G-324DS, MPC574XG - Motherboard * MCU:             PPC5748GMMN6A 1N81M * Fsys:            PLL0 160MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  Connect jumpers J15 and J16 on motherboard *                    Connect P14 H to P15 H *                    Connect P14 L to P15 L * ********************************************************************************
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******************************************************************************** * Detailed Description: * * Configures the FlexCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. * Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. * * In this config, CAN_0 transmits a message. CAN_1 receives the message. * * EVB connection: * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * NOTE! Termination resistor (120Ohm) have to be placed on transceivers output * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************
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This tool simplifies CAN bit timing calculation for CAN modules (FlexCAN, MCAN) available on MPC5xxx and S32K1xx families.   Enter input parameters into light green cells.   Device and Transceiver are selected from pull-down menus.        By selecting Transceiver, propagation delay parameter is also loaded, but can be simply overwritten by user value. Rest of parameters can be modified directly upon user needs. The tool lists possible setting together with register view. A recommended setting is highlighted. Three criteria are used for recommended values selection - desired sample point - highest fcpi accuracy - same prescalers for nominal and data phases, if CAN FD is calculated   For sure other setting can be selected, if needed, by clicking on respective line in list.   Note: Macros have to be enabled! BR, Petr
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Detailed Description:  Initializes the MCU including the FlexCAN peripherals.  Configures the FlexCAN to transmit and receive a CAN message.  In this config, CAN_0 transmits a message. CAN_1 receives the message.  CAN_0 MB8 is configured to send data each 1sec.This interval is generated by PIT.  CAN_1 RXFIFO is configured to receive a message and interrupt for MB5 is enabled.  To connect FlexCAN0 module (MCU's PB0/PB1 pins) to the motherboard's transceiver  with J5 CAN DB9 connector you have to:  - connect J17 2-6 on daughter board  - connect J17 5-3 on daughter board  This should be done as default    To connect FlexCAN1 module (MCU's PA14/PA15 pins) to the motherboard's transceiver  with J6 CAN DB9 connector you have to:  - connect J37 2-3 on motherboard  - connect J38 2-3 on motherboard  Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1  Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2  Terminate the CAN bus by connecting a 60 ohm resistor between CANH and CANL  To see LED toggling connect P8.1 to USER LED (P7.x)  ------------------------------------------------------------------------------  Test HW:  MPC5744P EVB  Maskset:  1N65H  Target :  RAM, internal_FLASH  Fsys:     200 MHz PLL with 40 MHz crystal reference
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******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************
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******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * ------------------------------------------------------------------------------ * Test HW:        X - PC5748G - MB (rev C) * MCU:             PPC5748GMMN6A * Maskset:       1N81M * Fsys:             160 MHz * Debugger:     Lauterbach Trace32 *             * Target:     Internal_FLASH * ********************************************************************************
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******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter.   * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************
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******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit * ECC error in internal SRAM (user must choose it in the option at the end of * main function). * Error Injection Module is used to generate a non-correctable (or single-bit) * ECC error in RAM. The bad data is accessed then, so the IVOR1 exception (or * ERM combined interrupt service routine) is generated and handled. * Example also offers useful macros for EIM and ERM modules. * The example displays notices in the terminal window (USBtoUART bridge J21) * (19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************
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******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ********************************************************************************
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******************************************************************************** * Detailed Description: * This SW provides the example of clearing of FCCU faults. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing example code. * ******************************************************************************** Revision History: 1.0     Jan-05-2016     nxa13250(Vlna Peter)  Initial Version *******************************************************************************/
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Revision 1 of the document is now officially published: http://cache.freescale.com/files/microcontrollers/doc/app_note/AN5200.pdf http://cache.freescale.com/files/microcontrollers/doc/app_note/AN5200SW.zip   Related code examples can be found also here (equal to AN5200SW): Example 1 - MPC5634M_2b_RAM_ECC_error_injection CW210 Example 2 - MPC5674F_1b+2b_RAM_ECC_error_injection CW210 Example 3 - MPC5643L 1b_RAM_ECC_error_injection CW210 Example 4 - MPC5643L 2b RAM and 2b FLASH ECC error injection CW210 Example 5 - MPC5675K-2b_RAM+2b_FLASH_ECC_error_injection CW210
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A requirement of the standard is to detect the accumulation of latent defects. To meet this requirement the MPC5744P has the ability to execute Built-In Self-Test (BIST) procedures.
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This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):
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This example enters the MCU into STANDBY0 low power mode and wakes up to backup SRAM. The WKPU6 (PE[0]pin) is used to wake up the MCU.   Regards, Petr   ******************************************************************************** * Detailed Description: * * On the EVB use KEY2 to enter Standby. * Use KEY1 to wake up from Standby to a code in backup SRAM. * * In RUN mode the LED1 blinks very fast, second core toggels LED3 * In STANDBY all LEDs are off. * The wakeup code blinks LED1 and LED2 slowly. * * The macro WKP_CORE is used to select which core is used after MCU wakes up. * When z4 core is selected, it is also necessary to set the MMU otherwise exception * is generated when uncovered memory area is accessed. * This is not needed for z0 core due to lack of the MMU.  * * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, SPC5646C 0N32E silicon * Target :  internal_FLASH * Fsys:     120 MHz PLL0 ********************************************************************************
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******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in internal DMA TCD RAM (user must choose it in the option at the end of * main function). * EIM (Error Injection Module) is used to simulate a multi-bit or single-bit * ECC error in DMA TCD RAM (Peripheral RAM). * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************
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