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******************************************************************************** * Detailed Description: * * ECSM Error Generation Register EEGR is used to generate a non-correctable * or single bit ECC error in RAM. The bad data is accessed then, so the IVOR1 * exception is generated and handled. * This file shows also ECSM_combined_isr and how to correct the wrong data. * Use macro Induce_ECC_error_by_DMA_read to select whether ECC error will be * injected by DMA read or CPU read. * At the end of main file you can choose if single bit or multi bit is injected * and select particular ME/EE setup by comment/uncomment of particular function * calls. * * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * ********************************************************************************

******************************************************************************** * Detailed Description: * Example shows MCU's temperature measurement using internal temperature sensor. * After basic initialization, the code initializes and calibrates eQADC, reads * test flash content and performs all necessary ADC measurement to calculate die * temperature. Results are then displayed in the terminal window. * ------------------------------------------------------------------------------ * Test HW: XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU: PPC5674FMVYA264 * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 264/200/150/60 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * Its intention is to offer advanced startup code additional to CW stationery. * ------------------------------------------------------------------------------ * Test HW: MPC5566EVB * MCU: PPC5566MVR132 * Fsys: 144/132/112/80/12 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: TPU_PORT_37 -> USER_LED_8 * TPU_PORT_38 -> USER_LED_7 (to see blinking LEDs) * ********************************************************************************

This example content a basic FMPLL initialization and configuration of Mode Entry module and Clock Generation module. By default active is core 2 -> e200z4 Demonstration of PIT triggering an interrupt on timeout. ******************************************************************************** * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190 (Vlna Peter) Initial Version 1.1 Sep-19-2019 nxa13250 (Vlna Peter) Added PIT + interrupts *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW: XPC564AKIT208S and XPC564AKIT324S * MCU: SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys: 150/132/120/12 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed frequency (48MHz) * Setup SIU, and demonstrate frequency modulation. * ------------------------------------------------------------------------------ * Test HW: XPC560B 64LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: SPC5602D * Cut: 1M18Y * Fsys: 48 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB clkout pin : Port J7 - pin 0 * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW: MPC5688EVB * MCU: SPC5668GMMG 0N61C * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys: 116 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: User LED 4 connected to pin P28-10 * *

******************************************************************************** * Detailed Description: * * * This example demonstrate functionality of XBIC_1 error injection * capability. The fault is generated on DMA transfer to SRAM. * After fault generation it is propagated to FCCU unit as NCF[59]. * * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ********************************************************************************

******************************************************************************** * Detailed Description: * In case user want GHS to initialize all cores it is necessary to define * preprocessor symbol: init_cores * However in this example the cores are initialized from function: Core_Boot(); * This example demonstrates how to initialize clock module and activate core0, core1 and core0 locksteped core. * ------------------------------------------------------------------------------ * Test HW: MPC57xx EVB * Maskset: 0N78H * Target : internal_FLASH * Fsys: 200 MHz PLL * ******************************************************************************** Revision History: 1.0 Feb-08-2016 b21190(Vlna Peter) Initial Version 1.1 Feb-09-2016 b21190(Vlna Peter) Added Core_Boot() function *******************************************************************************/

******************************************************************************** * Detailed Description: * This example demonstrates basic interrupt functionality. * ------------------------------------------------------------------------------ * Test HW: MPC56xx Motherboard + XPC564xB/C 208LQFP * Maskset: 0N32E * Target : internal_FLASH * Fsys: 16MHz IRC as system clock ******************************************************************************** Revision History: 1.0 Mar-13-2017 b21190(Vlna Peter) Initial Version *******************************************************************************/

* Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT3 and PIT2 interrupts are implemented. PIT interrupt toggle LED every second. * * * This example also shows, how to implement IVOR exceptions for core 0. * IVOR1 handler with while(1) loop is ready to use. * * * For correct HW vector mode setup, following files was added to the project: * * - exceptions.s * - handlers_vle.s * - HW_vector.c * * * Following files has been modified (all changes are marked by comment): * * - 56xx_flash.ld * - Vector.c * - MPC57xx__Interrupt_Init.c * * Following file was removed from project (files are still place in project, but * not compiled and linked) * * - intc_sw_handlers.S * - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW: MPC567XADAT516, MPC567XEVBFXMB * MCU: PPC5676RDMVY1 3N23A * Fsys: 180 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to J241, * User LED 1 connected to J242. *

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * IT INITIALIZES EBI FOR EXTERNAL SRAM CONNECTED TO XPC564AKIT324S AND TEST IT. * * ------------------------------------------------------------------------------ * Test HW: XPC564AKIT324S * MCU: SPC5644AMVZ1 0M14X QAK1235G * Fsys: 150/132/120/12 MHz * Debugger: Lauterbach Trace32 * Target: RAM, internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

******************************************************************************** * Detailed Description: * 200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing * example code + FCCU ALARM state configuration * ------------------------------------------------------------------------------ * Test HW: MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target : internal_FLASH* ********************************************************************************

* Detailed Description: * This example demonstrates frequency modulation at 20kHz with 250 steps. * Test HW: xPC57xx EVB + MPC5746C minimodule * Maskset: 1N06M * Target : Internal Flash * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Apr-23-2015 b21190(Vlna Peter) Added INTC driver and PIT ISR 1.3 May-14-2015 b21190(Vlna Peter) Dissabling SWT in Startup code 1.4 Jun-06-2017 b21190(Vlna Peter) ported for MPC5746C 1.5 Sep-29-2020 b21190(Vlna Peter) Added 20kHz frequency modulation *******************************************************************************/

Detailed Description: Demo application measures analog voltage from externally connected humidity sensor HIH-5030. Obtained values and processed and displayed on MPC5606S-DEMO-V2 board’s TFT panel. Application uses standard Graphics Libraries for MPC5606S for simple graphic output that is managed in mc_base.c module only. ------------------------------------------------------------------------------ Test HW: MPC5606S-DEMO-V2 + HIH-5030 MCU: PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys: 64MHz Debugger: Lauterbach Trace32 Target: internal_FLASH Terminal: none EVB connection: For complete project you may see following link: Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4a * Configure PIT timer to trigger interrupt and service it. * Example configures start of z7 cores via SW routine. * ------------------------------------------------------------------------------ * Test HW: MPC57xx MB + MPC5775K-326DS minimodule * Maskset: 0N76P * Target : internal_FLASH * Fsys: 265 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Sep-07-2017 b21190(Vlna Peter) Initial Version *******************************************************************************/ Example also contains Lauterbach multicore script as you can see below: It will display 3 Power view instances.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, third LED by second core, initializes and display notice via UART * terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW: XPC56xxMB2 + XPC564xB/C, PPC5646C 0M87Y silicon * Target : internal_FLASH, RAM * Fsys: 120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm * script for RAM: run_from_ram_vle.cmm * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW: MPC5604EEVB64 * MCU: PPC5604EEMLH 0N10D * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys: 40 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position * 2-3 fit SCI tx and rx connected * ********************************************************************************