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Continuously reducing the power consumption of integrated circuits is a constant topic in the development of integrated circuits. Reduced power consumption helps save power, extend standby time and reduce product heat, etc. Needless to say, low power consumption has become one of the important factors to measure product performance.   We usually recommend customers to refer MCUXpresso SDK power_mode_switch_lpc demo as low power design reference code. With this demo, customers can use serial terminal to control MCU to enter four low power consumption modes:Sleep mode,Deep Sleep mode,Power Down mode and deep power down mode. Meanwhile, user can also choose a variety of wake-up methods to wake up MCU through UART command.   However, when customers take use of power_mode_switch_lpc demo to measure lower power static characteristics, they find discrepancies with data sheet. Take example with LPCXpresso845MAX board. In power down mode, the demo board current reaches to around 100uA in debug mode. But data sheet states the typical current value is 1.5uA, no more than 10uA (see the Table below). Where is the problem? The purpose of the power_mode_switch_lpc demo is to demonstrate several low power modes and multiple wake-up methods to customers. We can’t get similar low power current value with default demo board as spec shows, but let's walk through a step-by-step demonstration and modify the routine to get the data sheet values.   LAB ENVIRONMENT: Demo Board: LPCXpresso845MAX SDK: SDK_2.11.0_LPCXpresso845MAX Demo Code: power_mode_switch_lpc IDE:MCUXpresso IDE v11.5.0   STEP: 1. Download power_mode_switch_lpc to LPC845 development board and run it. The serial port selects low power mode, press (SW2 button) to wake up. The program runs into power down mode, with debugger connected, the measured Idd is 99.5uA To enter low power mode, the following code is used: POWER_EnterPowerDown(DEMO_ACTIVE_IN_DEEPSLEEP); In order to wake up, parameter DEMO_ACTIVE_IN_DEEPSLEEP is configured with PDSLEEPCFG. BOD and watchdog oscillator power domains are turned on. All these setting results in potential current loss, causing power supply current higher than expectation.   2. In this step, we will remove wakeup initialization code // DEMO_InitWkt(); Replace this line of code //POWER_EnterPowerDown(DEMO_ACTIVE_IN_DEEPSLEEP); //enter power down mode with BOD and watchdog osc with POWER_EnterPowerDown(0); //power down BOD and watchdog osc   The modification is to turn off BOD power domain and watchdog clock in power down mode, compile and download the code again and enter the power down mode. At this time, the measured Idd is 57.3uA   In this way, Idd is significantly reduced. However, 57.3uA is still far from the typical value of 1.5uA stated in the data sheet. This is due to MCU debug power domain is turned on by IDE debugger, which leads to extra current consumption.  3. Thus we disconnect debugger and let the development board work in stand-alone mode (power off and re-power on). After power on, LPC is in power down mode. At this time, the measured Idd is 1.4uA. This is quite similar as the current value in datasheet. Consider GPIO configuration: The spec data shown in datasheet are tested under a dedicated test board with almost no external peripheral devices, and unused pins are basically in a floating state. For custom board or  LPCXpresso804 EVK. Some of its IO pins have external pull-up resistors and LEDs. If the GPIO is configured to output low power, the small light will be lit, resulting in additional power consumption. So we configure all pins as pull-up inputs for low power measurement.   Consider package: The test is based on LPCXpresso845MAX equipped LPC845 64pin package. It also applies to LPC845 48pin package. 33 package doesn't have VDDA pin. Due to VDD and VDDA pin design are not exactly the same as other package, for instance, 33pin low power consumption in power down mode is slightly higher than 64/48pin, but no more than 10uA as our spec in DS. Summary: Low power current parameters of the data sheet are measured with all MCU oscillators and analog domains off. Besides, reasonable configuration of GPIO can further reduce MCU power consumption. Before entering the low power consumption mode, it is recommended to set the unused GPIO as a pull-up input according to the actual situation (It can also be set to output low when the pin is floating). In applications with high requirements for low power consumption, users need to carefully optimize the code design to obtain the best low power consumption design.
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经常有客户在使用LPC55S69的过程中遇到读 Flash进入异常HardFault中断的现象。如果在Flash Mass Erase之后从未对Flash扇区进行过写操作,直接用指针通过AHB读Flash地址会导致程序跳入HardFault 中断而无法继续正常运行。 原因    刚出厂的LPC55Sxx FLASH处于全零的全擦除状态,没有设置ECC。当芯片通过LinkServer 和MCUXpresso IDE建立连接时,先擦除要下载代码用到的扇区,再把代码下载到对应位置,并对相应存储区的ECC值同时进行更新。代码以外的区域仍然是无ECC设置的擦除状态。 当LPC55Sxx 通过AHB总线直接读取Flash内存区域时(例如,mytemp = *(uint32_t*)0x4000)要对Flash ECC进行校验。这一指令对于读有效代码区是没有问题的, 因为这一区域的ECC在下载代码时早已设置好。但是一旦读取没有代码的扇区,由于没有检测到正确的ECC,导致Flash读取失败,并跳转到下图中的HardFault_Handler()异常中断:   我们在Sector Erase后通过AHB读取Flash内存内容,也会遇到同样的HardFault异常跳转,出问题的原因都是一样的。 解决方法 针对这一问题我们有如下两种解决方法: 先执行Flash写操作,再读取Flash 与Flash 擦除操作不同,执行Flash写操作后对应的ECC值也同步更新。这样,ECC校验通过后,通过下面的代码就可以对Flash直接进行AHB读取。 volatile uint32_t mytemp; …… mytemp = *(uint32_t*)0x1000;//read memory content 0x1000 to mytemp 请注意:0x1000必须是一个已经写过的地址。 如果Flash的某个扇区处于被擦除的状态,我们只需要在通过AHB总线读取内存区域之前对该区域执行写操作,这样ECC校验位更新正确后,就可以正常读Flash。 Flash的写操作可以参考MCUXpresso SDK自带的flashiap例程,函数FLASH_Program。   使用Flash控制指令读取Flash区内容 使用Flash控制指令进行读操作不会导致硬件错误(请参阅UM11126 “Command listing (CMD)”章节)。这是用户手册中推荐的读Flash正确打开方式。 请注意:CPU只有在频率低于100MHz时,才能进行Flash操作(读,写,擦除,校验,等等),当CPU频率超过100MHz时是不能实现上述操作的。 目前,官方没有提供上用控制指令读取Flash内容的例程,因此需要您根据下面步骤创建自己的读Flash程序。 开发环境: IDE: MCUXpresso IDE v11.1.0 SDK MCUXpresso SDK v2.7.0 步骤: 在MCUXpresso IDE中导入一个基础例程,如led_blinky 在下图所述选项中添加iap组件   选择iap1,点击OK   点击完OK之后,fsl_iap_ffr.h, fsl_iap.c, fsl_iap.h文件将自动添加到工程中   在source文件夹中添加附件中的memory.h和memory.c文件   4) 使用Flash 控制指令时,需要在源文件中添加memory.h, fsl_iap.h   5) 调用memory初始化和memory读取函数   6)调试,单步执行(step over)到memory_read(),查看结果  
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Recently I found some customers have a bit of problem when porting project from one MCU to another, so this article using simple steps demonstrates how to change MCU with MCUXpresso. There is also a video demonstrated the detail steps in attachment. Pay attention, as MCUXpresso User Guide says: All projects are associated with a particular MCU at creation time. The target MCU determines the project memory layout, startup code, LinkServer flash driver, libraries, supporting sources,launch configuration options etc. etc. so changing a project’s associated MCU should not be undertaken unless you have a total grasp of the consequence of this change. Therefore rather than changing a project’s associated MCU, it is strongly recommended that instead a new project is generated for the desired MCU and this new project is edited as required. However, on occasion it may be expedient to reset a project’s MCU (and associated SDK) and this can be achieved as follows. For example, changing lpc55s69 to lpc55s06, we need install SDKs for lpc55s69 and lpc55s06 before all the below steps. 1 - Change MCU & Package 1.1 – Change MCU Right click “MCU” under Project tree, choose “Edit MCU” Uncheck ”Preserve memory configuration”(it is checked by default)->choose LPC55S06->there is a warning, choose Yes. We can see the Memory details changed to lpc55s06, then click ”Apply and close”. 1.2 – Change Package 2 - Change Compiler Definitions In Properties view->Settings->MCU Compiler ->Preprocessor, change the definition for CPU from LPC55S69JBD100 to LPC55S06JBD64 as below: 3 – Change/add SDK driver for LPC55s06 Selected project, then click ”Manage SDK components”, choose the drivers our application used, for example, clock, power, usart. Click “OK”, then click “Yes” to update. Delete LPC55S69 device related files: Add “system_LPC55S06.c” and “system_LPC55S06.h” files: 4 - Change startup file. Delete LPC55s69 startup files, add “startup_lpc55s06.c”, we can find the startup file in any SDK demo. 5 - Change board related files. Refer to our own new board, change files under “board” folder, for example pins, uart number, here directly copy from SDK demo for LPCxpresso55s06 board. 6 - Test the project  function with new board Build project until no compile error, download and run it, result as below.        
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Symptoms Many LPC55 users experienced connection failure when using ISP USB0 for firmware update. In practice, we don’t suggest user updating firmware via ISP USB0 for LPC55(S)6x/ 2x,LPC55(S)1x/0x parts. Diagnosis LPC55 USB0 is Full Speed USB port. The default setting of CMPA turns off the USB0 port. Some users may reconfigure CMPA to enable ISP USB0 in order to use ISP USB0 BOOT, but this is not recommended in practice. LPC55 ISP USB0 uses internal FRO as clock source. According to LPC55 data sheet, the FRO accuracy is only +-2%, while the FS USB data rate tolerance specification is +-2500ppm(+-0.25%). Obviously, the LPC55 FRO spec can’t meet the USB0 clock accuracy requirement. See below extraction from NXP manuals. Fig 1. The accuracy of FRO ( Extracted from LPC55S69 Datasheet )   Fig 2. The accuracy requirement of USB FS( Extracted from TN00063 )  Some users may wonder why USB0 can use internal FRO as clock source in the user application?  Whenever internal clock source FRO is used as USB0 clock source, we must calibrate FRO in source code for communication. That’s to say, trim FRO to an accurate frequency. We can see FRO trim in many MCUXPressoSDK USB demos. When using FRO as the USB0 clock source, in order to ensure the USB0 clock accuracy, we must use the USB0 SOF frame synchronization to calibrate the FRO in order to ensure the accuracy of FS USB clock source (reference design of TN00063, TN00063-LPC5500 Crystal-less USB Solution). Unfortunately, the BOOT ROM of LPC55 does not support USB SOF calibrating FRO. As a result, even if we enable ISP USB0, the FRO clock drift can still cause USB0 communication failure under non-room temperature conditions. Solution Since ISP USB0 is not recommended for firmware update, the user manual no longer announces the enablement bit of ISP USB0 in CMPA. If you need to use USB0 for firmware update, we recommend using ISP USB1 (High Speed USB), because USB1 uses accurate external clock source which can ensure the ISP USB1 working stable. In addition, the communication protocol of ISPUSB complies with BLHOST specification. For details, see:  blhost User's Guide - NXP  
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This article mainly introduces how to use CTIMER measuring pulse-width in LPC845, in fact, it can applies to all LPC products  including CTIMER modules. 1  CTIMER has below features: A 32-bit timer/counter with a programmable 32-bit prescaler. Four 32-bit match registers that allow interrupt generation on  match. The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.(This article mainly use this feature.) Up to four match registers can be configured for PWM operation.   2 Introduction There is neither pulse-width measurement nor input capture demo under SDK, so write this article and related code for this topic. The principle is clearing the timer and prescaler on the leading edge of an input and capturing the timer valued on the trailing edge.   3  Main steps   Step1 Choose CAP input channel, capture edge, and enable interrupt if needed. Using “Capture control register”. The Capture control register is used to control whether one of the four capture registers is loaded with the value in the timer counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, n represents the timer number, 0 or 1. In this example, choose capture channel 0 as input channel, falling edge as capture edge, and enable capture interrupt. SDK code: CTIMER_SetupCapture(CTIMER,CTIMER_CAP0_INT,  CTIMER_CAP_FALL,TRUE); Step2 Select which capture input edge will cause the timer and pre-scaler to be cleared. Using “Count control register”. The Count Control Register (CTCR) is used to select between timer and counter mode, and in counter mode to select the pin and edge(s) for counting. When counter mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the APB bus clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. The timer counter register is incremented only if the identified event occurs and the event corresponds to the one selected by bits 1:0 in the CTCR register. Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the APB bus clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input cannot exceed one half of the APB bus clock. Consequently, duration of the HIGH/LOWLOW levels on the same CAP input in this case cannot be shorter than 1/APB bus clock. Bits 7:4 of this register are also used to enable and configure the capture-clears-timer feature. This feature allows for a designated edge on a particular CAP input to reset the timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge, permits direct pulse-width measurement using a single capture input without the need to perform a subtraction operation in software. In this example, we choose timer mode, configure Channel 0 rising edge clearing the timer, enable clearing of the timer and the pre-scaler. SDK code:   CTIMER->CTCR = CTIMER_CTCR_CTMODE(0)|CTIMER_CTCR_SELCC(1)   |CTIMER_CTCR_ENCC_MASK ; Step3 Read pulse-width value from “Capture register”. Each Capture register is associated with one capture channel and may be loaded with the counter/timer value when a specified event occurs on the signal defined for that capture channel. The signal could originate from an external pin or from an internal source.   SDK code: CTIMER_GetCAPCounter(HW_CTIMER0, HW_CTIMER_CH0); We can read capture value on capture interrupt. Detail code please refer to attached project, it based on MCUXpresso IDE v11.3, SDKv2.9, LPCxpresso845MAX board.   4  Test Result Input a signal as below into channel 0 (P1_0), pulse width is 10us. Print the measurement results on Console view of MUXpresso IDE:        
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There are two ways to program LPC chips using Flash Magic, ISP mode and  Single Wire Debug (SWD) mode. ISP mode support COM port, USB, CAN and Ethernet. SWD support LINK2(LPC1800/lpc4300) bridge and LPC11u35 bridge. This article uses four demonstrations to show these programming methods.   1. ISP mode   1.1 UART ISP Mode Demonstration   1.2 USB ISP Mode Demonstration 2. Single Wire Debug(SWD) Mode   2.1 SWD over Link2 Bridge     2.1.1 Introduction     2.1.2 Demonstration  2.2 SWD over LPC11U35    2.2.1 Introduction    2.2.2 Demonstration    2.2.3 Recover board   Download Flash Magic tool from: https://www.flashmagictool.com/ Pay attention use the new version Flash Magic v13.10 or later.   About detail steps please refer to attachment. Thanks!
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LPCXpresso804 board has a on-board debugger developed with LPC11U35. Old batches of the board uses the old firmware for LPC11U35 debugger. The old firmware has some issues such as that when you send a string through the debug COM port the LPC804 only can receive the first byte. The solution is easy. We can download the newest firmware for LPC11U35 and update the firmware for LPC11U35. Download the fimware. The firmware and driver can be download from this link. Update the firmware.(Details can be found in UM11083: User Manual for LPCXpresso804 Board) Hold down the reset button and keep it held down while applying power to the board. Release reset. Using File Explorer (or equivalent on Mac/Linux platforms), look at the available drives on your system. A device called CRP_DISABLED will appear. Delete the firmware.bin file on the CRP_DISABLED drive. Drag and drop the firmware.bin file you downloaded from nxp.com on to the CRP_DISABLED drive. Re-power the board. The board should now enumerate on your system - allow 20-30 seconds for this to complete.
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The documentation is only valid for the LPC55xx and LPC55Sxx families. In power down mode, some of peripherals for LPC55xx are power off, which means that the peripherals lose it’s power in power-down mode, so it is required to reinitialize the peripherals after waking-up from  power down mode. The DOC lists the peripherals which lose power in power down mode and are required to initialize, introduces the procedure to enter the power down mode, and  the procedure to reinitialize the peripherals after waking-up from power down mode. The doc is attached and power scheme is also attached.
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MCUXpresso SDK for LPC55xx uses FLASH API to implement FLASH drivers. Some user may meet issue when executes FLASH program code, for instance: status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8); After execution this code, nothing changed in the destination address, but error code 101 returns: This error code looks new, as it doesn’t commonly exist in other older LPCs. If we check FLASH driver status code from UM, code 101 means FLASH_Alignment Error: Alignment error Ah ha? ! Go back to the definition of FLASH_Program, status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); New user often overlooks the UM description of this API “the required start and the lengthInBytes must be page size aligned”. That’s to say, to execute FLASH_Program function, both start address and the length must be 512 bytes-aligned. So if we modify status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8); To status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 512); FLASH_Program can be successful.   !!NOTE: In old version of SDK2.6.x, the description of FLASH_Program says the start address and length are word-aligned which is not correct. The new SDK2.7.0 has fixed the typo.  Keep in mind: Even you want to program 1 word, the lengInBytes is still 512 aligned, as same as destAdrss! PS. I always recommend my customer to check FLASH driver status code when meet problem with FLASH API. We can find it in UM11126, Chapter 9, FLASH API. I extract here for your quickly browse:   Happy Programming
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The documentation discusses how to generate phase-shift PWM signals based on SCTimer/PWM module, the code is developed based on MCUXpresso IDE version 10.3 and LPCXpresso5411x board. The LPC family has SCTimer/PWM module and CTimer modules, both of them can generate PWM signals, but only the SCTimer/PWM module  can generate phase-shift PWM signals. In the code, only the match registers are used to generate events, I/O signals are not used.  The match0 register is set up as (SystemCoreClock/100), which determines the PWM signal frequency. The the match1 register is set up as 0x00, which generate event1. The the match2 register is set up as (SystemCoreClock/100)/2;, which generate event2. The duty cycle is (SystemCoreClock/100)/2-0x00= (SystemCoreClock/100)/2, which is 50% duty cycle, the cycle time is (SystemCoreClock/100). The event1 sets the SCT0_OUT1, event2 clears the SCT0_OUT1, so SCT0_OUT1 has 50% duty cycle. The the match3 register is set up as (SystemCoreClock/100)/4;, which generate even3. The the match4 register is set up as 3*(SystemCoreClock/100)/4, which generate event4. The duty cycle is 3*(SystemCoreClock/100)/4  -  (SystemCoreClock/100)/4= (SystemCoreClock/100)/2, which is 50% duty cycle. The event3 sets the SCT0_OUT2, event4 clears the SCT0_OUT2, so SCT0_OUT2 has 50% duty cycle. The phase shift is (SystemCoreClock/100)/4 - 0x00= (SystemCoreClock/100)/4, which corresponds 90 degree phase shift. PWM initilization code: //The SCT0_OUT1 can output PWM signal with 50 duty cycle from PIO0_8 pin //The SCT_OUT2 can output PWM signal with 50 duty cycle fron PIO0_9 pin //The SCT0_OUT1 and SCT0_OUT2 PWM signal has 90 degree phase shift. void SCT0_PWM(void) {     SYSCON->AHBCLKCTRL[1]|=(1<<2); //SET SCT0 bit     SCT0->CONFIG = (1 << 0) | (1 << 17); // unified 32-bit timer, auto limit     SCT0->SCTMATCHREL[0] = SystemCoreClock/100; // match 0 @ 100 Hz = 10 msec     SCT0->EVENT[0].STATE = 0xFFFFFFFF; // event 0 happens in all states     //set event1     SCT0->SCTMATCHREL[1]=0x00;     SCT0->EVENT[1].STATE = 0xFFFFFFFF; // event 1 happens in all states     SCT0->EVENT[1].CTRL = (1 << 12)|(1<<0); // match 1 condition only     //set event2     SCT0->SCTMATCHREL[2]=(SystemCoreClock/100)/2;     SCT0->EVENT[2].STATE = 0xFFFFFFFF; // event 2 happens in all states     SCT0->EVENT[2].CTRL = (1 << 12)|(2<<0); // match 2 condition only     //set event3     SCT0->SCTMATCHREL[3]=(SystemCoreClock/100)/4;     SCT0->EVENT[3].STATE = 0xFFFFFFFF; // event 3 happens in all states     SCT0->EVENT[3].CTRL = (1 << 12)|(3<<0); // match 3 condition only     //set event4     SCT0->SCTMATCHREL[4]=3*(SystemCoreClock/100)/4;     SCT0->EVENT[4].STATE = 0xFFFFFFFF; // event 4 happens in all states     SCT0->EVENT[4].CTRL = (1 << 12)|(4<<0); // match 4 condition only     //PWM output1 signal     SCT0->OUT[1].SET = (1 << 1); // event 1 will set SCT1_OUT0     SCT0->OUT[1].CLR = (1 << 2); // event 2 will clear SCT1_OUT0     SCT0->RES |= (3 << 2); // output 0 toggles on conflict     //PWM output2 signal     SCT0->OUT[2].SET = (1 << 3); // event 3 will set SCT1_OUT0     SCT0->OUT[2].CLR = (1 << 4); // event 4 will clear SCT1_OUT0     SCT0->RES = (3 << 4); // output 0 toggles on conflict     //PWM start     SCT0->CTRL &= ~(1 << 2); // unhalt by clearing bit 2 of the CTRL } Pin initialization code: //PIO0_8 PIO0_8 FC2_RXD_SDA_MOSI SCT0_OUT1 CTIMER0_MAT3 //PIO0_9 PIO0_9 FC2_TXD_SCL_MISO SCT0_OUT2 CTIMER3_CAP0 - FC3_CTS_SDA_SSEL0 void SCTimerPinInit(void) {     //Enable the     SCTimer clock     SYSCON->AHBCLKCTRL[0]|=(1<<13); //set IOCON bit     //SCTimer pin assignment     IOCON->PIO[0][8]=0x182;     IOCON->PIO[0][9]=0x182;     IOCON->PIO[0][10]=0x182; } Main Code: #include <stdio.h> #include "board.h" #include "peripherals.h" #include "pin_mux.h" #include "clock_config.h" #include "LPC54114_cm4.h" void SCT0_Init(void); void SCTimerPinInit(void); void P1_9_GPIO(void); void SCT0_PWM(void); int main(void) {       /* Init board hardware. */     BOARD_InitBootPins();     BOARD_InitBootClocks();     BOARD_InitBootPeripherals();     printf("Hello World\n");    // SCT0_Init();    // P1_9_GPIO();     SCTimerPinInit();     SCT0_PWM();     /* Force the counter to be placed into memory. */     volatile static int i = 0 ;     /* Enter an infinite loop, just incrementing a counter. */     while(1) {         i++ ;     }     return 0 ; } The Yellow channel is PIO0_8 pin output signal, which is SCT0_OUT1 PWM output signal. The Bule channel is PIO0_9 pin output signal, which is SCT0_OUT2 PWM output signal.
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Description This application provides a human interface via terminal (UART1) menus and numbered selections to select and play audible medical alerts that are generated algorithmically on the NXP LPC23xx. The medical alarms are designed to comply with the IEC 60601-1-8 standard for audible medical alarms. The IEC standard seeks to improve patient safety by standardizing medical audible and visual alarms. The audible portion of the standard specifies high, medium, and low priority alarms, and these are provided via a menu system. In addition, a test menu is added to facilitate analysis of the quality of the alarms generated and their compliance with the standard. Many previous applications used playback techniques to use pre-recorded alarm sounds for the alerts. An algorithmic approach provides a much more efficient, high-quality implementation compared to the pre-recorded sounds. Plus, the sounds can be customized to differentiate equipment while still staying within the parameter limits of the standard. Block Diagram Documentation     IEC Alarm Detailed Documentation Products Below are recommended microcontrollers for use in implementing this design to a system. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2364 100 128KB 34KB 128KB flash/34KB RAM version of LPC2368, no SD/MMC LPC2366 100 256KB 58KB 256KB flash version of LPC2368, no SD/MMC LPC2368 100 512KB 58KB + 8KB 100-pin version of LPC2378, no external bus LPC2378 144 512KB 58KB + 8KB 144 pin, similar to LPC2368 but more pins and a MiniBus (8-bit) LPC2387 100 512KB 98KB LPC2368 with 98KB SRAM LPC2388 144 512KB 98KB LPC2378 with 98KB SRAM and USB Host/OTG LPC2458 180 512KB 98KB + 8KB LPC2468 with 16-bit External Memory Interface LPC2460 208 0KB 98KB + 8KB Flashless LPC2468 LPC2468 208 512KB 98KB Host/OTG/device, 32-bit ext. bus, 512KB flash/98KB RAM, 208 pin package LPC2470 208 0KB 98KB + 8KB LPC2460 with XGA LCD controller LPC2478 208 512KB 98KB + 8KB LPC2468 with XGA LCD controller More Information Example Code IEC Alarm Example Code Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. documentation.pdf 395.85 KB example.code_.zip 255.55 KB
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In some early LPC products, such as LPC11xx, LPC17xx, LPC18xx, LPC40xx, LPC43xx, LPC8xx, etc, CRP is used to utilize code protection. CRP has three different security levels: Figure 1 shows the security levels of CRP1, CRP2, and CRP3. Figure 1 The LPC55 series (LPC55(S)0x, 1x,2x, and 6x) uses Secure boot and Protected Flash Region (PFR) configuration instead of CRP for security protection. The part number with S (eg. LPC55S) supports Secure boot, for instance, LPC55S28 and LPC55S06. However, non-S series products, such as LPC5506, LPC5528,  can only utilize code protection by configuring FPR related fields. CRP2 is the most commonly used protection level. With CRP2, SWD access is blocked, so users can not read, write, or erase Flash via SWD or ISP. In addition, users cannot erase part of Flash to modify existing code. Once in CRP2 mode, Flash can only be recovered by Mass Erase Flash, which effectively prevents attacker from reading and modifying the Flash code. Unfortunately, the LPC5500 device such as LPC55(S)0x, 1x,2x,6x doesn't have exactly the same functional mechanism as the CRP2, which is questioned by many users. However, if we need to achieve the same functionality as CRP2, we can configure CMPA to disable ISP and SWD debugging port. 1.   Disable ISP Customer Manufacturing/Factory Configuration Area (CMPA) is part of the PFR, Configure BOOT_CFG to select whether the ISP mode is enabled. Table 1 shows the field table starting with 9E40 word address in CMPA. ISP control domains have been marked in red (as shown in Table 1). Table 2 shows the mode selection of ISP domains, 111 is ISP disabled. If the ISP mode is disabled, set BOOT_CFG to 0b1110000. Word Address(HEX) Byte Address Field Description 6 5 4 3 2 1 0 9E40 9E400 BOOT_CFG Default ISP mode 0 0 0 0 9E404 SPI_FLASH_CFG 0 0 0 0 0 0 0 9E408 USB_ID USB Vendor ID 9E40C SDIO_CFG 0 0 0 0 0 0 0 9E41 9E410 CC_SOCU_PIN ISP_CMD_EN MCM33_DBGEN 0 0 0 0 0 9E414 CC_SOCU_DFLT ISP_CMD_EN MCM33_DBGEN TAPEN SPIDEN SPNIDEN DBGEN NIDEN Table 1 Default ISP mode Bit 【6:4】 Auto ISP 000 USB_HID_MSC 001 UART ISP 010 SPI Slave ISP 011 I2C slave ISP 100 Disable ISP 111 Table 2 2.   Disable SWD The DCFG_CC_SOCU is a configuration that specifies debug access restrictions per debug domain. These access restrictions are also referred as constraint attributes in this section. The debug subsystem is sub-divided into multiple debug domains to allow finer access control. Figure 2 shows debug domains and their corresponding control bit position in DCFG_CC_SOCU. Logically, DCFG_CC_SOCU has two components: SOCU_PIN and SOCU_DFLT. The SOCU_PIN and SOCU_DFLT registers are used together to define SWD debug access for the module. Which is logically composed of two components: SOCU_PIN: A bitmask that specifies which debug domains are predetermined by device configuration. SOCU_DFLT: Provides the final access level for those bits that the SOCU_PIN field indicated are predetermined by device configuration. In another words, set the corresponding bit of SOCU_PIN and SOCU_DFLT register to 1 at the same time to enable the module. This module is disabled by setting the corresponding bits of the SOCU_PIN and SOCU_DFLT registers to 0 simultaneously. See Figure 2. Figure 2 Note that the default value of CC_SOCU_PIN and CC_SOCU_DFLT in LPC55 PFR are all zeros. Therefore, in this case, although SOCU_PIN and SOCU_DFLT are both 0, the bit reverse rule is not met (Figure 3 below). Therefore, all debugging permissions are enabled by default when CC_SOCU_PIN and CC_SOCU_DFLT are all 0. Figure 3 Note: the distinction between CC_SOCU_PIN(CC_SOCU_DFLT) and SOCU_PIN(SOCU_DFLT). The former with CC_ includes the reverse bit of the latter. For example, if SOCU_PIN and SOCU_DFLT are set to all zeros and the reverse bit is set to 1, all SWD modules are disabled. Figure 4 3. Implementation The following uses LPC5506 as an example to configure the CMPA field: 3.1  Disable ISP and SWD Figure 5 Keep the default CMPA values except for the two highlighted in red in Figure 5. 1) Set BOOT_CFG to 0x70 to disable ISP. 2) Set all SOCU_PIN and SOCU_DFLT to 0, and set all reverse bits to 1. That is, disable all debug accessing subdomains. 3.2 Enable ISP and SWD Figure 6 Keep the default CMPA values except for the two highlighted in red in Figure 6. 1) Set BOOT_CFG to 0x00 to enable Auto ISP. 2) Restore the default values of DCFG_CC_SOCU, that is, CC_SOCU_PIN and CC_SOCU_DFLT to all zeros. in this case, all debug permissions are restored (turned on) because the rule of bit reversal is not met (see Part 2 of this article). 3.3 Code Implementation Enable or disable the SWD and ISP functions by serial command (1 or 0). Figure 7 The demo code is attached. This routine has been tested on the LPCXpresso55S06 development board. NOTE:     As system security requirements and the attack surface evolves, it is important for customers to understand the types of attacks (especially advanced physical attacks) which NXP does not claim to protect against, or strongly mitigate, so that appropriate mitigation can be taken by the customer at the system level if necessary.  
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The minimum saturation current spec of Inductor is 300mA in the LPC55xx internal DC/DC converter, why is it 300mA, what is the actual current flowing through the inductor? 1)This is internal DC/DC converter block diagram for LPC55xx, on the LX pin, the 4.7uH inductor and 22uF capacitor are required, the FB pin is the detected pin to sense the output voltage, the DC/DC converter provide about 1.1V power for the VDD_PMU power supply pin. Let's discuss the current flowing through the inductor L1 via LX pin   2)compute the actual current flowing the inductor The above circuit is the illustrating block diagram, the control regulation uses PWM signal to control the MOSFET, but the high time of the PWM signal is constant for each PWM cycle, in other words, the on-time of the MOSFET is constant, for the LPC55S69 internal DC/DC converter, the on-time Δt is 0.52us, which means that the interval of MOSFET turning-on time is 0.52us. Assume that the VDC_IN is 3.3V, the output voltage of the DC/DC converter is 1.1V, the constant high time of the PWM signal is 0.52uS. when the MOSFET is on, the capacitor will be charged.   The above figure is the waveform tested on the LX pin of LPC55S68 on the LPC55S69-EVK board, you can measure via scope that the high time of the yellow PWM signal is 0.52uS, during which the MOSFET turns on, the capacitor is charged. The inductor works in DCM mode(discontinuous current mode)   The incremental current flowing the inductor during the MOSFET turns on: ΔI= (VDC_IN-VDC_OUT)* Δt/L=(3.3V-1.1V)*0.52*10**(-6)/4.7*10**(-6)=243mA.   3)The actual flowing current through the inductor is about 250mA for each PWM cycle, so when you select the inductor, the saturation current spec must be greater than actual current, the minimum required saturation current spec for the 4.7uH inductor is 300mA, when you select inductor for the DC/DC converter, you should select the inductor with 300mA or above saturation current .
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The example demos how to use ARM TX Event to trigger ADC based on LPC55S69-EVK board and MCUXPresso IDE and SDK. As the Table 753, the “ARM tx event” is the one of the ADC triggering source, although it is a hardware triggering, but the mechanism is the same as software triggering, after ADC configuration, you execute the instruction asm(“SEV”); the ARM tx event will be generated and trigger ADC to sample. The ADC of LPC55xx support hardware trigger mode, each hardware trigger source corresponds to a trigger register, as the Table 753, the ARM tx event ASC triggering source index is 11, so you have to initialize the ADC trigger control register TCTRL11. In the TCTRL11 register, you can assign the command ID, select the FIFO0 or FIFO1 to save the ADC result, enable hardware triggering.    
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Contents     Introduction to OPAMP. ........................................1     Usage of LPC5536-OPAMP. ................................2 2.1 Follower OPAMP. .................................................2 2.2 Non-inverting OPAMP. .........................................3 2.3 Differential OPAMP. ..............................................3     Test Preparation of LPC5536-EVK. ......................4     Test Result ............................................................5 4.1      Follower Test ....................................................6 4.2      Non-inverting Test ............................................7 4.2.1 Error Analysis. ...................................................7 4.2.2 Gain Error and Output Offset Error ...................8 4.2.3 OPAMP Output Error .........................................9 4.4 Differential Test ...................................................10     Conclusion. .........................................................11   The Article shows the OPAMP performance test that the precision of LPC5536-OPAMP matches the description in the product data sheet. The gain error is less than 5%, and the input offset voltage is less than 5mV, which can meet the presicion need to a certain extent. It is worth mentioning that the output error of LPC5536-OPAMP is very small at low magnification. For example, the full-range error is just single-digit mV at the magnifications of 2X and 5X in non-inverting mode. For scenarios requiring higher precision, users can connect the external high-precision resistors to achieve higher output precision.  The article includes detailed test steps and EVK board settings. For detail, see attached article.  
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Because the LPC55S69 has PowerQuad, in SDK example code, the FFT/FIR/IIR and the other DSP function are implemented by the Powerquad module instead of the Cortex-CM33 core.  This is the Powerquad example to implement the DSP function:'   But if customers want to use CMSIS-DSP to implement the DSP function based on Cortex-CM33 instead of Powerquad module, customers can not import SDK example, he has to create a new project, this is the procedures: 1)Create a new project by clicking New->Create a new C/C++ Project   2)select the processor like LPC55S69 3)In the following menu,click CMSIS Driver, and check the CMSIS_DSP_Library and CMSIS_DSP_Library_Source You have to click the Driver which can select your peripherals driver you will use.    3)as the following screenshot, after completion, you can see the CMSIS-DSP source code and library have included in the project    
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As a free and open-source graphics library, LVGL provides great convenience for related series of chips in creating animations, building advanced graphics and building various blocks. LVGL has been integrated into the MCUXpresso SDK package, which can be imported either through the SDK download or directly in the GUI Guider. GUI-Guider is a ready-to-use GUI from NXP. On the basis of being free for NXP equipment, it has a series of advantages such as convenient operation, automatic programming, Chinese and English interface and input. The following takes the LPC54S018 development board as an example, by creating a simple UI interface, to let everyone familiar with its basic operation process and usage. Create new project Select V8 lvgl version, LPC54S018 development board, EmptyUI, set the name and path, click Finish Fig.1 Set the overall background Drag Widget Tab to the GUI Editor, and resize it to full screen size. Fig.2 Add time display and to-do functions. 1) Change the Tab Content1 name to Clock in the red box on the right. Fig.3 2) Drag aclock into editor, adjust its size and position, and set the time according to the red box in Figure 4. Fig.4 3) Drag the dclock clock into the editor, adjust its size and position, and set the time according to the red box in Figure 5. Fig.5 4) Drag the checkbox into editor, adjust its size and position, and edit its content according to Figure 6. Fig.6 In the second Tab content, add a simple counting function and set the progress bar to interact with it. 1) Add a background. Click Import to import the background image, in the widget, drag the image into the editor, set the size and position, select the imported image in the image path and set its transparency, as shown in Figure 7. Fig.7 2) Add count value, progress bar and button. Figures 8, 9 and 10. In Figure 8, when adding a progress bar, set the starting value in the second step. The range value of the progress bar is set by lv_bar_set_range(guider_ui.screen_progress_bar, 0, 100) which can be added to a key event, executing on every click. Therefore, it is recommended to add this code to the subsequent export file costomer.c, and set it once during initialization. Fig.8 Fig.9 Fig.10 3) Add some explanatory text to the progress bar. The operation steps are shown in Figure 11. Fig.11 4) Create an event in the corresponding button, select Customer Code, write the corresponding code, and complete the interaction. Take the ADD button as an example, as shown in Figure 12. Fig.12 In the Tab third content, 3D animation effect is shown. 1) Set the 3D picture. Select 3Dimg, drag it into the editor, set the image in the image path, and then select the rotation center and rotation angle, as shown in Figure 13. Fig.13 2) Set the display switch. Turn on the switch to display the 3D picture, and when the switch is turned off, the picture disappears. Such as Figure 14. Fig.14 In the fourth Tab content, add “help”. 1) Add logo. Add img, import image to set transparency. Fig.15 2) List the first three modules. Drag the list Widget into the editor, create new lines and modify pictures and texts. After completion, generate the code as shown in Figure 16. The results can be directly displayed by simulation or imported into the development board. Figure 17 shows the simulator and selectable target. The simulation results are shown in Figure 18. There are two ways to download the design to the development board. One is to select the available IDE in Figure 17 and download it directly through GUI Guider. The second is to export the source files first, replace them one by one in the relevant SDK demo code, build with application code in IDE and download/debug with IDE debugger. Fig.16 Fig.17 Fig.18 Video Class : https://www.youtube.com/watch?v=QM52Nu16zKQ  
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  This article mainly introduces how to re-enable SWD after disabled. Problem description The ECRP (Enhanced Code Read Protection) of LPC546xx series is used to configure different security levels of the user program. It is configured at the offset 0x20 of the boot image file and used in conjunction with OTP. Users of LPC546xx can disable SWD, ISP by configuring ECRP value. Some users need to restore after disabling SWD, they can use the "unlock LPC546xx" command in J-link commander. For example:   But for some chips, this method still fails to recover SWD. This paper presents a method to restore SWD based on LPC-LINK2. When using the "unlock LPC546xx" command does not work, you can try the method in this article. Theoretical analysis and solutions Customer’s example: LPC54605:Configure ECRP to 0x00015800. After disabling SWD, it needs to be restored. When the ECRP value is 0x00015800, we analyze from high to low through  user manual. In ECRP, 31:18 bits are reserved, and 17:16 bits determine the status of SWD. In this example, 17:16=01 ,this means that SWD is disabled.   15: 14 =01, it is not allowed to enter ISP through IAP call.   13: 12 = 01, it is not allowed to enter ISP through pin.   11: 10 = 10, IAP sector erase / write protection is disabled, so sector protect (5:0) is ignored.   At this point,  SWD (17:16) is DISABLED, ISP Entry from ISP (15:14) is DISABLED, and ISP Entry from Bootloader (13:12) is DISABLED, the IAP Mass Erase can still be used to erase the entire Flash to recover a device. as long as the OTP MASS ERASE is ENABLED. If the OTP has been configured and bit 4 is set to 1, that is, disabled mass erase command, the SWD can never be recovered again. When Mass Erase is enabled, the Debug Mailbox is also enabled and allows a debugger to communicate with the bootloader to execute a Mass Erase.   Therefore, the Debug Mailbox can be used to perform Mass Erase operation and restore ECRP settings. To achieve the purpose of re-enabling SWD. Operation steps IDE: MCUXpressoIDE_11.4.0_6237 or other versions IDE installation path: C:\nxp\MCUXpressoIDE_11.4.0_6237 Tool script: LPC546xxMassErase.scp Tool script path: C:\nxp\MCUXpressoIDE_11.4.0_6237\ide\binaries\Scripts Other versions of MCUXpressoIDE and other installation paths operate the same.   1)Put LPC546xxMassErase.scp script in the path: C:\nxp\MCUXpressoIDE_11.4.0_6237\ide\binaries\Scripts 2) Open a command prompt window. 3) Change the path to C:\nxp\MCUXpressoIDE_11.4.0_6237\ide\binaries.   4) Execute the command of redlinkserv-commandline. 5) After executing the redlinkserv -commandline command, you should see the redlink> prompt.   6) Execute the load command "C:\nxp\MCUXpressoIDE_11.4.0_6237\ide\binaries\Scripts\LPC546xxMassErase.scp". 7) After executing the load command, you should see "LPC546xxMassErase.scp" being loaded.   😎 Execute the run command. 9) After executing the run command, you should see the following message.   At this point, the SWD interface can be used for normal debugging. Query ECRP level In the LPC546xx user manual, we can see  ISP-AP command, one function is query the ECRP  level, that is, to view the ECRP configuration of this chip.   From the log in part 3, we can see the returned ECRP level:   However, there is no explanation in the user manual, so here we show the meanings of each bit. There is a table translation from the ECRP level user defined and the ECRP definition used by the ROM code: /* Feature bit defines */ #define CRP_JTAG_EN_BIT         (1 << 6) #define CRP_MASS_ERASE_DIS_BIT  (1 << 7) #define CRP_IAP_PROT_EN_BIT     (1 << 😎 #define CRP_ISP_PINS_EN_BIT     (1 << 9) #define CRP_ISP_IAP_EN_BIT      (1 << 10) #define CRP_DBG_MBOX_EN_BIT     (1 << 11) #define CRP_COUNT_MASK          0x3F #define CRP_DEFAULT_FEATURES    0xFFFFFFFF #define CRP_MASS_ERASE_ONLY     (CRP_SECT_ERASE_DIS_BIT) For example: In CRP_JTAG_EN_BIT, 1 is JTAG/SWD enabled and 0 is disabled. It’s corresponding to ECRP value bit 17 and 16. In CRP_MASS_ERASE_DIS_BIT, 0 is Mass Erase allowed and 1 is disallowed. It’s corresponding to the combination of ECRP value bit 0~5, bit 10~11, and bit 14~15. In CRP_IAP_PROT_EN_BIT, 1 is IAP protection enabled and 0 is disabled. It’s corresponding to ECRP value bit 14~15. In CRP_ISP_PINS_EN_BIT, 1 is ISP pin enabled and 0 is disabled. It’s corresponding to ECRP value bit 12~13. In CRP_ISP_IAP_EN_BIT, 1 is ISP in IAP mode enabled and 0 is disabled. It’s corresponding to ECRP value bit 14~15. In CRP_DBG_MBOX_EN_BIT, 1 is ISP-AP or debugger mailbox enabled and 0 is disabled. It’s corresponding the combination of some reserved ECRP bits and OTP setting. Of course, all these ECRP value used by the ROM not only look into the user defined ECRP value but also check the OTP setting. When “Query ECRP Level” is called, it returns the value used by the ROM code, but not the ECRP value programmed in the image by the user.   Summary: In  LPC546xx series,  debugger can communicate with  LPC546xx through  Debug mailbox even if SWD is disabled. As long as the OTP does not disable the Mass Erase function, debugger can request LPC546xx to execute mass erase through Debug Mailbox to restore the SWD function. In addition, this article also supplements the specific meaning of  return value using ISP-AP command.  
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  需求: 客户需要对Image文件做出完整性检测,利用IDE固有功能添加这类信息简便且可靠,以往有类似的link提到了这些配置,对于LPC55系列,需要做一些更新。 CRC Checksum Generation with MCUXpresso IDE - NXP Community Solution 基于MCUX环境 下载 SRecord http://srecord.sourceforge.net/ srec_cat.exe是下载后我们主要使用的工具,通过为其添加一个系统变量名,将SRecord目录加入系统路径     重启MCUX IDE之后可以在工程配置中看到该变量:       创建一个脚本文件crc_add.txt,放在debug目录下,用于填充app后的flash空余位置为0xFF, 并后续生成CRC32值并放置0x00037FFC位置。最终生成的srec文件为包含所有内容的image。           # srec_cat command file to add the CRC and produce application file to be flashed # Usage: srec_cat @filename #first: create CRC checksum lpcxpresso55s06_hello_world_image_length_MCUX.srec # input file #-fill 0xFF 0x00000000 0x00038000 # fill blank code area with 0xff from 0x00000000 to 0x00038000 (0x00038000是把LPC55S06的末尾地址稍往前提,实际因为0x0003D7FF) -fill 0xFF 0x00000000 0x00037FFC #填充0-0x37FFC区间的未用地址为0xff -crop 0x00000000 0x00037FFC # just keep code area for CRC calculation below , 保留这段区间的内容,排除除此范围内的其他数据 #-CRC16_Big_Endian 0x00037FFE -CCITT # calculate big endian CCITT CRC16 at given address., 为以上空间数据计算CRC16,并放置在0x00037FFE地址,2字节 -CRC32_Little_Endian 0x00037FFC -CCITT #CRC32 -crop 0x00037FFC 0x00038000 # keep the CRC itself #second: add application file lpcxpresso55s06_hello_world_image_length_MCUX.srec # input file -fill 0xFF 0x00000000 0x00037FFC # fill code area with 0xff -crop 0x00000000 0x00037FFC #-crop 0x10000000 0x10000170 0x10000172 0x10010000 #keep all except CRC #finally, produce the output file -Output # produce output lpcxpresso55s06_hello_world_image_length_MCUX_crc.srec      创建一个crc_file_convert.txt文件,也放在debug目录下,用于将上一步生成的最终image的srec文件转换为bin文件,用于生成或者比对 # srec_cat command file to add the CRC and produce application file to be flashed # Usage: srec_cat @filename #third: create bin file lpcxpresso55s06_hello_world_image_length_MCUX_crc.srec -o lpcxpresso55s06_hello_world_image_length_MCUX_crc.bin -binary 在IDE的Post build栏目添加如下命令:     arm-none-eabi-size "${BuildArtifactFileName}"   默认自带的统计image size功能 arm-none-eabi-objcopy -v -O binary "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.bin"    将image转成bin文件,用于后续使用和比对 arm-none-eabi-objcopy -v -O srec "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.srec" & srec_cat.exe @CRC_add.txt 填充image,计算CRC32,整合成新的srec image srec_cat.exe @CRC_file_convert.txt  将上一步得到的srec image转化为bin文件,用于后续使用和比对   《hello_world_image_length_MCUX》例程会自行统计应用程序的CRC32值,并于IDE产生的CRC32值做比对   这里需要注意的是,由于MCUX IDE是借助于外部工具来填充flash和计算CRC32,所以默认IDE调试和下载选择afx文件并不包含这些信息。当校验程序开始运行,会发生: 读写未写入的flash,对于LPC55系列会发生hardfault CRC32值并不存在 所以测试这个程序需要单独下载包含所有的srec文件或者bin文件,而不是默认的afx文件。      
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1    introduction The doc demonstrates how to use MRT(Multi-rate Timer) module to implement the delay function, the delay time is programmable. The MRT has a One-shot stall mode, with the mode, while the MRT channel counter counts down, the core stalls until the MRT channel counter reaches to zero. After the MRT channel counter reaches to zero, the MRT channel becomes idle, the core continues to work.   2 delay function description Sometimes, it is expected that there is a programmable delay between two instructions, for example Instruction 1 Delay Instruction 2 In general, the delay function can be implemented by forcing the core to execute __asm(“NOP”) instructions This code is like: Void delay(uint32_t interval) {        Uint32_t counter;        Counter=ConvertTimeToCounter(interval);        For(uint32_t i=0; i<counter); i++)        {        __asm(“nop”)        } }   The macro convertTimeToCounter is used to convert a time to a number of loop   1.   MRT feature The MRT module of LPC family provides a unique feature called One-shot stall mode, because the test is based on LPC55S69-EVK board, so I referred to the section 27.5.3 One-shot stall mode in UM11126.pdf. The MRT does not have external pad.   One-shot stall mode: Bus stall mode can be used when a short delay is need between two software controlled events, or when a delay is expected before software can continue. Since in this mode there are no bus transactions while the MRT is counting down, the CPU core stalls, consumes a minimum amount of power during that time until the MRT counter reaches to zero. Therefore the One-shot stall mode of MRT can make core stall during the MRT counting down process, the delay function can be implemented.   3 MRT clock source and delay time For the LPC55S69, the clock source of MRT module is the AHB Bus clock, which is the same as the core clock. For the LPC55S69 example, there is the code to set up the core clock void BOARD_InitBootClocks(void) {     BOARD_BootClockPLL150M(); } So the  MRT clock frequency is 150MHz.       The delay time is a time, but the MRT is a counter, so the delay time must be converted to the counter value. The counter value is dependent on the MRT clock frequency. The MRT clock source is AHB bus clock, or the core clock. The LPC55S69 core clock frequency is 150Mhz, so we can define #define MRT_CLOCK_FREQUENCY 150MHz If the required delay time is delay_time variable in second unit, the required MRT counter value is   MRT counter value=delay_time/(MRT clock cycle time)=delay_time* MRT_CLOCK_FREQUENCY.   For example, assume the required delay_time is 1mS or 1*10**(-3)  Second, the corresponding counter value is 1*(10**-3)*150*(10**6)=150 000   The MRT delay time restriction. The MRT counter register is 24 bits, the maximum counter value is 2**24= 16,777,216, the maximum delay time is 16777216/(150*10**6)=0.111848 S or 111 mS.     3 source code description MRT delay function source code is based on SDK package SDK_2_11_1_LPCXpresso55S69.zip, the tools is MCUXpresso IDE v11.5.0. The example is run on LPC55S69-EVK The example uses MRT to delay 100mS(0.1 Second), after the delay, a LED is toggled The MRT counter value is 0.1S*150*(10**6)=15 000 000   For the mrt_init() api function, it initializes the MRT and set the MRT channel0 in OneShotStall mode. Once the core executes the line MRT_StartTimer(MRT0, kMRT_Channel_0, 15000000); the MRT channel0 counter will count down from 15000000, during the counting process the Cortex-M33 will stall. After the counter reach to ZERO, the core finishes the stalling mode and continues to execute the next line, the MRT channel0 counter will be in idle mode.       /**  * @file    LPC55S69_Project_mrt_stall.c  * @brief   Application entry point.  */ #include <stdio.h> #include "board.h" #include "peripherals.h" #include "pin_mux.h" #include "clock_config.h" #include "LPC55S69_cm33_core0.h" #include "fsl_debug_console.h" #include "fsl_mrt.h" #include "fsl_iocon.h"   /* TODO: insert other include files here. */ #define BOARD_LED_PORT BOARD_LED_BLUE_GPIO_PORT #define BOARD_LED_PIN  BOARD_LED_BLUE_GPIO_PIN /* TODO: insert other definitions and declarations here. */ void mrt_init(void); /*  * @brief   Application entry point.  */ int main(void) {       /* Init board hardware. */     BOARD_InitBootPins();     BOARD_InitBootClocks();     BOARD_InitBootPeripherals(); #ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL     /* Init FSL debug console. */     BOARD_InitDebugConsole(); #endif     mrt_init();     PRINTF("Hello World\n");     for(;;)     {     MRT_StartTimer(MRT0, kMRT_Channel_0, 15000000);     GPIO_PortToggle(GPIO, BOARD_LED_PORT, 1u << BOARD_LED_PIN);     __asm("nop");       }     /* Force the counter to be placed into memory. */     volatile static int i = 0 ;     /* Enter an infinite loop, just incrementing a counter. */     while(1) {         i++ ;         /* 'Dummy' NOP to allow source level single stepping of             tight while() loop */         __asm volatile ("nop");     }     return 0 ; }   uint32_t mrt_clock; mrt_config_t mrtConfig; void mrt_init(void) {           /* mrtConfig.enableMultiTask = false; */         MRT_GetDefaultConfig(&mrtConfig);           /* Init mrt module */         MRT_Init(MRT0, &mrtConfig);           /* Setup Channel 0 to be repeated */         MRT_SetupChannelMode(MRT0, kMRT_Channel_0, kMRT_OneShotStallMode);           //MRT_StartTimer(MRT0, kMRT_Channel_0,  15000000);   }       }                                                                                                              When the above code is running, user can see the blue LED toggles on the LPC55S69-EVK board. Connecting the PIO1_4 pin signal ( the pin 5 of P18 connector) on LPC55S69-EVK, the PIO1_4 signal toggling frequency is 5Hz, the cycle time is 200mS, so the delay is 100mS.      
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