ROM Bootloader KL43 chip with Kinetis Bootloader residing in the on on-chip read-only memory (ROM), can interface with USB, I2C, SPI, and LPUART peripherals in slave mode and respond to the commands sent by a master (or host) communicating on one of those ports. When KL43 chip with a blank flash, the Kinetis bootloader will execute automatically. Once the flash is programmed, the value of the FOPT field at Flash address0x40D will determine if the device boots the ROM bootloader or the user application in flash. The FTFA_FOPT [BOOTSRC_SEL] will select if boot from customer application (Flash) or boot from ROM bootloader. For example:       When Flash address 0x40D value is 0xFF, boot source is ROM bootloader;       When Flash address 0x40D value is 0x3D, boot source is Flash (Customer application). There with hardware pin(/BOOTCFG0) to control if boot from user application or ROM bootloader with FTFA_FOPT[BOOTPIN_OPT] bit . When FTFA_FOPT[BOOTPIN_OPT]  = 0, it forces boot from ROM if /BOOTCFG0 pin set to 0. blhost utility application The blhost utility is an example host program used to interface with devices running the Kinetis bootloader. The blhost application is released as part of Kinetis bootloader release package available on www.freescale.com/KBOOT . The blhost application default located at C:\Freescale\FSL_Kinetis_Bootloader_1_1_0\bin\win folder. About how to use blhost application, please check KBLHOSTUG document for more detailed info. Call Rom Bootloader from customer application In general, if customer application was programmed, the boot option should be change to Boot from Flash. If customer want to call the ROM bootloader during the application running, customer can refer below example. Set a signal for application code to call the ROM bootloader, such as press a button. In this demo, we use FRDM-KL43Z board SW3 (PTC3) to call the ROM bootloader. //Initalize PTEC3 as GPIO button PORT_Init (PORTC, PORT_MODULE_BUTTON_MODE, PIN_3, 0, NULL); GPIO_Init (GPIOC, GPIO_PIN_INPUT, PIN_3); The bootloader entry point for customer application to call the ROM bootloader.  //prototype of the entry point definition void run_bootloader(void * arg); //Variables uint32_t runBootloaderAddress; void (*runBootloader)(void * arg);   // Read the function address from the ROM API tree. runBootloaderAddress = **(uint32_t **)(0x1c00001c); runBootloader = (void (*)(void * arg))runBootloaderAddress; in <main.c> routine to call the ROM bootloader:   while (1)   {     if ((GPIOC_PDIR & (1 << 3)) == 0)     {       // Start the bootloader. runBootloader(NULL);     }   } Press SW3 button of FRDM-KL43Z board will call ROM bootloader.  Customer could continue to debug the code until the ROM bootloader be called. If customer debug into the runBootloader(NULL) function, there will stop at fixed address: 0x1C00_00C0. In fact, during call the ROM bootloader function , there will setting some parameters and then reset the KL43. When KL43 back from reset, it will boot from ROM bootloader. That reset will cause debugger disconnect with the KL43 product. More detailed info, please check attached demo code. BTW: The demo project is [frdm_led_test] inside of KL43 baremetal sample code, which could be downloaded from here.

       所谓“知识产权保护”，其实就是在产品量产之后防止其芯片内部代码通过外部调试器被有效读取出来的手段，毕竟现在来说硬件电路是比较容易被复制的，如果软件再不设防的话，在山寨技术如此发达的今天（用发达来形容貌似不是很过分吧，呵呵）这个产品估计很快就会被淘汰了。        因为最近有很多客户问到关于Kinetis的加密锁定问题，所以我觉着还是有必要对其细说说的。其实飞思卡尔对于知识产权保护方面还是做了很大的功夫的，而且使用起来也是比较方便的（这点很重要），具体可以参考Kinetis的Reference Manual中Security这一章，这里我就以在IAR环境下锁定K60为例介绍一下使用方法： 1. 首先简单介绍一下原理，即如果将K60置于Security状态（即锁定状态），则是不能通过Debug接口或者EzPort接口对芯片内部flash有任何操作的（CPU还是可以正常读写flash的，也就是说程序还是可以正常运行的，只不过是不能被外部非法读取了），当然“mass erase”命令除外（我们平时在Jlink Command窗口中敲入的unlock Kinetis命令就是触发这个命令给芯片的），通过“mass erase”命令可以再次将芯片擦除到出厂状态（即unsecure解锁的过程），这样芯片就又可以正常使用了（方便用户之后的程序升级）。咳咳，不过不用担心，解锁之后的芯片其内部的flash已经被完全擦除掉变为空片状态，也就是说内部的代码已经没有了，所以。。。懂的。。。呵呵； 2. 说完Security的原理，下面再聊聊K60实现security的process。我们可以通过K60的FTFL_FSEC寄存器中的SEC位来设定芯片的security状态，如下图所示，芯片默认出厂状态SEC位是为10的，即非加密锁定的，而如果将SEC位设定为00、01或者11任何一种情况，则芯片都将处于锁定状态（这就是我们接下来要干的事了，呵呵）。这里可能会有人疑问，在这个寄存器在重新上电之后会保存内容吗，我只能说“咳咳，都能抢答了”，哈哈，这正是我下面要说的； 3. K60在flash中0x00000400~0x0000040F这16个字节范围的地址定义为寄存器加载地址（Flash配置区），如下图所示，而这其中0x0000040C的地址内容在芯片上电之后会被自动加载到FTFT_FSEC寄存器中，也就是说我们只需要在烧写程序的时候把相应数据写到该flash地址即可在上电之后对芯片进行加密锁定，由此实现加密锁定。 4. 好了，原理和process都说完了，准备工作就做好了，下面就撸胳膊抹袖子开工干活吧，呵呵。其实飞思卡尔已经为我们做好了相关工作，只不过我们平时因为用不到没有注意到罢了。我们打开IAR环境，然后导入需要加密的代码工程，再打开工程目录下cpu文件组中的vectors.c和vectors.h（如果你的工程架构类似于飞思卡尔官方的sample code的话就在这个路径下）。在vectors.h里的最后部分我们会看到4个config段（共16个字节大小），如下图1，这四个段就是定义了上述0x400~0x40F的内容，其中CONFIG_4中最后的0xfe即为0x40C地址的内容（注意ARM处理器默认是little end模式的，所以0x40C在低地址），0xfe表明SEC位为10，即非加密状态，这样如果我把该0x40C地址的内容改成0xfc、0xfd或者0xff任意一个都可以实现对芯片的加密锁定。至于该四个配置段定义是如何映射到K60的flash区中的呢，去vectors.c文件中中断向量表vector_table[]的最后看看就知道了，如下图2； 5. 这里我们选择将CONFIG_4内容由原来的0xfffffffe改成0xfffffffd即可，然后保存编译通过之后，在查看其生成的s19文件中可以看到如下图所示，即0x40C地址的内容被修改成了0xfd，这样烧写文件就搞定了； 6. 当然到这一步实际上还没有完，其实在IAR的新版本之后（IAR6.6之后），其自带的flashloader默认是把0x400~0x40F这段保护起来的（防止误操作对芯片意外的security），即使如上面所述修改好相应内容，在烧写的过程中flashloader也不会对这段地址的内容做任何擦除和写入。为此还需要再额外对IAR的flashloader进行配置，具体步骤如下： （1）进入Options->Debugger->Download，选择如下： （2）点击“OK”，然后系统会提示保存该修改后的flashloader配置，建议把自己修改好的.board文件保存到自己的工程目录下，方便以后直接调用该flashloader。 7. 至此全部设置就搞定了，点击编译连接，然后下载，即可把加密后的代码烧写到芯片的flash里面去了。注意如果我们点击调试按钮的话，一旦程序烧进去之后调试器会自动复位芯片，此时加密状态位会被load到FTFT_FSEC[SEC]位中，芯片的调试端口就会被停掉，所以这时进入不到调试界面，而是弹出错误窗口，不用担心，因为此时程序已经正确烧到芯片中，我们重新插拔电源之后会看到程序已经正常执行，而此时的芯片已经处于加密状态。当然如果我们想再进入调试模式调试芯片的话，一种是通过Jlink Command窗口解锁，如下图1，另一种是再次点击调试按钮，会弹出解锁窗口，点击解锁即可，如下图2。 图1 图2

Hi, all The default AN2295 UART bootloader doesn't work well on K21/other Kinetis because of using FEI and complicated autocalibration mechanism. I made a simple version to make it works on MK21DX128VMC5, FYI. Readm.txt: UART bootloader for K21. (Default is MK21DX128VMC5) 128KB_Pflash_64KB_Dflash.icf is application link script example for MK21DX128 used together with UART bootloader, UART bootloader use 0x0 - 0xFFF. Q: Why need this patch? A: The original AN2295 use internal RC and FLL output as system clock. The calibration mechanism is not stable. The main change of this patch is to use external cystal plus PLL as system clock to communicate with PC software. Changes to AN2295 1) Add MK21D5.h for K21 support 2) Add AN2295_TWR_K21_cfg.h for K21 support(Copy from AN2295_TWR_K60_cfg.h) 3) AN2295_TWR_K21_cfg.h    1> #define KINETIS_MODEL K21_50MHz    2> #define KINETIS_FLASH FLASH_128K    3> #define BOOT_UART_BASE UART2_BASE_PTR       #define BOOT_UART_GPIO_PORT PORTE_BASE_PTR       #define BOOT_UART_GPIO_PIN_RX   17       #define BOOT_UART_GPIO_PIN_TX   16    4> #define BOOT_PIN_ENABLE_NUM        7 4) Add mcg folder and mcg.c/mcg.h 5) kinetis_params.h:    1> Modify SRS_REG/SRS_POR_MASK/INIT_CLOCKS_TO_MODULES to meet MK21D5.h    2> Add PORT_PCR_PS_MASK for BOOTLOADER_PIN_ENABLE_INIT to enable Pull-up. 6) bootloader.h: #define BOOT_WAITING_TIMEOUT 500. PC software can't communicate to bootloader if only 1s delay. 7) bootloader.c:    1> #include "mcg.h"    2> Use 25MHz PEE:       SIM_CLKDIV1 = ( 0    | SIM_CLKDIV1_OUTDIV1(1)                            | SIM_CLKDIV1_OUTDIV2(1)                            | SIM_CLKDIV1_OUTDIV4(1));             (void)pll_init(8000000,       /* CLKIN0 frequency */                      LOW_POWER,     /* Set the oscillator for low power mode */                      CRYSTAL,       /* Crystal or canned oscillator clock input */                      4,             /* PLL predivider value */                      25,            /* PLL multiplier */                      MCGOUT);       /* Use the output from this PLL as the MCGOUT */    3> Restore to FEI mode before jump to Application:       pee_pbe(8000000);       pbe_fbe(8000000);       fbe_fei(32768); Knowing issues: 1) Don't use virtualCOM from OSJTAG, it's very hard to communicate with PC software. Use RS232 in TWR-SER2. 2) BOOTLOADER_CRC_ENABLE must be 0, otherwise PC software will report unknown protocol version

In this document we are going to see how to use the attached code which implements the configuration of the FRDM-KL25 board as a USB HOST interfacing with a Numeric Keyboard and a 16x2 LCD. The project is compiled in the CodeWarrior IDE using Processor Expert and the Components to support the USB module of the USB Stack 4.1.1. How to add the Processor Expert USB components. The instructions to install the USB components to use them with Processor Expert are in the documentation of the USB Stack 4.1.1; here you can see the steps as well: Download the USB Stack 4.1.1 from the Freescale’s Website (USB Stack 4.1.1) Run the .exe file and install it in the default location. Open CodeWarrior and select Import Components in the Processor Expert button in menu bar. An Open windows will pop up, there you need to go to the path: <install folder>\Freescale USB Stack v4.1.1\ProcessorExpert\Components. To have the complete components and support for the USB module add each PEupd file repeating this step. Close CodeWarrior and open it again to ensure correct installation of the components. Check that the new components are available in the Components Library. About this Project. This project is based in the example code for Processor Expert in the USB Stack 4.1.1 USB_HID_MOUSE_HOST_MKL25Z128_PEx which implements the use of the FRDM-BOARD KL25 and a HID Mouse Device to interface with. In this project the HID Device is a Numeric Keyboard and the HOST Device (FRDM-KL25) is handling the data and printing them in a 16x2 LCD used in 8 bits mode (The LCDHTA component used here was created by Erich Styger; find the component an all the information about it here: http://mcuoneclipse.com/2012/12/22/hd44780-2x16-character-display-for-kinetis-and-freedom-board/ and say Thank you Erich: “Thank you Erich”). Here you can find a video of the implementation of this application: HID HOST WITH FRDM-KL25 The hardware components are: FRMD-KL25 Rev.E Adafruit Prototype Shield v.5 LCD JHD-162A Numeric USB Keyboard (Product Name: Numpad i110, Model No. GK-100010) USB _host Inside the project you can see there is a folder called USB_Host an it contains two important folders with source files: App_keyboard: Contains the specific function for the Keyboard configuration: in use, attached detached, callbacks and more; contain how to handle the data coming from the device. The function process_kdb_buffer is where the data is transmitted to the LCD and use it for the application. Classes: contain the necessary function to handle a hid as the device. Handle all the functions necessary for the USB protocol. Note: The usb_classes.c and usb_classes.h files are generated by processor expert. I attach these two files as well to have a reference how these files must look like. This is because sometimes during the code generation process Processor Expert erases part of the code. I hope this project is useful for you. Best Regards, Adrian.

Hi All, NXP provide a software driver library for Kinetis M devices, the KM bare-metal drivers. It includes support for peripherals and FreeRTOS. :smileyalert:NOTE: Before creating a new FreeRTOS project for KM devices you need to download the KM driver support package and install it. You can find the instructions HERE​. FreeRTOS new project creation The following instructions will guide you to generate a new project for Kinetis M devices with all the bare-metal drivers’ support. You can either select create a new project without FreeRTOS support or with it. In this case the instructions show how to create a FreeRTOS project for IAR 7.5. Go to template folder in the KM drivers package installation folder Run the make_project by Double clicking on it The make-project application guide the user to select the appropriate application. Select the IDE for new project support according to the application requirements. NOTE: The IDEs showed are only the IDEs that its support package is installed. The new project creation also manages the debug options for the project. Select the specific debug option for your new project. Select the KM variant you are using. NOTE: For KM34Z256 devices the default option is MKMxxZ256 and is selected automatically. The creation of the project supports creating linked or standalone projects: o   Create projects in driver’s subfolder: The project will be created in the path KMxxxSWDRV_Rx_x_x\build\supported_ide\projects and all the folders and files inside the project will be linked to the real location setting virtual folders in the workspace. In this case it will not be possible to move the project from that location, doing it will cause building problems. o   Create Standalone project: The standalone project option will let us select the new project location and will link the files to the actual project location. In this case the necessary source code will be copied to a new location. This options is recommended for versions control If option 1 is selected the project will be generated, you can check the project in the mentioned folder. If option 2 is selected following instructions need to be followed. Type the path that will contain the new project. In this path project files will be installed. Type project name and press enter. Project will be created and make_project window will self-close. Project folder structure looks like next: Open the IAR project by double clicking in the .eww file of the new project. FreeRTOS project structure This section will discuss the FreeRTOS default project and main.c file structure. Here a project created for IAR 7.5 is presented as an example. There are two main folders in a FreeRTOS application. The rest of the folders and files are the same for non-RTOS applications. freertos > contains all the FreeRTOS Kernel source code project > Contains files to configure definitions, FreeMaster usage and the main function. NOTE: The main function will be always contained in a file named project_name.c This is the structure of the project_name.c file: By default the main function contains the code to create and start two different tasks. Also, in the same file, the two tasks are defined. The main function initializes the application peripherals and create task A and task B. The xTaskCreate() function creates a new task and adds it to the list of tasks that are ready to run. The functions is defined as: pvTaskCode. Pointer to the task entry function. Tasks must be implemented to never return. pcName. A descriptive name for the task. This is mainly used to ease debugging. Max length defined by configMAX_TASK_NAME_LEN. usStackDepth. The size of the task stack specified as the number of variables the stack can hold - not the number of bytes. For example, if the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes will be allocated for stack storage. The stack depth multiplied by the stack width must not exceed the maximum value that can be contained in a variable of type size_t. pvParameters. Pointer that will be used as the parameter for the task being created. uxPriority. The priority at which the task should run. pvCreatedTask. Used to pass back a handle by which the created task can be referenced. After creating the two tasks the main functions calls vTaskStartScheduler() that starts the real time kernel. After calling the kernel has control over which tasks are executed and when. The task source code looks like the following: Tasks receive pvParameters parameter, this is the one that this passed when Task is created (refer to the pvPrameters in cTaskCreate function). Each task has an infinite loop, this means the task will run continuously but the RTOS schedules will the one deciding when each task will run according to priority. Default project can be modified by user adding tasks and using RTOS services to create application. If support for a different IDE is needed you just need to change follow the instructions decribed in FreeRTOS project creation and select the IDEs required by your application. References: FreeRTOS manual from THE TOOLCHAIN​ Hope information helps! Happy FreeRTOS coding! Regards, Adrian Cano NXP FAE

This example shows a FRDM-KL46Z interfacing with a Bluetooth-serial board BT_BOARD V1.05, it uses FREEMASTER to graph temperature and light sensor variables. Check how to connect, configure Bluetooth, and freemaster in attached document FRDM-KL46Z-Bluetooth-Freemaster.zip contains                            srec file                            firmware                            fremaster project (.pmp) Luis

Intro to Cortex-M0+ main features presented by Alejandro Lozano, Freescale, TIC. Intro to Cortex M0+. Kinetis L series description. Introducción al Cortex-M0+. Principales características presentadas por Alejandro Lozano, Freescale TIC. Introducción al Cortex-M0+ Descripción de la familia Kinetis L.

This hint will demonstrate how to verify ADC conversion rate (with oscilloscope) during testing phase.   Refer to the phenomenon descripted in"Figure 1. Voltage drops at ADC input during sampling process" of AN4373. If too large values is selected for the external RC components, serious voltage disturbances (voltage drops/peaks) at the ADC input (see Figure 1) can be observed. The disturbance at the ADC input in this case results from the basic principle of operation of the sample and hold (S/H) circuit inherent in a SAR ADC. Although we should avoid this happening, but it can be used to measure the ADC conversion rate with oscilloscope during testing phase.   According to the 'Table 30. 16-bit ADC operating conditions' of K64P144M120SF5, we can know that the max ADC conversion rate is 818.330 ksps. Here I create an example by using KDS3.2 with Processor Expert(See the attach file). After select same configuration according to that table, I got almost the same ADC conversion rate. The conversion time meet equation given in Reference Manual too. Now let's measure the ADC conversion rate on FRDM-K64F board with oscilloscope. After connected an external 1.5KΩ resistance, the value of external RC components is big enough to be observed. Below is the waveform observed with oscilloscope, the frequency between voltage drops at ADC input during sampling is about 818 ksps. This test result is consistent with the theoretical calculated value.

Simple guide to setting up a PIT to create a 1 second reccuring interrupt that toggles an LED without the use of processor expert.

Basic baremetal example to use I2C registers configuration. Original code obtained from TWR-K64F, usable on FRDM-K64F with adjustment. I hope it's useful.

Test environment: FRDM-K64F Rev.D IAR ARM Workbench IDE V8.30.1 MCUXpresso SDK for FRDM-K64F v2.4.2(2018-08-02) Test project is [ftm_output_compare] located with default path: ..\FRDM-K64F\boards\frdmk64f\driver_examples\ftm\output_compare Test reason to verify the CnV register is updated on the next FTM counter change. Three test signals: FTM0_CH0 pin as output compare pin will generate square signal with 1.33KHz . FTM0_CH1 pin generate 24KHz Edge-Aligned PWM signal(High-true pulses (clear Output on match)) with 50% duty cycle as FTM counter monitor. When FTM counter change, the FTM0_CH1 will toggle to output high voltage. Test using a delay() function to emulate modify FTM0_CH0 output compare mode and CnV value periodically. There is a GPIO pin will toggle after each delay() function to detect/verify the CnV value actual load point. FlexTimer module setting: The FTM0 refer clock is 60MHz For the FTM0_CH1 pin generate 24KHz PWM signal, the FTM0 MOD value is fixed to 0x9C3 (60MHz/24KHz = 2500).   Below is the overall signals: Test Process Record: During FTM0 module initialization, set the FTM0_CH0 pin output compare value to 0xA00 (more than MOD register value (0x9C3)) with below code: Set the CnV value more than MOD register is to avoid the output compare be set during at start. After that,  enable FTM0 counter and toggle GPIO pin to set a mark: After delay, toggle GPIO pin and update CnV register to 0x270 (the match point is half of the PWM high voltage). The actual signal is : After the first CH0 output compare set match, before set CH0 pin clear on match. It need to keep the CH0 pin with same output compare mode and set CnV back to 0xA00 (more than MOD) again with below code: Then we set CH0 with clear on match mode and update CnV value to 0x752 (middle of CH1 PWM low voltage): The actual signal is: With the similar code, before next CH0 set on match, it need to keep the CH0 pin with same match compare mode setting and CnV change back to 0xA00 (more than MOD). The actual signal is below: Note: During the output compare signal compare mode set/clear change phase, it need to keep previous output compare mode setting, please don't using kFTM_NoOutputSignal setting at code. Otherwise, the output compare signal will exist decay: Test Result: From FTM0 register value, the FTM0_SYNCONF[SWRSTCNT] bit is clear, which means select Legacy PWM synchronization method. The legacy PWM synchronization method will update Output Compare mode CnV register value at the next FTM counter change. The actual signal also verify it. Below is FTM0 all registers value: For the more detailed info, please check the original thread at here. Please check attachment about test code.

Nested Vectored Interrupt Controller Module by Vicente Gómez Freescale TIC. NVIC Explanation Hands-on IRQ using a pin. Interruption timers. Presentación de la NVIC (Nested Vectored Interrupt Controller) por Vicente Gómez, Freescale TIC. Explicación de la NVIC. Hands-On IRQ usando un pin. Timers con interrupción

Hi team ,      I would like to share an experiment that about the Fast IO - zero wait state access of KL series . Detail please refer to attached file . Best regards, David

Encrypted QuadSPI image Implementation       The Kinetis family of MCU includes the system security and flash protection features that can be used to protect code and data from unauthorized access or modification. This application note discusses the usage of encrypted boot with the KBOOT and experiment with the FRDM-K82 board. FRDM-K82 board

1. USB Multilink Universal    支持 Kinetis, HCS08, HC(S)12(X), S12Z, RS08, ColdFire V1/+V1, ColdFire V2-4*, Qorivva 5xxx, DSC.    PE Micro, http://www.pemicro.com/ 2. USB Multilink Universal FX    支持 Kinetis, Qorivva MPC5xxx, ColdFire +V1/ColdFire V1, ColdFire V2/3/4, HC(S)12(X), S12Z, HCS08, RS08, DSC, 683xx, HC16.    PE Micro, http://www.pemicro.com/ 3. J-Link    支持飞思卡尔ARM based Microcontroller Kinetis.    可以配合PC端的软件JFlash对目标板进行烧写。    Segger, http://www.segger.com 4. ULink2    支持飞思卡尔ARM based Microcontroller Kinetis.    Keil, http://www.keil.com/arm/ulink/ 5. USBDM    开源调试器    可以配合PC端的上位机对目标板进行烧写。    http://usbdm.sourceforge.net/    https://github.com/podonoghue    http://sourceforge.net/projects/usbdm/ 6. CMSIS-DAP    ARM公司开源调试器    仿真器相关介绍页: http://mbed.org/handbook/cmsis-dap-interface-firmware    仿真器的源码下载: https://github.com/mbedmicro/CMSIS-DAP 7. OpenSDA     P&E Microcomputer Systems

The following document explains how to load an encrypted image using the MCUBoot in the K64. Download the SDK for the K64, be sure that the MCU boot feature is selected:  https://mcuxpresso.nxp.com/en/welcome   For the example, I’m going to use gpio_led_output. To prepare the example to work with the bootloader, you would need to do the following steps: In properties / C/C++ Build / MCU settings set the start of the flash to the 0xa000, this to preserve the bootloader section:   Generate the binary for the image to load.   Write BCA Create the BCA, this field is to manage the different features of the bootloader. To generated this, the KinetisFlashTool can be used, you can find it in the following link. In this options you need to add the tag, the peripheral used to communicate and a timeout to have a time frame to call again the bootloader without need to call it from your application. Click OK and save the BCA to the image.     The bootloader can be found in the SDK examples: In the bootloader_config.h, change the BL_FEATURE_ENCRYPTION_KEY_ADDRESS for outside the code you would load, in this case, I'm going to use the 0xF000: #define BL_FEATURE_ENCRYPTION_KEY_ADDRESS 0xf000 // NOTE: this address must be 4-byte aligned. After this, load the firmware to the MCU. For the next steps we will need to generate the secure file: Generate the AES 128 key using the elftosb Command: elftosb.exe -V -d -f kinetis -n 1 – K 128 -o SBKEK.key Create the SB image from the binary, Use option -k to pass the key generated before Use option -f to define the device. Device must be kinetis to be able to use a 128 AES key Use option -c to load the bd file. (see attached) Use option -o to define the output Command: elftosb.exe -V -d -f kinetis -c (bd file path) -k (key path) -o (output path).sb2 (image path)   Now we will load the image using the blhost: Erase the memory section to load the program and reset the device  Command: blhost.exe -p COMx – flash-erase-region 0xa000 0x10000 Program AES key, same as generated in the previous step. Load it to the memory section previously defined in the  BL_FEATURE_ENCRYPTION_KEY_ADDRESS and confirm that the key was loaded correctly: Command: blhost.exe -p COMx – write-memory 0xF000 “{{key generated}}” Command: blhost.exe -p COMx –read-memory 0xF000 16   Load the SB file Command: blhost.exe -p COMx – receive-sb-file (path encrypted sb file) After a reset the application should run correctly.                

作者 Sam Wang & River Liang    说明,本文对比8位MCU的位操作在系统升级到M0+内核的MCU后所带来的影响,可以作为客户对升级MCU时,对代码及RAM上资源的评估使用. 一)简单的I/O翻转对比.对比条件:MCU为MC9S08PT与KE02,开发平台CW10.3                   1.使用PT的代码如下:          if (!PORT_PTAD_PTAD0){             PORT_PTAD_PTAD0=1;         }else{             PORT_PTAD_PTAD0=0;}       PT的代码编译后占用9个Byte。                000002D4 000004   BRSET  0,PORT_PTAD,PORT_PTAD                000002D7 1000     BSET   0,PORT_PTAD                000002D9 202E     BRA    *+48       ;abs = 0x0309                000002DB 1100     BCLR   0,PORT_PTAD       2.KE是基于ARM的M0+内核，使用的代码如下                  if(GPIOA_PDOR & 0x1)                     { GPIOA_PCOR = 0x1;}                  else                     { GPIOA_PSOR = 0X1;}       编译后结果为                00000706:   ldr r3,[pc,#24]                00000708:   ldr r2,[r3,#0]                0000070a:   movs r3,#1                0000070c:   ands r3,r2                0000070e:   beq main+0x6c (0x718)       ; 0x00000718                00000710:   ldr r3,[pc,#12]                00000712:   movs r2,#1                00000714:   str r2,[r3,#8]                00000716:   b main+0x20 (0x6cc)       ; 0x000006cc                00000718:   ldr r3,[pc,#4]                0000071a:   movs r2,#1                0000071c:   str r2,[r3,#4]       这段M0+内核的代码编译后占用24个Byte       3.KE系列是Freescale在M0+的基础上加入了位操作引擎BME，用以优化ARM内核的位操作性能，使用BME功能的代码如下                     #define PTA0_SET   (void) (*((volatile unsigned char *)(0x4C000000+(0<<21)+0xF004))) //?==0                                                       //LAS1      第0位       GPIOA_PSOR地址的A0-A19                     #define PTA0_CLR   (void)(*((volatile unsigned char *)(0x4C000000+(0<<21)+0xFF008)))                                                      //LAS1      第0位       GPIOA_PCOR地址的A0-A19                     #define PTA0                *((volatile unsigned char *)(0x50000000+(0<<23)+(0<<19)+0xF000))                                                     //UBFX           第0位     1位           GPIOA_PDOR 地址的A0-A18                if (!(PTA0))                     {PTA0_SET; }                else                     {PTA0_CLR;}           KE的BME代码编译结果如下：                    165                if (!(PTA0)){                 00000998:   ldr r3,[pc,#24]                0000099a:   ldrb r3,[r3,#0]                0000099c:   uxtb r3,r3                0000099e:   cmp r3,#0                000009a0:   bne RTC_IRQHandler+0x18 (0x9a8); 0x000009a8                  166                PTA0_SET;                                             //Using BME                000009a2:   ldr r3,[pc,#20]                000009a4:   ldrb r3,[r3,#0]                000009a6:   b RTC_IRQHandler+0x1c (0x9ac); 0x000009ac                  168                PTA0_CLR;      //Using FASTER GPIO                000009a8:   ldr r3,[pc,#16]                000009aa:   ldrb r3,[r3,#0]       代码编译后占用20个Byte         4, CW里面有设置可以优化C编译器，具体路径在Project->Proteries->C/C++ Build->Setting->GCC C Complier->Optimization           优化后共用16个Byte                  165         if (!(PTA0)){                 0000091e:   ldr r3,[pc,#20]                00000920:   ldrb r3,[r3,#0]                00000922:   cmp r3,#0                00000924:   bne RTC_IRQHandler+0x12 (0x92a); 0x0000092a                  166                         PTA0_SET;                                             //Using BME                00000926:   ldr r3,[pc,#16]                00000928:   b RTC_IRQHandler+0x12 (0x92c); 0x0000092c                  168                         PTA0_CLR;      //Using FASTER GPIO                0000092a:   ldr r3,[pc,#16]                0000092c:   ldrb r3,[r3,#0]       5, 结果     如果单纯靠M0+内核访问寄存器，KE代码的占用空间与PT的比为24：9        如果使用KE的BME功能，代码与PT的比为16:9（使用了BME）        在判断Bit时, KE使用代码与PT的比为8:3        单单设置一个Bit时KE与PT代码占比为4:2 因此在M0+等ARM核上进行位操作，其效率比8位单片机低，使用了BME功能后，可以有效提高位操作的性能。 二)典型变量的位操作. 对比条件:MCU为MC9S08PT与KE02,开发平台CW10.3                测试代码:if (xx&1){              xx&=0xFE;       }else{             xx|=1;}       1,设置XX在0 page时,其与上面的I/O翻转结果一样,代码为9个BYTES    2,在KE中，编译结果如下,设置优化前,需要52个Bytes的代码量,26个执行周期.                                                     if (xx&1){                00000a52:   ldr r3,[pc,#64]                00000a54:   ldrb r3,[r3,#0]                00000a56:   uxtb r3,r3                00000a58:   mov r2,r3                00000a5a:   movs r3,#1                00000a5c:   ands r3,r2                00000a5e:   uxtb r3,r3                00000a60:   cmp r3,#0                00000a62:   beq main+0x5a (0xa76)       ; 0x00000a76                     200                         xx&=0xFe;                00000a64:   ldr r3,[pc,#44]                00000a66:   ldrb r3,[r3,#0]                00000a68:   uxtb r3,r3                00000a6a:   movs r2,#1                00000a6c:   bics r3,r2                00000a6e:   uxtb r2,r3                00000a70:   ldr r3,[pc,#32]                00000a72:   strb r2,[r3,#0]                     203         }}                00000a74:   b main+0x28 (0xa44)       ; 0x00000a44                     202                         xx|=1;                00000a76:   ldr r3,[pc,#28]                00000a78:   ldrb r3,[r3,#0]                00000a7a:   uxtb r3,r3                00000a7c:   movs r2,#1                00000a7e:   orrs r3,r2                00000a80:   uxtb r2,r3                00000a82:   ldr r3,[pc,#16]                00000a84:   strb r2,[r3,#0]                     203         }}       3, 设置优化后,需要22/20个Bytes的代码量,11/10个执行周期.                ldr r3,[pc,#40]                     199         if (xx&1){                0000095e:   movs r2,#1                     197         xx++;                00000960:   ldrb r1,[r3,#0]                00000962:   adds r1,#1                00000964:   uxtb r1,r1                00000966:   strb r1,[r3,#0]                     199         if (xx&1){                00000968:   ldrb r1,[r3,#0]                0000096a:   tst r1,r2                0000096c:   beq main+0x34 (0x974)       ; 0x00000974                     200                         xx&=0xFe;                0000096e:   ldrb r1,[r3,#0]                00000970:   bics r1,r2                00000972:   b main+0x34 (0x978)       ; 0x00000978                     202                         xx|=1;                00000974:   ldrb r1,[r3,#0]                00000976:   orrs r1,r2                00000978:   strb r1,[r3,#0]                0000097a:   b main+0x20 (0x960)       ; 0x00000960 如果采用以空间换时间的话,其参考代码如下.                 if (xx==0){                                 xx=1;                 }else{                                 xx=0;  }       4, 如考虑中断嵌套的话,还令需要4个Byte代码。       5, 结果 KE使用代码与PT的比为至少为20:9。      在判断Bit时, KE使用代码与PT的比为8:3.       6,使用BYTE替换Bit, 编译结果,设置优化前,需要22个BYTES.                     197         if (xx==0){                000009e8:   ldr r3,[pc,#44]                000009ea:   ldrb r3,[r3,#0]                000009ec:   cmp r3,#0                000009ee:   bne main+0x38 (0x9f8)       ; 0x000009f8                     198                         xx=1;                000009f0:   ldr r3,[pc,#36]                000009f2:   movs r2,#1                000009f4:   strb r2,[r3,#0]                000009f6:   b main+0x3e (0x9fe)       ; 0x000009fe                     200                         xx=0;                000009f8:   ldr r3,[pc,#28]                000009fa:   movs r2,#0                000009fc:   strb r2,[r3,#0]    7,设置优化后,需要16/14个BYTES的代码量.                     197         xx++;                0000095c:   ldr r3,[pc,#36]                     202                         xx=1;                0000095e:   movs r1,#1                     197         xx++;                00000960:   ldrb r0,[r3,#0]                00000962:   adds r0,#1                00000964:   uxtb r0,r0                00000966:   strb r0,[r3,#0]                     199         if (xx){                00000968:   ldrb r0,[r3,#0]                0000096a:   cmp r0,#0                0000096c:   beq main+0x32 (0x972)       ; 0x00000972                     200                         xx=0;                0000096e:   strb r2,[r3,#0]                00000970:   b main+0x20 (0x960)       ; 0x00000960                     202                         xx=1;                00000972:   strb r1,[r3,#0]                00000974:   b main+0x20 (0x960)       ; 0x00000960       8, 结果 ,在RAM的空间允许的情况下,KE使用代码与PT的比为至少为12:9. 三) 8 bit变量加1       1,在PT中对8 bit变量加1,只需要4个BYTES.    24:                 XX++; 00000014 450000   LDHX   #XX       00000017 7C       INC    ,X       2,M0+的8 bit变量加1,设置优化前,需要14个BYTES                     197         xx++;                00000a44:   ldr r3,[pc,#48]                00000a46:   ldrb r3,[r3,#0]                00000a48:   uxtb r3,r3                00000a4a:   adds r3,#1                00000a4c:   uxtb r2,r3                00000a4e:   ldr r3,[pc,#40]                00000a50:   strb r2,[r3,#0]       3,而如果使用优化设置,那么要12个BYTES                     197         xx++;                0000095c:   ldr r3,[pc,#36]                     202                         xx=1;                0000095e:   movs r1,#1                     197         xx++;                00000960:   ldrb r0,[r3,#0]                00000962:   adds r0,#1                00000964:   uxtb r0,r0                00000966:   strb r0,[r3,#0]       4, 结果 , 在8 bit变量加1时,KE使用代码与PT的比为至少为12:4，但这是32bitARM内核操作8bit变量都普遍存在效率变低的现象。 四) 16位+8位加法       1, 8 bit 编译结果,需要8个BYTES.                0000008 320000    LDHX   xx                0000000B AF01     AIX    #1                0000000D 960000   STHX   xx       2, M0+ 编译结果,设置优化前,需要10个BYTES.                00000a44:   ldr r3,[pc,#44]                00000a46:   ldr r3,[r3,#0]                00000a48:   adds r2,r3,#1                00000a4a:   ldr r3,[pc,#40]                00000a4c:   str r2,[r3,#0].       3, M0+ 编译结果,设置优化后,需要8个BYTES.                0000095c:   ldr r3,[pc,#20]                0000095c:   ldr r3,[pc,#20]                0000095e:   ldr r2,[r3,#0]                00000960:   adds r2,#1                00000962:   str r2,[r3,#0]       4,结果,M0+在16位加法时能够达到8bit单片机的效率，结果相同. 五)结论     因此用户在移植PT(或其它8 bit MCU)代码到KE02时,要选型时需要充分考虑客户原先代码具体运算情况,理论上存在使用KE后代码变大的情况.   但是使用KE等32bitM0+内核时可以在16bit或以上的乘、加运算时获得更好的效率，占用更小的代码空间和运算时间。   另外KE对GPIO的控制寄存器比PT多了一些功能,可以一次操作多个I/O,是不错的功能.

最近在论坛、QQ群里好多人都在讨论低功耗设计，想到之前遇到的一个客户也有这方面的一个要求，顺着他的想法做了一个在低功耗模式下使用ADC的例子。客户要做的是一个恒温控制，在设定温度范围内让MCU进入休眠状态，只有在超过温度范围后才唤醒MCU进行温度调节。话不多说，让我们开始例程介绍。 运行平台： FRDM-25Z IARv7.3 在KL25_SC代码包中platinum工程上修改 Low Power Mode 简介 飞思卡尔Kinetis系列MCU基于90纳米TFS技术，使得MCU在低功耗模式下，拥有良好的性能和功耗表现，KL系列更是被评为业内最低功耗的MCU。KL25Z 功耗模式总共有 11 种，分别是：Run、VLPR、Wait、VLPW、Stop、VLPS、LLS、VLLS3、VLLS2、VLLS1、VLLS0，能够满足客户对MCU各种低功耗的配置要求，在深度睡眠模式下智能外设能够处理相应数据而不需要唤醒内核。    图1 在本设计中需要在低功耗模式下监控温度，热电偶的电信号需要用到ADC进行采样，查手册可知ADC能够运行的最低功耗模式是VLPS模式。VLPS模式下大部分外设仍然可以使用，但需要注意的是在VLPS模式下总线时钟是禁止的，因此在进入VLPS模式前应该将ADC的时钟设为ADACK，不然它进入VLPS模式后就嗝屁了。VLPS模式下只能采用硬件触发来触发ADC采样，本例采用的是LPMR定时器来触发ADC采样。VLPS模式下可以采用中断唤醒方式，本例采用ADC中断唤醒。当然也可以采用异步DMA通道来搬运ADC转换结果，搬运完成后自动回到VLPS模式下，感兴趣的话也可以试一下这种方式哈。   图2 代码介绍：    int main (void) {      #ifdef CMSIS  // If we are conforming to CMSIS, we need to call start here     start(); #endif          lptmr_init(1000,LPTMR_USE_LPOCLK);   //trigger ADC per 1000ms     // 初始化代码中设置LPO作为lptmr的时钟源，保证lptmr在VLPS下能够正常工作；     init_ADC16();                                                                                          //初始化ADC，设置ADC硬件触发源为lptmr，使能ADC范围比较模式，即当转换结果小于C1V，大于C2V时保存结果；     enable_irq(ADC0_irq_no);                                                                      //在进入低功耗模式前使能ADC中断。     printf("Enter VLPS mode...\r\n");     clockMonitor(OFF);     enter_vlps();     while(1)   {                  if(flag_wakeup == 1)           {             flag_wakeup = 0;             ADC0_SC2 &= ~ADC_SC2_ACFE_MASK;              disable_irq(ADC0_irq_no);                                                              //退出后，为调节温度需关闭范围比较模式，同时关闭ADC中断，采用查询模式；             printf("Wake up from VLPS..\n");             printf("adcresult = %d\n",adcresult);           }                              if((ADC0_SC1(0) & ADC_SC1_COCO_MASK) == ADC_SC1_COCO_MASK)     //查询转换结果           {             adcresult = ADC0_R(0);             printf("wake up adcresult = %d\n",adcresult);             if((adcresult>= 4000) && (adcresult<= 5000))                                   //当调节到ADC结果再次进入调节范围时，准备进入低功耗模式；             {               ADC0_SC2 |= ADC_SC2_ACFE_MASK;                                         //为实现监控，重新使能范围比较模式和ADC中断。               enable_irq(ADC0_irq_no);               printf("Enter VLPS mode...\n");               clockMonitor(OFF);               enter_vlps();             }           }              } }        实验结果：      设置比较值为4000~5000，打印结果如下： 图3       好了，就这些了，第一次写技术文章，很浅显的东西说了一大堆，比较乱，望批评指正哈。       附件为参考代码。

Common： 1. 如何在IAR、Keil和Codewarrior中禁止掉Kinetis的NMI脚 2. 使用Codewarrior、IAR和Keil三大IDE配置生成bin文件 3. Codewarrior、IAR和Keil三大IDE局部优化指令 Kinetis Design Studio 1. 飞思卡尔免费开发环境KDS调试时显示外设寄存器内容​ CodeWarrior: 1. Codewarrior中如何查看Flash和RAM占用Size大小， include路径如何配置？ 2. Codewarrior10.5低功耗模式唤醒后保持调试功能 3. 浅谈Codewarrior局部优化技巧 4. 在Codewarrior10.x调试模式下导出内存数据到s19文件 5. CodeWarrior10.x中英文系统界面切换 6. CodeWarrior10.x新建Kinetis工程方法 7. Codewarrior10.x下使用ewl_noio库以节省代码空间 8. Codewarrior10.x下生成的image文件后缀都是.hex 9.代码重定位-CodeWarrior/KDS-kineits L 系列 IAR: 1. 利用IAR Timeline工具测试delay函数执行时间 2. 使用老版本IAR支持新器件 3. IAR环境下Flash loader工作原理 4. IAR环境下Flash调试和RAM调试的区别 5. IAR环境下更改ARM大小端存储模式 6. 简单移植Kinetis IAR开发框架模板的方法 7. Kinetis图形化显示stack堆栈使用情况 8. IAR使用小技巧（常用快捷键，LiveWatch配置方法，修改调试模式入口地址） 9. 实现IAR下S19、Bin、Hex文件格式转换 10. IAR生成和调用Kinetis函数库 11. 批处理查找添加IAR工程头文件 12. 通过IAR MAP文件查看目标文件内存分配 13. 解析IAR的ILINK链接器icf配置文件 14. 重定向printf输出到IAR虚拟终端 15. 解决双击eww文件无法同时打开多个IAR工程的问题 16. IAR下使用noinit段的方法和指定地址的变量分配 Keil: 1. Keil编译器ARMCC中添加对GCC扩展格式的支持 2. 关于Keil无法正确下载程序问题的总结

There with phase shifting when using two different FTM modules to output PWM signals. Although the two FTM modules using the same clock source (bus clock), there still exists the phase shifting status. Please check attached video about phase shifting. FTM Global Time Base(GTB) introduction The global time base (GTB) is a FTM function that allows the synchronization of multiple FTM modules on a chip. The following figure shows an example of the GTB feature used to synchronize two FTM modules. In this case, the FTM A and B channels can behave as if just one FTM module was used, that is, a global time base. K65’s FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: The code description:    // Configure ftm params with frequency 2MHz for CLK        ftm_pwm_param_t ftmParamCLK = {             .mode                   = kFtmEdgeAlignedPWM,   //PWM mode             .edgeMode               = kFtmLowTrue,           //PWM Low-true pulses (clear Output on match-on)             .uFrequencyHZ           = 200000u,         //2MHz clock frequency             .uDutyCyclePercent      = 50,                //Duty cycle 50%             .uFirstEdgeDelayPercent = 0,                        };    //using FTM0 & FTM3 GTB feature    FTM_HAL_SetClockSource (FTM0, kClock_source_FTM_None);   //disable FTM0 clock source    FTM_HAL_SetClockSource (FTM3, kClock_source_FTM_None);   //disable FTM3 clock source      FTM_HAL_SetGlobalTimeBaseCmd(FTM0, true);   //enable FTM0 GTBEEN    FTM_HAL_SetBdmMode(FTM0, kFtmBdmMode_11);   //enable FTM0 BDMMODE    FTM_HAL_SetGlobalTimeBaseCmd(FTM3, true);   //enable FTM3 GTBEEN    FTM_HAL_SetBdmMode(FTM3, kFtmBdmMode_11);   //enable FTM3 BDMMODE        FTM_HAL_SetClockSource (FTM0, kClock_source_FTM_SystemClk);   //disable FTM0 clock source    FTM_HAL_SetClockSource (FTM3, kClock_source_FTM_SystemClk);   //disable FTM3 clock source      FTM_HAL_SetCounter(FTM0, 0U);        //clear TFM0 counter value to 0    FTM_HAL_SetCounter(FTM3, 0U);        //clear FTM3 counter value to 0      FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM0, true);      //enale FTM0 GTBEOUT Please check attached video about after using GTB feature, the FTM0_CH4 and FTM3_CH1 PWM output signals. How to output two PWM output signals at one FTM module with KSDK? The two PWM output signal will provides the same clock frequency with different duty cycle. The two PWM output signal need use the same PWM mode. Please check below code to enable K65’s FTM0 module output two PWM signals. // Configure ftm params with frequency 2MHz for CLK        ftm_pwm_param_t ftmParamCLK = {             .mode                   = kFtmEdgeAlignedPWM,   //PWM mode             .edgeMode               = kFtmLowTrue,           //PWM Low-true pulses (clear Output on match-on)             .uFrequencyHZ           = 200000u,         //2MHz clock frequency             .uDutyCyclePercent      = 50,                //Duty cycle 50%             .uFirstEdgeDelayPercent = 0,                        }; // Configure ftm params with frequency 2MHz for CLK                ftm_pwm_param_t ftmParamSH =         {              .mode                   = kFtmEdgeAlignedPWM,   //PWM mode              .edgeMode               = kFtmLowTrue,   //PWM Low-true pulses (clear Output on match-on)              .uFrequencyHZ           = 200000u,        //2MHz clock frequency              .uDutyCyclePercent      = 75,     //Duty cycle 75%              .uFirstEdgeDelayPercent = 0,         };     // Initialize FTM module,     // configure for software trigger.     memset(&ftmInfo, 0, sizeof(ftmInfo));     ftmInfo.syncMethod = kFtmUseSoftwareTrig;  //Using software trigger PWM synchronization     FTM_DRV_Init(BOARD_FTM_INSTANCE, &ftmInfo);  //FTM0 initialization     FTM_DRV_SetClock(BOARD_FTM_INSTANCE, kClock_source_FTM_SystemClk, kFtmDividedBy1); //Enable FTM0 counter clock     FTM_DRV_PwmStart(BOARD_FTM_INSTANCE, &ftmParamCLK, BOARD_FTM_CHANNEL); //Enable PWM output at FTM0_CH4     FTM_HAL_SetClockSource(FTM0, kClock_source_FTM_None); //Disable FTM0 counter clock     FTM_DRV_PwmStart(BOARD_FTM_INSTANCE, &ftmParamSH, BOARD_FTM_CHANNEL5);   //Enable PWM output at FTM0_CH5 The tested code also be attached, please using it with KSDK V1.2 software. Wish it helps.