*******************************************************************************  The purpose of this demo application is to present a usage of the  FlexCAN IP Driver for the S32K3xx MCU.  The example uses FLEXCAN-0 for transmit & receive Tusing following Message buffer :-- #define RX_MB_IDX 1U #define TX_MB_IDX 0U. BAUDRATE : 500 KBPS  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

*******************************************************************************  The purpose of this demo application is to present a usage of the Siul2_Icu IP Driver for the S32K3xx MCU.  The example uses EIRQ-13 on PTB23 for interrupt..  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************        

*******************************************************************************  The purpose of this demo application is to present a usage of the  LPSPI IP Driver for the S32K3xx MCU.  The example uses LPSPI2 for transmit & receive Twelve bytes using the DMA. MOSI MISO connected on Hardware in loopback.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

Customer may need more high performance via S32K3xx. How to optimization user's code?  As following have some suggestions:  1. Most of user code allocate to P-Flash and enable I-Cache 2. Allocate system stack to D-TCM and enable D-Cache 3. Execute code frequently allocate to I-TCM. E.g., ISRs etc. 4. OS' task stack allocate to D-TCM 5. vector table allocate to D-TCM Please note: 1. Due to enable D-Cache, other masters(E.g., DMA, HSE, another APP cores) access theses area of cacheable will be impact. So, theses area need to allocate to non-cacheable area. 2. If another master(E.g., DMA, HSE and another APP cores) access the D-TCM need to over back door. E.g., core1/DMA/HSE access core0' DTCM needed to over backdoor.  Information: S32K3' Coremark in RM, theses Coremark' value are from ARM. If used IAR/GHS etc and set compiler flag, then the Coremark value is very closely with RM. If used GCC, then the Coremark value will less than RM. BR Tomlin    

*************************************************************************************************************** Detailed Description: Example shows implementation of Analog Comparator ‘45.7.5 Windowed mode (#s 5A & 5B)’ of S32K1XXRM using S32 SDK API. The Comparator is configured to compare analog input 0(AIN0) with half the reference voltage generated with the internal DAC. PDB is used to generate pulse output which is used as sampling windows of CMP block via TRGMUX. PDB period is 5ms, the first 2.5ms WINDOW=1 and the next 2.5ms WINDOW=0. Pdb0PulseOut not only be TRGMUX to Cmp0Sample but also to TrgmuxOut0, so that we are able to observe WINDOW at TRGMUX_OUT0(PTA1) pin. Based on the input from CMP0_IN0 (1kHz external triangle wave) the LEDs light by the following rules: 1) Vin < DAC voltage : RED on, GREEN off 2) Vin > DAC voltage : RED off, GREEN on 3) Unknown state : RED on, GREEN on EVB connection: Signal Function pin S32K144EVB-Q100 WINDOW TRGMUX_OUT0 PTA1 J5.5 2.5ms WINDOW=1 and 2.5ms WINDOW=0 Plus input CMP0_IN0 PTA0 J5.7 Need to connect external 1khz triangle wave COUTA CMP0_OUT PTE3 J1.16 square wave PTC1 PTC1 J5.13 If there is no external triangle wave, a square wave(PTC1) is generated and output to CMP0 (PTA1) * * ------------------------------------------------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144UAVLL 0N47T * Target: Debug_FLASH * Compiler: S32DS3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: PEMicro OpenSDA * ------------------------------------------------------------------------------------------------------------------------ Revision History: Ver   Date              Author            Description of Changes 1.0   Nov-9-2023   Robin Shen    Initial version, based on cmp_dac_s32k144 and pdb_periodic_interrupt_s32k144 ***************************************************************************************************************

******************************************************************************** * Detailed Description: * The example adds DTCM_1 backdoor access for CM7_0. * int_dtcm_1_bd memory region and section dtcm1_bd_data added to the linker file. * DTCM1 ECC initialized in startup_cm7.s * MPU on DTMC1 enabled in system.c * Global variables decleared with __attribute__ ((section(".dtcm1_bd_data"))) in main.c * ------------------------------------------------------------------------------ * Test HW: S32K314EVB-Q172 * MCU: S32K314 * Debugger: S32DS_ARM_3.4 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * The purpose of this example is show how to keep data in SRAM memory over SW * reset. SW reset is triggered by pressing the SW3 button on the S32K118EVB. * Reset is delayed for 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN is * cleared allowing to retain SRAM data during the reset. After SW reset, * SRAMU_RETEN is set to allow accesses to SRAM. * File startup_S32K116.S in modified to skip ECC RAM initialization for SW reset * source. To check whether stored data stayed unmodified in the SRAM, specified * address is read and the LED lights up. * ------------------------------------------------------------------------------ * Test HW: S32K118EVB-Q064 * MCU: S32K118 LAMLH 0N97V QTZE1802B * Fsys: fsys = 48MHz * Debugger: Lauterbach Trace32 * Target: Debug * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.0 May-17-2023 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Example is based on Siul2_Port_Ip_Example_S32K344 and its purpose it to show * how to integrate ITCM and DTCM memories to the project. * * Modification has been done in following files: * - main.c * - startup_cm7.s * - linker_flash_s32k344.ld * * In the main function, function is placed to ITCM memory and executed. Also * data field in placed to DCTM and accessed. * ******************************************************************************** * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: PlatformSDK_S32K3_3_0_0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 7 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 3 channels, ADC1 4 channels. PDBs are set to back-to-back mode to perform chain conversion as shown in RM's Figure 46-3. PDB back-to-back chain forming PDB0-PDB1 ring. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 ch5 External input channel 28 is selected, as it is connected to potentiometer on the EVB. PDB0 is triggered by LPIT ch0 at 500ms rate. Two DMA channels are configured to read result registers from both ADCs. * ------------------------------------------------------------------------------ * Test HW: S32K148EVB-Q144 * MCU: FS32K144UAVLQ 0N20V * Target: Debug_FLASH * EVB connection: UART terminal 115200, 8N1 * Compiler: S32DS.ARM.3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: S32DS ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 Feb-21-2023 Petr Stancik Initial version, based on adc_hwtrigger_s32k148 *******************************************************************************/

 

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 7 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 3 channels, ADC1 4 channels. PDBs are set to back-to-back mode to perform chain conversion as shown in RM's Figure 46-3. PDB back-to-back chain forming PDB0-PDB1 ring. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 ch5 External input channel 28 is selected, as it is connected to potentiometer on the EVB. PDB0 is triggered by LPIT ch0 at 500ms rate. * ------------------------------------------------------------------------------ * Test HW: S32K148EVB-Q144 * MCU: FS32K144UAVLQ 0N20V * Target: Debug_FLASH * EVB connection: UART terminal 115200, 8N1 * Compiler: S32DS.ARM.3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: S32DS ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 Jan-26-2023 Petr Stancik Initial version, based on adc_hwtrigger_s32k148 *******************************************************************************/

Question As we know, the TPPSDK supports S32K144 MCU and various Kinetis MCUs to initialize GD3000 in NXP MC solutions. Because of the release of S32K3 and related SW RTD, it’s necessary to expand the capability of TPPSDK to support S32K3 MC based RTD LLD driver or MCAL driver. Unfortunately, the AA team will not maintain the TPPSDK anymore.  How could we configure the GD3000 chip for S32K3 platform?   Answer I took some time to finish this work. Here I'd like to share you the The Expanded TPPSDK Based on S32K3 RTD that is suitable for S32K3 MC application. You can find the Application Note, the source code of new TPPSDK (GD3000 driver), two examples in the attachment. I hope these materials can help you get start with the expanded TPPSDK on S32K3.

           The hardware of this routine is based on S32K142EVB, the IDE is S32_Design_Studio for ARM 2018.R1, SDK version is S32K1xx_RTM_3.0.0, PTB12 is used to simulate Hall pulse output,PTC12 and PTC13 are buttons to change the flip frequency of PTB12 port, and PTB13 is used as the input capture port. When using the demo program in this article, you need to connect PTB12 and PTB13 ports.   Here we assume that we are using a brushed DC motor!   1.The Hall sensor       The Hall sensor is a magnetic induction sensor. The magnetic ring and the Hall element form an induction combination. The magnetic ring rotates with the rotor. The Hall induction magnetic ring rotates with the rotor. , 3-pole pairs, 4-pole pairs, etc., each pair of poles is divided into two levels of N.S. A pair of magnetic poles outputs one pulse signal, and multiple magnetic poles output multiple pulse signals. The number of magnetic pole stages determines the number of pulse signals. , the higher the accuracy.   Hall sensor 2.The relationship between the motor magnetic ring series and the output Hall waveform 5 pole pairs 3.Determination of motor rotation direction         The direction of the motor is judged by the phase difference of the two Hall signals. As shown in the figure below, the phase of Sensor A is ahead of Sensor B, so it can be considered that the current rotation direction of the motor is clockwise.   4.Calculation of motor speed         The speed of the motor can be calculated by the pulse width of the pulse, and the number of revolutions of the motor can be calculated by the number of pulses. Assuming that the Hall magnetic ring of the motor has 5 pairs of poles, it means that there are five pulses in one revolution of the motor, and the speed of the motor = 60 / (t1 * 5) rev/min. The number of pulses can be obtained by the edge capture function of the FTM. Motor speed and stroke         Assuming that the clock of the FTM is 2MHz, then it takes 1/2000000 seconds for the counter to add 1. Since the unit of the motor speed is rpm, the calculation formula of the motor speed is : -> Motor Speed = 60 / (5 * a* (1 / 2000000))         In this formula, '5' is the number of pole pairs of the magnetic ring, and 'a' is the difference of the counter corresponding to the falling edge of two consecutive pules.         Let’s do a test, the square wave in the below figure is the outputs of PTB12, and the output pulse period is 32.1ms. Then the time required for the motor to rotate once should be:32.1ms *5 = 160.5ms, then the speed of the motor should be: 60 * 1000 / 160.5 = 373.83rpm.   PTB2 output square wave          The below picture is directly obtained by the debugger. It can be seen that the speed of the motor at this time is 373, which is not much different from the value measured by the oscilloscope, which is 373.83. This is because I did not use the floating-point calculation result in the program. In summary, we use the input capture function of the FTM module completes the calculation of the motor speed.   debuger monitor results 5.How to calculate the direction of rotation of the motor         Above we calculated the speed of the motor, but did not make judgement on the direction of the rotation of the motor. As mentioned above, the rotation direction of the motor is judged by the phase difference of the two Hall pulse waveforms. Usually, we think of using the timestamp to judge the current state of the phase, so we will enable the two input captures, and then calculate the two Halls timestamp of the falling edge of the pulse.         In fact, there is a simpler method, it only needs to read the high and low state of the other Hall pulse level when the falling edge of one hall pulse is interrupted. In short, we only need to enable one input capture, and the other to be used as a GPIO port.

Symptoms Recently found the compatibility issue is a troublesome problem especially when we are supporting different version of RTD. Remove/install the RTD SDK and plug, but it is not a perfect way because reinstall the RTD would cause a lot of time, sometimes it is unreliable. Diagnosis After investigated the mechanism of CT and MEX file, and found a work around to let the old project can be run in new version of RTD basis. Solution Already tested it with several reference code and examples of RTD, it can work. Attached is the document.

 

Symptoms   Diagnosis   Solution  

Symptoms   Diagnosis   Solution  

This article is written in Chinese. It is mainly for the disty and mass market customers in local China. It is useful for the the developers who is newly in touch with S32K1, and will help them install several software of S32K1, otherwise it may waste a lot of time.     S32DS中快速搭建S32K1的开发环境 一．背景 我最近换装了新电脑，需要重新安装S32DS，发现存在很多问题。尤其是对比之前的安装过程，发现官网的很多链接已经失效，甚至有一定的迷惑性。 最新的S32K1安装包比较隐蔽，而且安装存在前后依赖，对于刚接触NXP S32系列的新手非常不友好，所以写这篇文档总结一下典型的问题和解决方法。 同时也希望提供一个check的思路和步骤，在后续新版本发布时，升级IDE的时候更方便找到合适的安装包。 二．S32DS中各个包依赖关系解析 在S32DS中，每一个系列的MCU，总共需要安装两个插件包，一个是基础依赖包，一个是SDK（也叫RTD，同一个意思）。 1．基础依赖包 这个包对应S32DS版本，比如当前的3.4.3，官网可以下载离线版，一般大小在3GB左右，会更新S32DS中的很多组件，如下图1所示：            图1 尤其需要关注图1中红框的内容，没有这个development package的话，是无法进行对应MCU的debug。 图1中安装的包，对应到S32DS中安装的内容如图2所示：            图2 2．RTD安装包（与SDK同义） 这个包对应于RTD版本，也会标识AutoSAR的版本，比如最新的2.0.0，AutoSar 4.4，如图3所示：           图3 基础依赖包与RTD安装包存在前后依赖关系，如果不安装基础依赖包直接安装RTD，在安装时会报错。另外，我们下载的RTD包，即使写明是K3，里面也会包含K1的RTD，这点需要注意。如果此时还没有装K1的development package，就会出错。 三．S32K1开发环境搭建 官网对于S32K3的软件划分为standard software和reference software，其中S32DS和基础依赖包在standard software中，可以很方便的找到。 但S32K1的官网却仅有一个reference software，页面也只能找到几个RTD（或SDK）链接：                                                                             图4 这里面所有的链接都不是我们需要的，全是RTD。问题就出在这里，K1的网页中没有K1的基础依赖包！而前面讲过，缺基础依赖包会导致RTD也无法安装。经过我研究，K1的基础依赖包隐藏的非常深，可以通过两个方法找到： 从S32K1的reference software进去，然后重新点击product list，如下图5所              图5         进入如下页面，如图6所示，这里最能看出来，针对K1的界面很不友好，需要点最底下的NXP Software.              图6 在NXP.com官网首页搜索栏直接搜S32DS，找到S32 Design Studio for S32 Platform（注意不要选成for ARM或或者for PowerPC），从S32DS的主界面进入，然后一直下拉，找到S32DS service pack 1，这个才是K1的，如图7所示：                 图7 这个链接更加隐蔽，要在40多个选项里挨个找。   经过上面两个方法，都可以进入图8所示的界面，然后再按图8所示操作：              图8   这回终于到了最终可以下载S32K1基础依赖包的地方，如图9所示。我们需要重点关注一下命名，SW32开头的，会包含所有S32的development package，包括K1，K3，G；SW32K1开头的，仅有K1，同理如果你在K3的界面中，可以看到SW32K3开头的。            图9 下载最新版本的S32K1基础依赖包，然后再安装RTD，大功告成。

****************************************************************************************************  Detailed Description:  The current RTD RTM 2.0.0 does not support overflow notification  if EMIOS ICU is used in the Edge Detect mode.  Workaround is to use another channel in ECU mode  clocked by the same counter bus as the ICU channel.  Emios_0 input clock: 48MHz CORE_CLK  MCL EMIOS_0_Ch_23 (BUS_A)  Global clock devider: 48  MCB prescaler: 1  MCB clock: 1MHz  MCB tick: 1us  MCB period: 65_535 ticks  Both OCU (Emios_0_Ch0) and ICU (Emios_0_ch3) use the same BUS_A counter clock.  GPIO generated PWM period: ~0.5s  That's 500_000 ticks  ICU routed to PTB0  GPIO PWM to PTB1  -----------------------------------------------------------------------------------------------  Test HW: S32K3X4EVB-Q172  MCU: S32K344  Debugger: S32DS 3.4, PEMicro Multilink rev.C  Target: internal_FLASH ****************************************************************************************************

************************************************************************************************************************** * Detailed Description: * * Connect PTC24 (PWM) to PTC25 (IC) * * PWM signal generated by EMIOS_1_ch0 (in OPWFMB mode) is measured by EMIOS_1_ch_1 (IPWM mode). * * EMIOS_1 global global clock (core clock = 48MHz) prescaled in EMIOS_Mcl driver (/48) = 1MHz. * * BUS_A generated by EMIOS_1_ch_23 * Tick = 10us (1MHz global clock prescaled by 10 = 100kHz) * * PWM (OPWFMB), EMIOS_1_ch_0, PTC24 * Tick = 10us (1MHz global clock prescaled by 10 = 100kHz) * * IC (IPWM), EMIOS_1_ch_1, PTC25 * Clocked by BUS_A * Tick = 10us * * ------------------------------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Debugger: S32DS 3.4, PEMicro Multilink rev.C * Target: internal_FLASH **************************************************************************************************************************