Customer may need more high performance via S32K3xx. How to optimization user's code?
As following have some suggestions:
1. Most of user code allocate to P-Flash and enable I-Cache
2. Allocate system stack to D-TCM and enable D-Cache
3. Execute code frequently allocate to I-TCM. E.g., ISRs etc.
4. OS' task stack allocate to D-TCM
5. vector table allocate to D-TCM
Please note:
1. Due to enable D-Cache, other masters(E.g., DMA, HSE, another APP cores) access theses area of cacheable will be impact. So, theses area need to allocate to non-cacheable area.
2. If another master(E.g., DMA, HSE and another APP cores) access the D-TCM need to over back door. E.g., core1/DMA/HSE access core0' DTCM needed to over backdoor.
Information:
S32K3' Coremark in RM, theses Coremark' value are from ARM. If used IAR/GHS etc and set compiler flag, then the Coremark value is very closely with RM. If used GCC, then the Coremark value will less than RM.
BR
Tomlin
