*******************************************************************************  The purpose of this demo application is to present a usage of the  FlexCAN IP Driver for the S32K3xx MCU.  The example uses FLEXCAN-0 for transmit & receive Tusing following Message buffer :-- #define RX_MB_IDX 1U #define TX_MB_IDX 0U. BAUDRATE : 500 KBPS  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

*******************************************************************************  The purpose of this demo application is to present a usage of the Siul2_Icu IP Driver for the S32K3xx MCU.  The example uses EIRQ-13 on PTB23 for interrupt..  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************        

*******************************************************************************  The purpose of this demo application is to present a usage of the  LPSPI IP Driver for the S32K3xx MCU.  The example uses LPSPI2 for transmit & receive Twelve bytes using the DMA. MOSI MISO connected on Hardware in loopback.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

*******************************************************************************  The purpose of this demo application is to present a usage of the  UART IP Driver for the S32K3xx MCU.  The example uses LPUART6 for transmit & receive five bytes using the DMA.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************    

*******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR and BCTU IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger BCTU conversion list to  perform  conversions on ADC1.  ADC channels  are selected to be converted on  ADC-1:  ADC1: P0, p1, p2, p3, p4, p5, p6, S10  Converted results from  BCTU_ADC_DATA_REG are moved by DMA into result array.  ADC channel S10 is connected to board's potentiometer.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Set PIT Freeze Enable :--- All channels are for ADC-1 , in BCTU list :--     "NEW DATA DMA enable mask" :-- controls These bit field in MCR register     "ADC target mask" :-- It controls "ADC_SEL " bit field in "Trigger Configuration (TRGCFG_0 - TRGCFG_71)" for single conversions you can enable only one instance so the possible values for target mask: 1 (0b001) ADC0 2 (0b010) ADC1 3 (0b100) ADC2| for list of conversions we can enable also parallel con version for example 3 (0b011) parallel conversion of ADC0 and ADC1 The trigger is configured as a list of parallel conversions ADC0, ADC1 in “Adc Target Mask”. List of ADC channels is defined in “BCTU List Items” while order is given by the “Adc Target Mask”: BctuListItems_0 is ADC0, BctuListItems_1 is ADC1 etc.      

Customer may need more high performance via S32K3xx. How to optimization user's code?  As following have some suggestions:  1. Most of user code allocate to P-Flash and enable I-Cache 2. Allocate system stack to D-TCM and enable D-Cache 3. Execute code frequently allocate to I-TCM. E.g., ISRs etc. 4. OS' task stack allocate to D-TCM 5. vector table allocate to D-TCM Please note: 1. Due to enable D-Cache, other masters(E.g., DMA, HSE, another APP cores) access theses area of cacheable will be impact. So, theses area need to allocate to non-cacheable area. 2. If another master(E.g., DMA, HSE and another APP cores) access the D-TCM need to over back door. E.g., core1/DMA/HSE access core0' DTCM needed to over backdoor.  Information: S32K3' Coremark in RM, theses Coremark' value are from ARM. If used IAR/GHS etc and set compiler flag, then the Coremark value is very closely with RM. If used GCC, then the Coremark value will less than RM. BR Tomlin    

*******************************************************************************  The purpose of this demo application is to present a usage of   configure TRGMUX to select triggers for staring Normal/Injected chain conversion. Select PIT0_Ch0 as the hardware trigger source of ADC1_Ch34 & Ch48 via TRGMUX and two LEDs to show the trigger Sequence. ADC1_Ch34 is connected to board's potentiometer,Ch38 is bandgap channel.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q257 * MCU: S32K344 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: OpenSDA * Target: internal_FLASH ********************************************************************************

*************************************************************************************************************** Detailed Description: Example shows implementation of Analog Comparator ‘45.7.5 Windowed mode (#s 5A & 5B)’ of S32K1XXRM using S32 SDK API. The Comparator is configured to compare analog input 0(AIN0) with half the reference voltage generated with the internal DAC. PDB is used to generate pulse output which is used as sampling windows of CMP block via TRGMUX. PDB period is 5ms, the first 2.5ms WINDOW=1 and the next 2.5ms WINDOW=0. Pdb0PulseOut not only be TRGMUX to Cmp0Sample but also to TrgmuxOut0, so that we are able to observe WINDOW at TRGMUX_OUT0(PTA1) pin. Based on the input from CMP0_IN0 (1kHz external triangle wave) the LEDs light by the following rules: 1) Vin < DAC voltage : RED on, GREEN off 2) Vin > DAC voltage : RED off, GREEN on 3) Unknown state : RED on, GREEN on EVB connection: Signal Function pin S32K144EVB-Q100 WINDOW TRGMUX_OUT0 PTA1 J5.5 2.5ms WINDOW=1 and 2.5ms WINDOW=0 Plus input CMP0_IN0 PTA0 J5.7 Need to connect external 1khz triangle wave COUTA CMP0_OUT PTE3 J1.16 square wave PTC1 PTC1 J5.13 If there is no external triangle wave, a square wave(PTC1) is generated and output to CMP0 (PTA1) * * ------------------------------------------------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144UAVLL 0N47T * Target: Debug_FLASH * Compiler: S32DS3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: PEMicro OpenSDA * ------------------------------------------------------------------------------------------------------------------------ Revision History: Ver   Date              Author            Description of Changes 1.0   Nov-9-2023   Robin Shen    Initial version, based on cmp_dac_s32k144 and pdb_periodic_interrupt_s32k144 ***************************************************************************************************************

*******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR and BCTU IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger BCTU conversion list to  perform parallel conversions on ADC0/ADC1. Three ADC channels  are selected to be converted on each ADC:  ADC0: S8 , P0, S8  ADC1: S10, S13, S17  Converted results from BCTU FIFO are moved by DMA into result array.  ADC channel S10 is connected to board's potentiometer, and converted value is  used to dim board's LED.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: Lauterbach * Target: internal_FLASH ********************************************************************************

Hi all,   Many customers complained about the K3 FlexIO I2S can not support continuous transferring because there is a gap time between 2 times of invoking SendData. This gap time will break the audio continuity and bring jitters. It is gapped by the transfer API closing and re-entry time cost.   To avoid this gap and implement a real continuous transferring, we made some changes with eDMA configurations. Finally, it works!   Besides, we also enabled eDMA half-complete interrupt to support double-buffer (ping-pong buffer) operation for user's further development.   Attachments are the example projects and corresponding introduction slides, please kindly check if you are interested in. Any problem, just let me know. Welcome your comments here.   Best Regards, Shuailin Li NXP GPIS, AE

******************************************************************************** * Detailed Description: * The purpose of this example is show how to keep data in SRAM memory over SW * reset. SW reset is triggered by pressing the SW3 button on the S32K118EVB. * Reset is delayed for 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN is * cleared allowing to retain SRAM data during the reset. After SW reset, * SRAMU_RETEN is set to allow accesses to SRAM. * File startup_S32K116.S in modified to skip ECC RAM initialization for SW reset * source. To check whether stored data stayed unmodified in the SRAM, specified * address is read and the LED lights up. * ------------------------------------------------------------------------------ * Test HW: S32K118EVB-Q064 * MCU: S32K118 LAMLH 0N97V QTZE1802B * Fsys: fsys = 48MHz * Debugger: Lauterbach Trace32 * Target: Debug * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.0 May-17-2023 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Example is based on Siul2_Port_Ip_Example_S32K344 and its purpose it to show * how to integrate ITCM and DTCM memories to the project. * * Modification has been done in following files: * - main.c * - startup_cm7.s * - linker_flash_s32k344.ld * * In the main function, function is placed to ITCM memory and executed. Also * data field in placed to DCTM and accessed. * ******************************************************************************** * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: PlatformSDK_S32K3_3_0_0 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 7 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 3 channels, ADC1 4 channels. PDBs are set to back-to-back mode to perform chain conversion as shown in RM's Figure 46-3. PDB back-to-back chain forming PDB0-PDB1 ring. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 ch5 External input channel 28 is selected, as it is connected to potentiometer on the EVB. PDB0 is triggered by LPIT ch0 at 500ms rate. Two DMA channels are configured to read result registers from both ADCs. * ------------------------------------------------------------------------------ * Test HW: S32K148EVB-Q144 * MCU: FS32K144UAVLQ 0N20V * Target: Debug_FLASH * EVB connection: UART terminal 115200, 8N1 * Compiler: S32DS.ARM.3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: S32DS ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 Feb-21-2023 Petr Stancik Initial version, based on adc_hwtrigger_s32k148 *******************************************************************************/

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 7 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 3 channels, ADC1 4 channels. PDBs are set to back-to-back mode to perform chain conversion as shown in RM's Figure 46-3. PDB back-to-back chain forming PDB0-PDB1 ring. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 ch5 External input channel 28 is selected, as it is connected to potentiometer on the EVB. PDB0 is triggered by LPIT ch0 at 500ms rate. * ------------------------------------------------------------------------------ * Test HW: S32K148EVB-Q144 * MCU: FS32K144UAVLQ 0N20V * Target: Debug_FLASH * EVB connection: UART terminal 115200, 8N1 * Compiler: S32DS.ARM.3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: S32DS ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 Jan-26-2023 Petr Stancik Initial version, based on adc_hwtrigger_s32k148 *******************************************************************************/

       This routine implements all four different mask setting methods.Users can refer to these routines to implement some application scenarios.Please note that this routine is for reference only.When posting this routine, I only did some limited tests, and I don't make sure that there are no problems. If you find it, please leave a message and I will revise it in time.       When the program was flashed into the S32K142EVB, the Blue Led will toggles every 500ms, this Led shows that the program is running on well condictions. If a message was received by S32K142EVB from external CAN bus, the Green Led will toggle,at the same time, the S32K142EVB will sent a message to CAN Bus which have the same data with the message received,and the ID is 0x02.At the last,the Red Led will toggle when a CAN error is occurd.   1.FlexCAN Mask Setting Overview          S32K1XX FlexCAN support  Frame mask function ,as you can see the FlexCAN mask can be set to Global Mask or Individual Mask,and user can choose to use FIFO or MB to receive message,but only MB can be used for sending messages.and one more thing you should be care is that the FIFO can not be used for CAN FD,this is because the FIFO data filed only support 8 bit datafiled.           If you use MB14 or MB15, have to set the mask of these tow MBs separately，and you can take a look at the two functions in the below. ->FLEXCAN_DRV_SetRxMb14Mask();  ->FLEXCAN_DRV_SetRxMb15Mask();   2.Hardware Needs. 1.S32k142EVB,(or own made board which can support CAN communications.) 2.CAN TOOL's which used for send or receive messages from CAN Bus on your computer.   If you don't have such tools ,you can use another board which can replace the CAN tools to send or receive CAN messages. 3.S32K142EVB should be powered by external 12V DC, and don't forget to connect the J107 to 1-2.   3.Software Needs. 1.This demo build on S32 Design Studio for ARM V2.2  2.The SDK version is SDK_S32K1XX_15   4.FlexCAN_RX_MB_Mask_Setting 4.1.Set the Mask Type to Global Mask Type.      In this case, we can only receive the messages which ID from 0x300~0x37F and 0x400~0x47F.      If you try to sent the messages with other ID's, the S32K142EVB will not have any reponse!  4.2.Set the Mask Type to Individual Mask Type.      In this routine,we can only receive frames with IDs in the range of 0x400~0x47F. 5.FlexCAN_RX_FIFO_Mask_Setting 5.1.Set the Mask Type to Global Mask Type.      In this routine,we can only receive frames with IDs in the range of 0x10~0x17, 0x20~0x27,0x30~0x37,0x40~0x47, 0x50~0x57,0x60~0x67,0x70~0x77,0x80~0x87. 5.2.Set the Mask Type to Individual Mask Type.      In this routine, we can only receive frames with IDs in the range of 0x10~0x17,0x20~0x27,0x30~0x37,0x40~0x47, 0x50~0x57,0x60~0x67,0x70~0x77,0x80~0x87.   End       If you need to use CAN FD, please note that FIFO cannot be used. Regarding FIFO, it has three filtering formats, you can refer to the following chapters in the data sheet for details. S32K-RM Rev 13. Chapter:55.4.2.15 Rx FIFO Global Mask register (RXFGMASK) Chapter:55.4.6 Rx FIFO structure          

Question As we know, the TPPSDK supports S32K144 MCU and various Kinetis MCUs to initialize GD3000 in NXP MC solutions. Because of the release of S32K3 and related SW RTD, it’s necessary to expand the capability of TPPSDK to support S32K3 MC based RTD LLD driver or MCAL driver. Unfortunately, the AA team will not maintain the TPPSDK anymore.  How could we configure the GD3000 chip for S32K3 platform?   Answer I took some time to finish this work. Here I'd like to share you the The Expanded TPPSDK Based on S32K3 RTD that is suitable for S32K3 MC application. You can find the Application Note, the source code of new TPPSDK (GD3000 driver), two examples in the attachment. I hope these materials can help you get start with the expanded TPPSDK on S32K3.

           The hardware of this routine is based on S32K142EVB, the IDE is S32_Design_Studio for ARM 2018.R1, SDK version is S32K1xx_RTM_3.0.0, PTB12 is used to simulate Hall pulse output,PTC12 and PTC13 are buttons to change the flip frequency of PTB12 port, and PTB13 is used as the input capture port. When using the demo program in this article, you need to connect PTB12 and PTB13 ports.   Here we assume that we are using a brushed DC motor!   1.The Hall sensor       The Hall sensor is a magnetic induction sensor. The magnetic ring and the Hall element form an induction combination. The magnetic ring rotates with the rotor. The Hall induction magnetic ring rotates with the rotor. , 3-pole pairs, 4-pole pairs, etc., each pair of poles is divided into two levels of N.S. A pair of magnetic poles outputs one pulse signal, and multiple magnetic poles output multiple pulse signals. The number of magnetic pole stages determines the number of pulse signals. , the higher the accuracy.   Hall sensor 2.The relationship between the motor magnetic ring series and the output Hall waveform 5 pole pairs 3.Determination of motor rotation direction         The direction of the motor is judged by the phase difference of the two Hall signals. As shown in the figure below, the phase of Sensor A is ahead of Sensor B, so it can be considered that the current rotation direction of the motor is clockwise.   4.Calculation of motor speed         The speed of the motor can be calculated by the pulse width of the pulse, and the number of revolutions of the motor can be calculated by the number of pulses. Assuming that the Hall magnetic ring of the motor has 5 pairs of poles, it means that there are five pulses in one revolution of the motor, and the speed of the motor = 60 / (t1 * 5) rev/min. The number of pulses can be obtained by the edge capture function of the FTM. Motor speed and stroke         Assuming that the clock of the FTM is 2MHz, then it takes 1/2000000 seconds for the counter to add 1. Since the unit of the motor speed is rpm, the calculation formula of the motor speed is : -> Motor Speed = 60 / (5 * a* (1 / 2000000))         In this formula, '5' is the number of pole pairs of the magnetic ring, and 'a' is the difference of the counter corresponding to the falling edge of two consecutive pules.         Let’s do a test, the square wave in the below figure is the outputs of PTB12, and the output pulse period is 32.1ms. Then the time required for the motor to rotate once should be:32.1ms *5 = 160.5ms, then the speed of the motor should be: 60 * 1000 / 160.5 = 373.83rpm.   PTB2 output square wave          The below picture is directly obtained by the debugger. It can be seen that the speed of the motor at this time is 373, which is not much different from the value measured by the oscilloscope, which is 373.83. This is because I did not use the floating-point calculation result in the program. In summary, we use the input capture function of the FTM module completes the calculation of the motor speed.   debuger monitor results 5.How to calculate the direction of rotation of the motor         Above we calculated the speed of the motor, but did not make judgement on the direction of the rotation of the motor. As mentioned above, the rotation direction of the motor is judged by the phase difference of the two Hall pulse waveforms. Usually, we think of using the timestamp to judge the current state of the phase, so we will enable the two input captures, and then calculate the two Halls timestamp of the falling edge of the pulse.         In fact, there is a simpler method, it only needs to read the high and low state of the other Hall pulse level when the falling edge of one hall pulse is interrupted. In short, we only need to enable one input capture, and the other to be used as a GPIO port.

Hi all, Recently, we completed S32K Sound Mixer reference code and demo, and glad to share this demo at here.   Some key feature of this demo:  - Demo HW based on S32K344/S32K148 + audio codec SGTL5000 + QSPI flash MX25L6433.  - Demo SW based on S32K3 RTD RTM 2.0.0 and S32K1 RTD RTM 1.0.0.  - Demo provided 2 kinds of sound mixing algorithm realization code, and corresponding audio materials and codec SGTL5000 driver.  - Demo showed how to programming QSPI flash and its AHB accessing via audio storage and playing process.  - Demo used mono audio as source for processing, and output stereo audio (I2S format) via SAI HW FIFO combine (Line_Mux) function with nearly no extra cost.   HMI/Cluster apps need multiple audio sources (usually warning sounds) be played simultaneously, which brings sound mixing ability requirement. However, S32K1/3 lack of this HW/SW feature support. With the demand from local key customer, and considering potential customer requirements, we planned to enable a SW sound mixer with scheduled peripherals, to enhance the S32K family audio mixing ability. It shall be easy of using/porting on S32K1/3, and use QSPI flash (AHB mode read) to store the music. Attachment the Sound Mixer package includes 2 sound mixing examples based on S32K344 EVB and S32K148 T-Box RDB, and some slides to introduce this implementation and quick start guide.    Thanks and welcome any comment from you. Best Regards, Shuailin Li

Symptoms Recently found the compatibility issue is a troublesome problem especially when we are supporting different version of RTD. Remove/install the RTD SDK and plug, but it is not a perfect way because reinstall the RTD would cause a lot of time, sometimes it is unreliable. Diagnosis After investigated the mechanism of CT and MEX file, and found a work around to let the old project can be run in new version of RTD basis. Solution Already tested it with several reference code and examples of RTD, it can work. Attached is the document.

Symptoms   Diagnosis   Solution