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******************************************************************************* * * The purpose of this demo application is to present a usage of the ADC_SAR and * BCTU IP Driver for the S32K3xx MCU. * * The example uses the PIT0 trigger to trigger BCTU conversion list. Five standard * ADC channels are selected to be converted. * Converted result from BCTU data register are moved by DMA into result array. * This result array should be placed into no cacheable area if data cache is enabled. * * ADC channel S10 is connected to board's potentiometer, and converted value is * used to dim board's LED. * * * ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: RTD 1.0.0 * Debugger: Lauterbach * Target: internal_FLASH ********************************************************************************
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  EV/HEV is the mega trend and NXP focused area. E-Compressor controller is a key and additional component of EV/HEV vs. traditional vehicle. While S32K14x is the perfect product for mainstream E-compressor application. To accelerate customer develop period in automotive E-compressor application, we develop the S32K142-ECC RDB. Actually, S32K142-ECC is not only suitable for E-compressor, but also can be used in other high voltage PMSM/BLDC application in automotive industry. HuabiaoTang_0-1645002142510.png This RDB (Reference Design Board) hardware is based on NXP S32K142 high-performance automotive-grade MCU and UJA1075A SBC (system basic chip) provides the following features: ◼ Support high voltage up to 400V and power range up to 3.7kW BLDC/PMSM applications. ◼ Support high voltage isolated 12V power supply, which for SBC, IPM and MCU power supply. ◼ Hardware support 3 types of current sampling solutions: single shunt, dual shunts and triple shunts; software support dual shunts in V1.0. ◼ Support multiple diagnose and protection covering UV, OV, OT, OC, Short, Stall Detection, etc.; ◼ Support speed/control commands from CAN/LIN/FreeMASTER; ◼ Support external watch dog for safety. the RDB hardware system block diagram is as below: HuabiaoTang_1-1645002667389.png The software package of S32K142-ECC RDB is available to enable user to evaluate the S32K142 based high voltage e-compressor motor control performance with out-of-box and build their own e-compressor motor control product prototype as a general high voltage motor control hardware platform. The software package has the following features: ◼ Support e-compressor control by FreeMASTER CAN/UART; ◼ Support e-compressor speed control and state feedback by CAN DBC file; ◼ Implemented advanced motor control algorithm, including low speed torque compensation, MTPA, 2-stage current alignment and enhanced ATO to make sure the motor robust start up and high efficiency; ◼ Support rich motor control diagnostic and protection: OV, UV, OC, OT, stall and phase loss and so on; ◼ Provide S32DS IDE and IAR for ARM IDE projects, support U-Multilink and J-LINK debugger; We have several S32K142-ECC RDB in stock, if you have the project and need the RDB for evaluation, please contact your local NXP or NXP dist FAE, Sales and Marketing. For technique support, contact [email protected]  thanks, Best regards, Raymond
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Hi Everyone, Here I'd like to share three S32K1xx SDK FlexCAN PD and PAL component sample projects to demonstrate its basic and advanced features: 1. S32K144_CAN_PAL_SamplePrj_Basic_TxRx_ID_FiltersConfig_SDKRTM3P0 34.png Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PAL driver: 1. Configure to receiver the following exact 16 standard ID CAN message with RxFIFO 8x ID filter table with format type-B(2x 16-bit ID) Standard ID: 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x111, 0x222, 0x333, 0x444, 0x555, 0x666, 0x777, 0x788 The RxFIFO is configured to use CPU interrupt for CAN message receive, and CAN_PAL cannot support DMA for RxFIFO directly. Note: A. FlexCAN of S32K1xx dose not support to receive CAN-FD message frame with RxFIFO, so no CAN-FD support in this demo project. B. All the filter table elements must be configured to contain only standard or extend ID, if it contains both standard and extend ID, the IDE-bit mask will be ignored.  C. After RxFIFO enabled, MB0~MB5 is used as the RX FIFO, at least MB6~MB7 are used as the ID filter table(to store the acceptance ID), the actual available MB number is determined by RxFIFO ID filter table size, details please refer to section--55.4.6 Rx FIFO structure of S32K1xx RM Rev.12.1  2. Configure two extra individual MBs to receive: RX_MB1: 16 standard ID CAN 2.0 message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F and  RX_MB2: 4 standard ID CAN 2.0 message with the ID8 and ID9 masked(mask=0x4FF, acceptance ID = 0x256): 0x056, 0x156, 0x256 and 0x356 Both the RxFIFO and individual MBs RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure one individual MB to blocking transmit a standard CAN 2.0 message with ID = 0x100 periodically(period = 5ms), and also send back the received CAN messages(if it's available) to the CAN bus as a response. 4. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is commented by default, so manual recovery codes does not work. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is not done this sample project!!!  5. There 3 on-board RGB LED are used to indicate the FlexCAN working status: red RGB LED will be toggled after RXFIFO received a CAN message; blue RGB LED will be toggled after individual MB received a CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB 2.S32K144_CAN_PAL_CANFD_ClassicCAN_Mix_TxRx_Wakeup_SDKRTM3P0 39.png Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PAL driver: 1. Configure to enable CAN-FD with 500 Kbit/s arbitration phase bitrate and 2Mbit/s data phase bitrate, so it can support both classic CAN 2.0 A/B and CAn-FD message frame transfer. Note: A. The RxFIFO is disabled to work with CAN-FD message frame. B. After CAN-FD enabled, CAN-FD message frame data length can support up to 64 Bytes, so the actual available MB number is determined by the max frame data length need to support, details please refer to section--55.4.5 FlexCAN message buffer memory map of S32K1xx RM Rev.12.1  C. In order to support bitrate bigger than 1Mbit/s for CAN-FD data phase with bitrate switch enabed, PE clock source of CAN_PAL should be configured to use peripheral clock(80MHz generated from SPLL) instead of 8MHz oscillator clock; 2. Configure 3 individual MBs to receive: RX_MB0: 16 extend ID CAN 2.0/FD message with the lower 4LSB masked(mask=0x1FFFFFF0, acceptance ID = 0xfff021): 0xfff020 ~ 0xfff02F RX_MB1: 16 standard ID CAN 2.0/FD message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F RX_MB2: 4 standard ID CAN 2.0/FD message with the ID8 and ID9 masked(mask=0x4FF, acceptance ID = 0x256): 0x056, 0x156, 0x256 and 0x356 Both the RxFIFO and individual MBs RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure 3 individual MBs to transmit: TX_MB0: send back any CAN(2.0/FD) messages received from RX_MB0; TX_MB1: send back any CAN(2.0/FD) messages received from RX_MB1; TX_MB2: send back any CAN(2.0/FD) messages received from RX_MB2; 4. Configure one individual MB(TX_MB3) to blocking transmit a standard CAN FD message with ID = 0x100 periodically(period = 5ms) and length = 64 bytes, and also send back the received CAN messages(if it's available) to the CAN bus as a response. 5. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is commented by default, so manual recovery codes does not work. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is not done this sample project!!!  6. Provided the sample codes of how to configure FlexCAN as the VLPS low-power mode wakeup source, RXD of FlexCAN0 is configured as GPIO IRQ interrupt with falling edge trigger before entering VLPS mode, and after wakeup, re-configure it back to RXD function. Note: A. S32K1xx FlexCAN is unable to work as the VLPS wakeup source B. After wakeup, it's necessary to call SDK clock_manager's API--CLOCK_SYS_UpdateConfiguration() to reconfigure the system clock, or it will use 8MHz SIRC, 48 MHZ FIRC and SPLL are disabled after wakeup. c. By default, after receive ID = 0x123(it can be configured via macro LP_REQUEST_ID in /include/Config.h ) standard CAN(CAN 2.0 or CAN-FD), the MCU will go to VLPS mode 7. There 3 on-board RGB LED are used to indicate the FlexCAN working status: blue RGB LED will be toggled after individual MB received a CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB 3.S32K144_FlexCAN_PD_SamplePrj_RxFIFO_DMA_Receive_SDKRTM3P0 36.png Functions implementation key points and tips: This sample project is made to demonstrate the following S32K1xx FlexCAN features with SDK FlexCAN PD driver: 1. Configure to receiver the following exact 16 standard ID CAN message with RxFIFO 8x ID filter table with format type-B(2x 16-bit ID) Standard ID: 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x111, 0x222, 0x333, 0x444, 0x555, 0x666, 0x777, 0x788 The RxFIFO is also configured to use eDMA channel 0 for CAN message receive, user can easily change to use CPU interrupt for RxFIFO in processor expert flexcan component configuration if required. Note: A. FlexCAN of S32K1xx dose not support to receive CAN-FD message frame with RxFIFO, so no CAN-FD support in this demo project. B. all the filter table elements must be configured to contain only standard or extend ID, if it contains both standard and extend ID, the IDE-bit mask will be ignored.  C. After RxFIFO enabled, MB0~MB5 is used as the RX FIFO, at least MB6~MB7 are used as the ID filter table(to store the acceptance ID), the actual available MB number is determined by RxFIFO ID filter table size, details please refer to section--55.4.6 Rx FIFO structure of S32K1xx RM Rev.12.1  2. Configure one extra individual MB(MB8) to receive 16 standard ID CAN 2.0 message with the lower 4LSB masked(mask=0x7F0, acceptance ID = 0x123): 0x120 ~ 0x12F; Both RxFIFO and individual MB RX use non-blocking receive method/API with MB TX/RX complete ISR callback installed to set a new circle buffer for next message frame receive 3. Configure one individual MB(MB9) to blocking transmit a standard CAN 2.0 message with ID = 0x100 periodically(period = 5ms), and also send back the received CAN messages(if it's available) to the CAN bus as a response. 4. Provide the FlexCAN bus-off manual recovery configuration API and interrupt ISR callback codes for reference, changing the macro CAN_BUSOFF_RECOVERY_MANUAL(in include/Config.h) to select the bus off recovery method(enable the macro definition: manual recovery, comment the macro definition: automatic recovery); Note: In this sample project, the macro CAN_BUSOFF_RECOVERY_MANUA is enabled by default, and manual recovery codes works. To make the bus-off recovery callback work, user should replace the flexcan PD driver codes and S32K144_feature.h with S32K1xx RTM 4.0.0(which can be downloaded from nxp.com with registered account login and then installed stand-alone or installed via S32DS v3.3 IDE update). This is already done this sample project!!!  5. There 3 on-board RGB LED are used to indicate the FlexCAN working status: red RGB LED will be toggled after RXFIFO received any CAN message; blue RGB LED will be toggled after individual MB received any CAN message; green RGB LED will be turn ON after enter bus-off and turn OFF after exist bus-off(recover successfully). To run this sample project, the following HW and SW require: SW: S32DS for ARM v2.2 IDE with S32K1xx SDK RTM 3.0.3 installation HW: S32K144EVB-Q100 Rev.C with a DC-12V adapter for its power supply by J16 and a USB-to-CAN adapter(such as PEAK CAN) to connect PC with J13 of the EVB Attached are the sample project for your reference, and details can also be fiound with the detailed comments in source codes. Hope it can help you, and any comments/questions are welcomed, and you can just ask in this thread and I will try to anwser them. Best regard, Enwei Hu(胡恩伟).  
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Hello,      NXP does a big change on document structure.     Generally, you can find pin assignment table, interrupt mapping and memory map table in RM. But now, these information change to Excel files and attached in RM.   For example on S32K.    You will find the words in RM, like 'For reset values per port, see IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual.'    Then, please go to attachment tab of your PDF file viewer, like Adobe Acrobat Reader DC.     These steps are also fit for MPC57xx , S32R family. Cheers! Oliver
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Dear all, I'd like to share some useful tips about S32DS for ARM v2018.R1 IDE and S32K1xx development  in Chinese as below: 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》; 《S32K SDK使用详解之S32 SDK软件编程思想详解》; 《S32K SDK使用详解之S32 SDK软件架构详解》; 《 S32K1xx系列MCU使用Tips--功能介绍及软件开发和硬件设计FAQ》; 《 S32K1xx系列MCU使用Tips--Flash加密后不断复位无法连接调试器的问题解决》; 《S32DS使用Tips--S32DS for Power V1.2 链接文件和启动过程详解》; 《S32K1xx系列MCU使用Tips之SDK软件架构和使用详解》; 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》; 《S32DS IDE使用Tips--应用工程调试常见问题(FAQ)答疑》; 《 S32DS 使用Tips之S32DS for Power不同版本之间的GNU工具链差异与外设寄存器位域访问问题总结》; 《 S32DS使用Tips之S32DS for Power v1.1应用工程升级到v1.2重新编译运行程序跑飞问题解决》; 《S32DS 使用tips--S32DS for ARM v1.3工程到S32DS for ARM V2.0迁移升级方法和注意事项》; 《  S32DS 使用 tips--工程属性配置(编译选项和C编译器、汇编器及链接器设置)》; 《 S32DS使用Tips--如何编译生成和调用静态库》; 《S32DS使用Tips--如何通过创建新的编译目标(Build Target)在同一个S32DS工程中同时编译静态库和应用程序》; 《 S32DS使用Tips--如何配置和使能Attach功能定位软件程序bug和完成bootloader与应用程序工程的联合调试》; 《 CodeWarrior与S32DS IDE使用 Tips之如何在应用工程中保留定义但未使用的全局常量、变量(用于参数标定)》; 《 S32DS 使用 tips--使用Flash from file下载S19或elf文件》; 《S32DS for ARM v2018.R1安装IAR Eclipse插件调用IAR工具链开发S32K系列MCU应用程序详解》 For more contents, please follow below link: “汽车电子expert成长之路”微信公众号最新最全原创技术分享文章列表 ; Hope this can help you and have a nice day~! Best regard, Enwei Hu(胡恩伟)
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I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 
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Where can I get s32k14x data sheet or reference manual???
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This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2 (GPIO) for wake-up from Standby mode on the S32K358 MCU, with RTC time preservation across Standby and functional reset clock sourced through SIRC. Test HW: FRDM-A-S32K358 / S32K3X8EVB-Q289 MCU: S32K358 IDE: S32DS v3.5 & S32DS v3.6.x SDK release: RTD 6.0.0 Debugger: PE Micro Target: internal_FLASH This example routine configures the WKPU unit for GPIO interrupt wake-up using pins PTH1 (WKPU0) and PTH3 (WKPU15). RTC time is preserved across Standby via the VDDBY supply domain. After wake-up, the functional reset clock is sourced from SIRC before transitioning to the main PLL. No fast wake-up path is used. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU0 (PTH1) and WKPU15 (PTH3) as wake-up sources. Enters Standby mode (normal wake-up). After pressing USER0/SW4(PTH1), MCU wakes up, resets and polls for USER1/SW5 (PTH3)  or USER0/SW4(PTH1) to be pressed again. Terminal output Settings: 115200 baud — 8 data bits — No parity — 1 stop bit — No flow control (LPUART6) The terminal interaction follows three distinct phases each cycle: boot/wake-up banner → SW6 to read RTC time → SW5 to enter Standby. A representative session is shown below. 1 — Initial power-on (cold start) RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 15 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 0 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 2 2 — Enter Standby → Wake-up → RTC time preserved MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 13 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 14 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 14 3 — Multiple Standby cycles (RTC keeps incrementing) MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 59 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 0 MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 4 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 6 Disclaimer — PTH3 pin on S32K3X8EVB-Q289: The EVB button mapped to PTH3 may fail to trigger a wake-up event. This is caused by the button connected to the VDD_HV_B (3.3 V) rail, while PTH3 belongs to the VDD_HV_A domain, which defaults to 5 V. The signal level mismatch prevents correct wake-up detection. Workaround: switch Jumper J23 from position 1-2 (default, 5 V) to position 2-3 (3.3 V) to align VDD_HV_A with the button voltage level before testing wake-up via PTH3. This example is provided as is with no guarantees and no support.
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * on the board RD-BESSK358BMU * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * RD-BESSK358BMU: * - All jumpers in default positions * - SW2 needs to be ON * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: RD-BESSK358BMU SCH-91654 REV B1 * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: RJ45 <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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Application note AN5258 for the S32K1 describes how to implement external pulse counting using DMA and PORT modules. Referring to that application note, we will implement a similar function using SIUL2 and DMA on the S32K3.   1. Introduction This article describes how to perform pulse counting using Enhanced Direct Memory Access (eDMA) and the SIUL2 module on a 32-bit automotive MCU in the S32K3 series. Typically, signal pulses can be counted using the eMios module; however, eMios can also be used for PWM output, ICU, OCU, and GPT. If resources available for eMios are insufficient, consider using the SIUL2 and DMA modules to implement external pulse counting. In this note, the SIUL2 module will be used to capture multiple pulse inputs, and the current major loop iteration count(CITER) register of the eDMA channel will be used as a pulse counter.   2. SIUL2 supports DMA triggering. SIUL2, or System Integration Unit Lite2, is primarily responsible for controlling the electrical attributes, multiplexing functions, GPIO, EIRQ, etc., of external pins. For the S32K3, SIUL2 functions can be categorized as follows: Pin mux/pad control: Configures MSCR, IMCR, etc. GPIO input/output: Typically used via Siul2_Dio/Siul2_Port drivers. External interrupt EIRQ: Only pins with the EIRQn option support SIUL2 external interrupts. DMA is triggered by external edge events. When using SIUL2 pins to trigger DMA, note that: SIUL2 EIRQ[0-15] can be used for interrupt requests or DMA requests, while EIRQ[16-31] can only be used for interrupt requests. In other words, the SIU2L module can support up to 16 external edge events triggering DMA. The file "S32K3xx_IOMUX.xlsx" can be found in the datasheet appendix.   3. Basic Event Chain for SIUL2 Triggered DMA SIUL2 external events still rely on the EIRQ path: a pad needs to be connected to the corresponding EIRQ input via IMCR, input buffering needs to be enabled, rising/falling edge detection needs to be configured, and the relevant request needs to be enabled. In this example, PTB26 is configured as SIUL2 EIRQ13, and external interrupt configuration is completed through registers such as IREER/IFEER and DIRSR. IP_SIUL2->IREER0 |= (1 << 13); // IREER0[EIRE13] = 1 (Enable Rising Edge) IP_SIUL2->IFEER0 &= ~(1 << 13); // IFEER0[EIRE13] = 1 (Enable Falling Edge) IP_SIUL2->DIRSR0 |= (1 << 13); // Select DMA Request for PTB26 The above bare-metal code clearly shows how to configure the Siul2 module to trigger DMA. However, if using RTD, note that: the current "Siul2_Icu" driver does not support configuring the DMA option. Therefore, when using the "Siul2_Icu" component, you also need to manually add and modify the "DIRSRx" bit to 1, i.e., select to enable "DMA request". SIUL2->DIRSR0 |= (1<<13);/* Select DMA Request for PTB26 */   4. DMAMUX / RM Configuration After a DMA request is generated on the SIUL2 side, the request source needs to be connected to a DMA channel via DMAMUX. This path is described in “S32K3xx_DMAMUX_map.xlsx”: 1.EIRQ[0 ~ 7] corresponds to 1 to 7 of DMAMUX0 Source, and EIRQ[8 ~ 15] corresponds to 1 to 7 of DMAMUX1 Source. 2.TCD 0 ~ 15 can be configured with any channel corresponding to EIRQ[0 ~ 7], and TCD 15 ~ 31 can be configured with any channel corresponding to EIRQ[8 ~ 15].  eDMA is mainly used for data transfer between main memory and other peripheral register spaces without CPU intervention. Upon receiving a peripheral request, the eDMA module's second loop begins basic data transfer. We set an empty transfer; each time SIUL2 triggers DMA, an empty transfer is performed, and the CITER bit is decremented accordingly. At this time, the value of the CITER register reflects the actual pulse count. Based on the above principle, we can calculate the pulse count or pulse frequency by periodically reading the CITER register. Note:       The CITER register can only hold a maximum of 15 bits of data. Check the CITER register each time you read it to ensure its value is not zero. When the CITER register is zero, CITER will reload its value from the BITER register and continue decrementing.   5. Example Project Demonstration This example program is based on the S32K344, using RTD version 7.0.1. It implements the function of acquiring the pulse frequency input from PTB26, PTA18, and PTA19 pins. 1.The timer is set to 1 second; the count value read in 1 second can be directly used as the measured frequency. 2. The maximum value of the CITER register is 0x7FFF, or 32767. When the count value exceeds 0x7FFF, the register will be reloaded with an initial value of 0x7FFF.. 3. CITER triggers a DMA interrupt during reload. "g_DmaChx_CallbackCounter" can be used to record the number of overflow reloads. 4. Based on CITER and "g_DmaCh16_CallbackCounter", high-frequency pulse input counting can be achieved. 5. To measure an input frequency of 40kHz, connect the signal generator's output signal to PTB26, PTA18, and PTA19. Senlent_0-1787211805542.png 6. Test result in S32 DS. Senlent_1-1787211927621.png          Using the Siul2 module to trigger DMA for counting is a very efficient method, but it should be noted that if other eDMA transfers are enabled in your application, more testing is required to ensure stable execution of all eDMA channels.  
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FRDM-A-S32K358 LwIP enablement with RTD 6.0.0.
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Mapping between SPD eMCEM and DCM for S32K311, S32K312, S32K314, S32K322, S32K324, S32K341, S32K342, S32K344.
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**************************************************************************************************** * Detailed Description: * This example uses BIST and EMCEM drivers from SPD 1.0.6. * BIST and EMCEM can be enabled or disabled using macros. * * BIST runs immediately after a power-on reset and triggers an ST_DONE reset. * EMCEM initialization is only possible after a system reset without an attached debugger. * Therefore, wait loops (controlled by macros) are used to manage execution flow * for both BIST and EMCEM. * * Fault injection is selected via macros: * - FAULT_EMCEM_DCM_NCF_1_AD_EDC_ERR_OUT → handled via NMI * - FAULT_EMCEM_DCM_NCF_2_PRAM1_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_2_ITCM_MULTI_ERR → handled via BusFault (if INJECT_EIM) and FCCU alarm * - FAULT_EMCEM_DCM_NCF_3_PFO_CODE_ERR → FCCU alarm → (if TIMEOUT_PFO_CODE_ERR) → NMI * - FAULT_EMCEM_DCM_NCF_5_STCU_NCF → handled via FCCU alarm * - FAULT_EMCEM_DCM_NCF_7_SW_NCF_0 → FOSU Destructive reset * (read resetReason after reset, MCU_FCCU_FTR_RESET). * FOSU triggers as no FCCU reaction is configured for NCF_7 * while FCCU is enabled and reactions are configured for other faults. * * ------------------------------------------------------------------------------------------------ * MCU: S32K3x4EVB-Q257 * Fsys: 160 MHz PLL with 16 MHz crystal reference * Debugger: Lauterbach Trace32, S32DS IDE 3.6.5 * Target: internal_FLASH ****************************************************************************************************
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/********************************************************************************************** * File main.c * Owner Daniel Martynek * Version 1.0 * Date May-12-2026 * Classification General Business Information ********************************************************************************************** * Detailed Description: * The code enables the data cache, reads a value from DFlash to load it into the cache, * then uses the LMEM interface to inspect and directly overwrite the corresponding cache line. * Finally, it reads the same address again through the CPU, which returns the modified value * from the cache instead of the original data stored in DFlash. * * In this simple setup, where only the data cache is enabled, the code executes from PFlash, * and the accessed data is located in DFlas — the cache line is unlikely to be re-evaluated. * Therefore, the CPU may consistently return the modified value - this behavior is not guaranteed. * ------------------------------------------------------------------------------------- * MCU: S32K142 * Fsys: 48MHz, FIRC * RTD: S32K1_RTD_3_0_0_QLP06_D2603_ASR_REL_4_7_REV_0000_20260320 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************
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The attached spreadsheet provides mapping between EIM and DCM faults for the S32K3x1, S32K3x2, S32K344, S32K324, and S32K314 devices. Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K344 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions. * * Configuration: * - Updated pin configuration * - Modified FXOSC, PLLAUX + dividers * - Platform: added EMAC_0_IRQn interrupt * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Added DIO * * main.c * - Updated only the header * device.c * - No updates * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: MR-CANHUBK344 * MCU: S32K344 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: EMAC <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K389 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions, except J848, J822, J1136 - disconnected to enable an external debugger. * * TJA1103-SDBR: * mode rev-RMII * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 1-2 * * Configuration: * - Updated pin configuration * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K389EVB-Q437 SCH-94080 REV C, 700-94080 REV A * MCU: S32K389 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC1_SABRE <-> TJA1103-SDBR (rev-RMII mode) <-> RDDRONE-T1ADAPT <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1120-SDBR: * mode RGMII-ID (both TXC/RXC), Master, Autonomous, XTAL * CONFIG 3 2-3 * CONFIG 5 1-2 * CONFIG 4,6 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1120-SDBR <-> Media converter TE-1402 (1G, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * S32K3X8EVB-Q289: * - All jumpers in default positions except: jumper J685 2-3 * * TJA1103-SDBR: * mode RGMII-ID (both TXC/RXC) * CONFIG 0,1 1-2 * CONFIG 2,4 2-3 * CONFIG 3 open * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 100M * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X8EVB-Q289 SCH-54870 REV C, 700-54870 REV A * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: SABRE <-> TJA1103-SDBR <-> Media converter TE-1402 (100M, Follower) <-> * USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K388 to enable pinging the lwIP stack * from the command window * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * EVB: * - All jumpers in default positions except: jumper J361 must be closed. * - Soldering rework required to connect an external debugger. * See S32K388EVB-Q289_HW_User Manual_A3.pdf, chapter 15 (Errata). * * Configuration: * - Updated pin configuration * - Modified PLLAUX + dividers * - Updated GMACx clocks * - Platform: added GMAC0 interrupts * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G, EthIndex = 0 * - Added DIO * * main.c * - Updated only the header * device.c * - Added RTD workaround for DCMRWF* registers * (copied from example S32K388_gptp_ds, S32K3xx gPTP Stack 1.0.0) * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * --------------------------------------------------------------------------------------- * Test HW: S32K388EVB-Q289 SCH-88925 REV A, 700-88925 REV X1 * MCU: S32K388 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: GMAC0 <-> Media converter TE-1402 (1G, Follower) <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11
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