Example_S32K142_LMEM_Cache_v1_0_S32DS3.6_RTD300

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/**********************************************************************************************
* File main.c
* Owner Daniel Martynek
* Version 1.0
* Date May-12-2026
* Classification General Business Information
**********************************************************************************************
* Detailed Description:
* The code enables the data cache, reads a value from DFlash to load it into the cache,
* then uses the LMEM interface to inspect and directly overwrite the corresponding cache line.
* Finally, it reads the same address again through the CPU, which returns the modified value
* from the cache instead of the original data stored in DFlash.
*
* In this simple setup, where only the data cache is enabled, the code executes from PFlash,
* and the accessed data is located in DFlas — the cache line is unlikely to be re-evaluated.
* Therefore, the CPU may consistently return the modified value - this behavior is not guaranteed.
*
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* MCU: S32K142
* Fsys: 48MHz, FIRC
* RTD: S32K1_RTD_3_0_0_QLP06_D2603_ASR_REL_4_7_REV_0000_20260320
* Debugger: Lauterbach Trace32
* Target: Internal_FLASH
**********************************************************************************************