This doc explain how to configure a new LPDDR4 and test it on S32G, contents as follows: 目录 1    硬件资源，文档及工具下载... 2 1.1    硬件资源... 2 1.2    内存配置测试相关的文档... 2 1.3    内存配置与压力测试工具. 3 2    内存设计要求... 3 3    LPDDR4基础... 3 3.1    基本知识... 3 3.2    Inline ECC.. 4 4    硬件连接... 6 5    S32G+LPDDR4内存配置与测试步骤... 8 5.1    配置LPDDR4初始化寄存器设置... 9 5.2    使用内存测试工具初始化PHY及生成DDRC配置Uboot源代码    11 5.3    生成DDRC配置ATF源代码(从BSP32开始) 14 5.4    测试内存... 18 5.5    其它尺寸的LPDDR4配置... 19 6    测试失败的DEBUG.. 24 7    内存参数应用到Uboot中... 25 8    内存参数应用到ATF中... 25 9    附录... 25 9.1    一个重要的DDR TOOL bug Fix. 25 9.2    Uboot DDR测试工具... 26 9.3    Kernel DDR测试工具... 27 9.4    附DDR tool测试项截图... 28   Contents 1    Hardware Materials, Docs and Tools Needed. 2 1.1    Hardware resource. 2 1.2    Related docs of memory configuration and test 2 1.3    Memory configuration and test tools. 3 2    Memory Hardware Design Requirement 3 3    LPDDR4 Basics. 3 3.1    Basic Knowledge. 3 3.2    Inline ECC.. 5 4    Hardware Design. 7 5    S32G+LPDDR4 Memory Configuration and Test Steps. 8 5.1    Configure LPDDR4 DDRC Register Settings. 9 5.2    Use the Memory Test Tool to Initialize the PHY and Generate the DDRC Configuration Uboot Source Code  12 5.3    Generate ddrc configuration ATF source code (starting from bsp32) 15 5.4    Memory Test 19 5.5    Other size LPDDR4 configurations. 20 6    Debug of the Fails of Test 25 7    Modify the DDRC register settings in Uboot 26 8    Modify the DDRC register settings in ATF. 26 9    Appendix. 26 9.1    A importance DDR TOOL bug Fix. 26 9.2    Uboot DDR Test Tools. 27 9.3    Kernel DDR Test Tool 28 9.4    Attached Screenshot of DDR Tool Test Items. 29

This doc explain  where is the design resource and what they are of S32G in Chinese,  Contents as follows: 目录 1 www.nxp.com 官网资源 ............................................. 2 1.1 www.nxp.com Documentation ................................ 4 1.2 www.nxp.com Tools&Software ............................. 10 2 Flexera资源 ............................................................. 18 2.1 Automotive HW-S32G Evaluation Board .............. 21 2.2 Automotive HW-S32G GoldBox ........................... 22 2.3 Automotive HW-S32G RDB2(RDB不再说明) ....... 22 2.4 Automotive SW-S32G2 Standard Software.......... 23 2.5 Automotive SW-S32G2 reference Software ......... 28 2.6 Automotive SW-S32G2 Tools .............................. 30 3 Docstore资源 ........................................................... 31

功能需求 RT117X系列MCU在汽车和工业类产品中有广泛应用，有很多客户对LIN通讯有需求，RT1176有12路独立的LPUART接口，最大支持的波特率能支持到20M，而且每一路都支持Break发送和中断接收，可以用来配合定时器实现LIN的主机和从机通讯。但是目前RT117X的EVK板没有放置LIN的收发器，SDK也没有相关LIN的示例代码和LIN协议栈支持，所以本示例目的是移植KW36工程中的LIN 2.1版本的代码到RT1176 EVK板子上，在硬件上通过跳线将LIN Master主节点和 Slave从节点的LPUART TX/RX线连接到FRDM-KW36板载的LIN收发器TJA1027上，分别实现LIN 2.1版本协议栈在Master和Slave节点的通讯功能验证，同时还需支持Auto Baud Rate自动波特率调整。为客户做二次开发或者移植用户自己的LINstack提供底层驱动，提高开发效率。 代码包软件   RT1176 LIN Master节点代码：RT1170_LIN_Porting_Demo_Master.7z RT1176 LIN Slave节点代码(支持自动波特率😞 RT1170_LIN_Porting_Demo_Slave_with_Auto_Baud_Rate.7z 配置FRDM-KW36板载LIN 收发器的代码: KW36_LIN_PHY_Board_Init.7z 硬件Setup   MIMXRT1170-EVK： 2pcs，分别用作LIN Master节点和Slave节点。 FRDM-KW36：2pcs， 分别用作Master节点的收发器，和 Slave节点的收发器 下图是系统连接，2块RT1170 EVK板分别和2块FRDM-KW36板通过Arduino接口连接在一起，然后将两块KW36之间的LIN收发器通过 J13 连接在一起，需要使用外部12V adapter为FRDM-KW36供电，否则板上的LIN收发器无法工作。特别强调的是，如果需要使能自动波特率检测的话，还需要将Slave节点RT1176 Arduino接口的J9-Pin2引脚连接到RT1176 Arduino接口的J9-Pin12引脚，作为Timer 脉冲捕捉的输入，即可完成系统硬件的setup。   软件Setup：   在以上硬件连接完成后，按照如下步骤下载对应软件： - Step1: 下载KW36_LIN_PHY_Board_Init.7z代码到两块FRDM-KW36板子上；  该代码中主要实现两个功能：第1个拉高板子的PTC5引脚，唤醒LIN收发器TJA1027。第2个将PTA18引脚配置成disable高阻状态。如果该引脚作为GPIO输出或者LPUART TX功能，会导致LIN slave回应数据出错(bit位丢失或者错误)。究其原因猜测应该是短路导致，当这个引脚作为GPIO输出或者LPUART TX功能，内部会有上拉，当RX1176 TX引脚输出Low时，由于电路上没有串联电阻(板子上使用的0Ω)，会导致引脚上出现大电流。尤其是第2个点，花费了很多时间去查这个问题，从波形去看，是有数据输出的，但只是数据不对，很具有迷惑性。当然如果客户是自己打的板子，板子上已经有LIN收发器就不需要这一步，直接跳到Step2即可。 - Step2: 下载RT1170_LIN_Porting_Demo_Master.7z代码到作为Master节点的IMRT1176-EVK板； - Step3: 下载RT1170_LIN_Porting_Demo_Slave_with_Auto_Baud_Rate.7z代码到作为Slave节点的IMRT1176-EVK板，如果需要使能自动波特率调整，需要配置宏linUserConfigSlave.autobaudEnable = true; 代码中默认是打开的。 实验结果   打开两个IMRT1176-EVK板串口，波特率配置115200，单击RT1176 Master节点上的按键SW7，便可以启动Master节点开始发送数据，通讯波形和串口打印信息如下两张图所示。   代码移植的几个难点   1. LIN通讯协议栈的调度流程的理解，包括Wakeup段，Break段，Sync段，PID段，Data段的状态切换和跳转，每个段的超时监测和错误处理，其核心思想有两个：一个在于LIN的RX引脚要不断去monitor TX引脚的状态，然后去切换状态机，具体调度的流程在后文会详细介绍，这里不展开。第二个是准确获取在每个段的定时器时间，尤其是超时超过一个overflow周期的情况，需要对timerGetTimeIntervalCallback0函数有理解。 2. 自动波特率调整功能的支持，该功能的原理是测量SYNC段的8个脉冲的脉宽，如果每个脉宽差异在2%范围内，再根据脉冲宽度去判断对应的波特率。在原来KW36的代码中是使用TPM的Overflow中断来作为计时，Edge中断来触发，而RT1176没有TPM，只能使用Qtimer (Qtimer功能上要更强于TPM)，但是不巧的是Qtimer不支持Overflow中断(参见芯片ERRATA 050194)，所以只能使用compare中断来实现类似的功能，而原有的计时定时计算都是基于overflow的，因此就需要对定时器部分的代码做大范围的更改。 应用中考虑到timerGetTimeIntervalCallback0函数在自动波特率调整时和超时监测处理时的一致性，最好使用同一个Timer的同一个channel，这就需要这个Timer既支持普通的定时中断模式，又支持input capture功能。对于TPM来说，是无法实现的因为两次在寄存器配置上时互斥的, 参见下图。幸运的是Qtimer支持这个feature，只是需要根据SDK代码做些配置 前面提到，需要QTimer支持input capture功能, 触发信号是LPUART_RX引脚的信号，需要硬件loop到Qtimer支持的硬件引脚上，对于KW36来说，只需要把这两个物理引脚连接在一起即可，但对RT1176来说, 只有这一步还不行，还需要对XBAR进行配置，将Qtimer的TIMER 1的触发引脚(合计有4个物理引脚)Link到QTIMER对应的Channel上，因为RT1176有4个QTimer，每个Qtimer有4个通道，标称的Qtimer trigger pin有4个，那具体哪个pin触发哪个QTimer的哪个通道，是需要配置的。如果客户没有使用过XBAR配置起来有难度，还好MCUXpresso config tool支持配置，可以简便的完成配置。示例代码和触发关系如下，如果实际硬件使用的物理引脚有区别，需要对应修改。 RT的XBAR功能非常强大，或许可以不使用外部的物理连线，直接将Qtimer的出发引脚的信号直接在内部Loop到LPUART_RX引脚，这样就更加灵活，此处只提供一个思路，不再进一步延伸。 IOMUXC_GPR->GPR15 = ((IOMUXC_GPR->GPR15 & (~(IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)))/*Mask bits to zero which are setting*/ | IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(0x00U) /*QTIMER4 TMR1 input select: 0x00U*/ | IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(0x00U) /*QTIMER4 TMR2 input select: 0x00U*/ ); 4. 在状态机切换和超时以及错误处理过程中，经常会看到两种模式Sleep模式和Idle模式，区别是什么呢？ LIN_LPUART_GoToSleepMode: 函数会关闭Break中断，RX接收中断，帧错误中断，保留RX边沿 中断; LIN_LPUART_GotoIdleState 函数会打开Break中断，RX接收中断，帧错误中断，关闭RX边沿中 断; 实际通讯波形   Master作为Subscribe角色时，发送Header，由Slave发送Respone Master作为PUBLIC角色时，同时发送Header，以及Respone 按照调度表依次发送LI0_lin_configuration_RAM数组定义的PID数据 static uint8_t LI0_lin_configuration_RAM[LI0_LIN_SIZE_OF_CFG]= {0x00, 0x30, 0x33, 0x36, 0x2D, 0x3C, 0x3D ,0xFF}; Qtimer准确读取wake up信号的脉冲宽度 Slave使能Auto baud rate后读取到的每个脉冲宽度数据 免责声明： THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND *ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, *INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUTNOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, ORPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY,WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE)

Introduction Background There is not an official data for PCIe latency and performance, while some customers pay attention to and request these data. This paper utilizes Lmbench lat_mem_rd tool and DPDK qdma_demo to test the PCIe latency and performance separately. Requirement 1) Plug Advantech iNIC (LX2160A) into LX2160ARDB. 2) Configure EP ATU outbound window at console. 3) Apply the patch to lmbench-3.0-a9, and recompile lmbench tool. 4) There is qdma_demo in iNIC kernel rootfs by default. Test Environment     PCIe Latency Overview   Direction Description Latency(ns) PCIe(Gen3 x8) – DDR read from EP to RC 900 PCIe – PCIe – DDR Read from EP to EP (through CCN-508) 1550 PCIe – PCIe – DDR Read from EP to EP (through HSIO NOC) 1500 Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App running at iNIC: Lmbench lat_mem_rd   # ./lat_mem_rd_pcie -P 1 -t 1m   PCIe Performance Overview    Direction Throughput (Gbps) PCIe EP to EP 50   Setup 1) LX2160ARDB 2) iNIC – PCIe EP Gen3 x8 with LX2160A 3) Test App : qdma_demo running at iNIC   $./qdma_demo -c 0x8001 -- --pci_addr=0x924fa00000 --packet_size=1024 --test_case=mem_to_pci Peer to Peer On LX2 Rev. 2      Products   Product Category NXP Part Number URL MPU LX2160A https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A LSDK software Layerscape Software Development Kit https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/layerscape-software-development-kit:LAYERSCAPE-SDK   Tools    NXP Development Board URL LX2160ARDB https://www.nxp.com/design/qoriq-developer-resources/layerscape-lx2160a-reference-design-board:LX2160A-RDB Advantech ESP2120 Card      

        S32G just support serial download a M7 image to run by internal rom codes, our S32G DS IDE have a flash tools to use this feature to burn the image to external device. So current image burn method will divide into 2 step: 1: burn a uboot into the external device by S32G DS flash tools. 2: reboot the codes with uboot and run with network to burn the linux image into external device.      which need two working place on manufacture line, and customer wish to have a one time on-line tools, which means we need use serial port to boot uboot directly but S32G rom codes do not support it.       We have a reference tools of S32V but which IP difference is big between on S32V and S32G, So we can not reuse it and have to develop a new one.       The development working include: 序号 开发工作 说明 开发者 1 开发 根据S32G的serial boot协议要求，开发PC端的串口工具来下载M7镜像 John.Li 2 开发 根据自定义协议要求，开发PC端的串口工具来下载A核Bootloader到SRAM中 John.Li 3 开发 根据自定义协议要求，开发M7镜像的串口接收与Checksum逻辑 John.Li 4 开发 修改M7镜像支持串口0 John.Li 5 开发 开发实现M7镜像的串口单字节同步收发函数 John.Li 6 开发 开发实现A53启动功能 John.Li 7 调试与Debug 调试解决串口接收乱码问题(Serial boot rom codes仍然在回送消息串口) John.Li 8 调试与Debug 提供 解决A核启动串口halt思路(Serial boot rom codes仍然占用串口) John.Li 9 调试与Debug 优化M7镜像，缩小大小 Tony.Zhang 10 调试与Debug 根据M7镜像和A核 Uboot在SRAM中的内存分配要求，重排M7镜像位置，避免冲突 Tony.Zhang 11 调试与Debug 在M7中初始化SRAM空间 Tony.Zhang 12 调试与Debug 在M7中设置SRAM可执行空间 Tony.Zhang 13 调试与Debug 调试解决由于cache没有及时回写导致的下载镜像错误的问题 Tony.Zhang 14 调试与Debug 集成，调优与文档 John.Li   Pls check the attachment for the doc/codes/binary release which include:    Release      |->M7: Linflexd_Uart_Ip_Example_S32G274A_M7: S32DS M7工程。      |->PC: s32gSerialBoot_Csharp: PC端的Visual Studio的C#的串口工具工程。      |->Test:      |    |-> 115200_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为115200      |    |-> 921600_bootloader.bin: S32DS M7工程编译出来的bin文件，波特率为921600      |    |->load_uboot.bat: 运行工具的批处理文件，运行成功后打开串口可以看到Uboot执行，默认使用的波特率是115299         |    |->readme.txt:其它测试命令 |    |->s32gSerialBoot.exe:编译出来的PC端串口工具 |    |->u-boot.bin: BSP29默认编译出来的u-boot.bin.      Product Category NXP Part Number URL Auto MPU     S32G274     https://www.nxp.com/s32g    

Overview The S12ZVH-REF-V1 is a reference design engineered for being a design base for starting an instrument cluster project, also it helps to reducing Automotive Cluster development time and maximizing engineering resources. Based on the 16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers, the S12ZVH-REF-V1 provides a production-looking design with impressive integration. The S12ZVH-REF-V1 reference design is not only provided as a hardware reference but also as a software and mechanical design. Block Diagram   Products Product Features S12ZVH MagniV Mixed-signal MCU  16-bit S12 MagniV® S12ZVH mixed-signal microcontrollers for instrument cluster.   Features Interfaces   LIN physical transceiver and connector CAN connector interfaced with MCUs CAN physical transceiver Components 1 x custom 160 segment LCD 1 x low-power piezoelectric speaker 4 x stepper motors 49 x LEDs used as telltales and backlights 6 x user buttons 2 x potentiometers S12ZVH The S12ZVH-REF-V1 does not include on-board programming/debugging circuitry; it requires an external programmer compatible with the BDM protocol. Files S12ZVH-REF-V1 Mechanical and Assembly files  S12ZVH-REF-V1 Reference Design Software (CW10.5) 

Demo      Features Detect fatigue using a camera via an algorithm based on optical absorption rate of facial blood vessels Efficient processing with up to 1.2MHz Quad ARM Cortex-A9 architecture with a NEON multimedia processing acceleration engine Video processing unit in i.MX 6Quad to record front camera video in H.264 format Face tracking algorithm to track the driver's head for a real driving use case   NXP Recommends i.MX6Q|i.MX 6Quad Processors|Quad Core

Built to automotive grade specifications, this Qi compliant wireless charging reference design charges up devices in the car. The devices can integrate into the dash or center console of car.     https://community.nxp.com/players.brightcove.net/4089003392001/default_default/index.html?videoId=4282648274001" style="color: #05afc3; background-color: #ffffff; font-size: 14.4px;" target="_blank   Features Wireless Charging Reference design for Automotive applications Integration into dash board or center console 5 Watts of power following Qi standard Near field Communication (NFC) Loop included   Featured NXP Products 5 Watt Wireless Automotive 5 Watt Wireless Industrial Links WCT-5WTXAUTO: Multi-Coil Wireless Charging Tr Block Diagram  

Demo This demo showcases the MAC57D5xx microcontroller rendering on a LVDS 1280x480 display for a full digital graphic instrument cluster and a Head-up Display on a secondary panel showcasing the warping capabilities of the microcontroller.       Single-chip instrument cluster solution with powerful graphics subsystem, including inline Head-Up Display warping functionality Dual-core ARM® Cortex®-A5/M4 for real-time and application processing and additional Cortex-M0+IOP core Cryptographic Services Engine, tamper detection and password protection for Flash memory and JTAG   Links Ultra-Reliable Multi-Core ARM-based MCU

MC07XS6517 and MC17XS6500 single ICs provide comprehensive, cost-effective solutions for halogen, industrial lighting, LEDs, xenons, main switches and DC motor control. The eXtreme switch products are the latest achievement in DC motors and industrial lighting drivers. They belong to an expanding family to control and diagnose various types of loads, such as incandescent bulbs or light emitting diodes (LEDs), with enhanced precision. The products combine flexibility through daisy chainable SPI at 5.0 MHz, extended digital and analog feedbacks, which supports safety and robustness. This new generation of our high-side switch products family facilitates electronic control unit designs supported by the use of compatible MCU software and PCB footprints, for each device variant.     Features Operating voltage range of 7.0 V to 18 V, with sleep current <5.0 μA 5.0 MHz 16-bit SPI control of overcurrent profiles, channel control including 8-bit PWM duty-cycles, output -ON and -OFF open load detections, thermal shutdown and pre-warning, and fault reporting Output current monitoring with programmable synchronization signal and supply voltage feedback Programmable overcurrent trip levels Enhance output current sense with programmable synchronization signal and battery voltage feedback Watchdog and limp home mode External smart power switch control -16 V reverse polarity and ground disconnect protections Compatible PCB foot print and SPI software driver among the family Programmable Penta high-side switches Wide range diagnostic, current sensing and very low Rdson Up to 30% smaller PCB and 50% lower component count MC07XS6517 and MC17XS6500 eXtreme Switch applications include halogen, industrial lighting, LEDs, xenons, main switches and DC motor control   Featured NXP Products MC17XSF500: MC17XSF500, Penta 17 mOhm High Side Switch - Data Sheet MC07XSF517: MC07XSF517, Triple 7.0 mOhm and Dual 17 mOhm High Side Switch - Data sheet Block Diagram  

Demo NXP has developed a whole vehicle multi-layered approach to vehicle security.  This demo will demonstrate the NXP security products in action, and show the 4 steps to securing an automotive electrical architecture, and how these 4 steps provide a barrier to the recent public vehicle hacks.   Features: Try to hack a typical automotive network. Enable and disable NXPs security layers to see how they work to protect the vehicle. Demonstrates various NXP security IP, including: A700x family secured MCUs, MPC5748G connected gateway and HSM/CSE security engines. ___________________________________________________________________________________________________________________________   NXP Recommends MPC5748G|NXP A700x|NXP   ___________________________________________________________________________________________________________________________      

  Demo Owner Mike Stanley   Tire Pressure Monitoring Systems (TPMS) help drivers with precise direct tire pressure measurement by providing individual tire readings – including the spare. NXP's world’s smallest, lowest-power, with highest memory for customer use TPMS is highly integrated with a pressure sensor, temperature sensor, accelerometer, MCU and a transmitter. Watch Mike Stanley explain the pressure sensor readings, temperature sensor display and the accelerometer/motion readings. These readings are time based periodic measurements where the data is given as an output to the driver.   Features Simulation that portraits the TPMS as if it were inside the vehicles tires and sending reports to the vehicle's display unit about tire pressure Module has the following: Pressure sensor, accelerometer, temperature sensor, low-frequency radio, Microcontroller   Featured NXP Products FXTH87 product page FXTH87 Fact Sheet Links Tire Pressure Monitoring Sensors Pressure Sensors Block Diagram  

本文说明如何检查S32DS Flash Tool的默认波特率，以便确认下载相关的失败问题，以及如何解决。 目录 1    背景与资料说明... 2 1.1  背景说明... 2 1.2  所需资料说明... 4 2    S32G波特率设置说明... 4 3    检查FlashTool Target image的默认波特率... 6 3.1  运行FlashTool下载Target image. 6 3.2  连接lauterbach检查波特率相关配置... 6 4    G2的检查情况... 8 5    如何解决此问题... 9  

this doc explain the S32G PCIe HW design checkpoints and How to debug HW issue with SW. 主要包括：         1：S32G PCIe硬件设计说明。         2：如何根据硬件设计配置软件。         3：如何根据软件现象debug硬件连接问题。         4：一个连接PCIe外设的demo. 目录 1    背景与资料说明... 2 1.1  背景说明... 2 1.2  所需资料说明... 2 2    PCIe硬件设计说明... 2 2.1  S32G PCIe能力... 2 2.2  S32G PCIe原理图设计... 4 2.3  S32G PCIe设计说明... 8 2.4  S32G PCIe硬件bring up. 9 3    PCIe 软件说明... 9 3.1  软件配置说明... 9 3.2  PCIe uboot初始化流程... 12 3.3  PCIe Linux初始化流程... 19 4    硬件连接错误的软件表现示例... 21 4.1  时钟配置错误... 21 4.2  硬件连接错误... 23 5    RDB3连接PCIe设置Demo. 25 5.1  硬件说明... 25 5.2  Uboot配置... 26 5.3  内核打印... 27 5.4  内核sys文件夹... 36  

Some common issues of HSE-H based on S32G are summarized. Hope it can help you understand the known issues of HSE-H. The issue contents have been listed to facilitate finding the topic you care about. Please refer to the attachment for details. Thank you.

FAST BOOT FOR lx2160 IN adas •Objective To speed ​​​​up bringup of LX2 chip-based systems •Pain Points to Address The bringup time is much longer than 3s, which is very sensitive in ADAS systems or time-sensitive systems. •Value Proposition / Key Features The guide can help customers shorten uboot time from 5s to less than 1.5s, saving more than 70% bootup time. •Deliverables Demo based on LX2160ARDB board. Reference codes and patches. Guide for Fast boot document. Fast boot 广泛用于嵌入式设备，现以lx2160ardb板为例进行相关探索。 启动流程： 优化思路： 1.适当提高FSPI时钟速率 diff --git a/lx2160asi/flexspi_divisor_32.rcw b/lx2160asi/flexspi_divisor_32.rcw index 422139c..0f8d5c9 100644 --- a/lx2160asi/flexspi_divisor_32.rcw +++ b/lx2160asi/flexspi_divisor_32.rcw @@ -7,8 +7,10 @@ * Modify FlexSPICR1 register, to increase FlexSPI clock closer to 50MHz, * with divisor value as 32. * => 750 * 2 / 32 ==> 46.875MHz + *write 0x1e00900,0x00000013 + * 0f -12 =125M */ .pbi -write 0x1e00900,0x00000013 +write 0x1e00900,0x0f .end ​ 2.关键路径优化 固化spd参数 固化ddrc参数 BL33 裁剪 详细patch和测试结果参考附件。

本文说明在S32G2 RDB2板上实现LLCE to PFE Demo的搭建过程。本Demo目前包括：  CANtoEth：CAN0发送，用硬件回环到 CAN1接收，然后通过PFE_EMAC1， 再通过RGMII接口发出。  CANtoEth：CAN0发送，用硬件回环到 CAN1接收，然后通过PFE_EMAC1， 再通过SGMII接口发出。  EthtoCAN：PC通过PFE_EMAC1的 RGMII发出，接收到CAN1，再硬件 回环到CAN0  CANtoCAN Logging to Eth: CAN0发 送，用硬件回环到CAN1接收，然后 通过PFE_EMAC1，再通过SGMII接 口发出,同时LLCE内部硬件把CAN1 再发送到CAN15_TX，再用硬件回环 到CAN14_RX 软件版本为 RTD3.0.0+LLCE1.0.3+PFE0.9.6/0.9.5。

This doc explain how to optimize the Linux boot time, Contents as follows: 目录 1 默认BSP28 Linux内核的启动时间分析和优化方向 ..... 2 2 UBoot的优化 .............................................................. 3 2.1 缩小Uboot的DTS尺寸 ............................................ 3 2.2 缩小Uboot的尺寸 .................................................... 4 2.3 去掉等待3S输入时间 .............................................. 4 2.4 配合内核修改的Uboot参数 ..................................... 4 2.5 关闭串口调试信息 .................................................. 5 2.6 MMC read的方法来读取内核和DTB ....................... 5 3 Kernal的优化 ............................................................. 5 3.1 DTB中去掉不用的驱动和代码 ................................. 5 3.2 内核中去掉不用的平台与驱动及相关代码 ............... 6 3.3 内核中去掉不用功能，缩小内核大小 ...................... 7 3.4 去掉initramfs支持 ................................................... 7 3.5 关闭调试信息 .......................................................... 7 3.6 提前eMMC驱动加载时间 ........................................ 7 3.7 将Kernel与DTB打包在一起..................................... 8 4 Rootfs+应用程序的优化 ............................................. 8 5 最终全部启动时间比较 ............................................. 12

This doc expain how to use eMMC from user space, contents as follows: 目录 1 eMMC的分区情况 ...................................................... 2 2 S32G+BSP29上默认的eMMC启动 ............................ 3 2.1 eMMC硬件设计 .................................................. 3 2.2 eMMC的镜像烧写办法与启动 ............................. 6 2.3 增加MMC内核测试工具 .................................... 10 3 eMMC GP功能的测试 .............................................. 10 3.1 eMMC GP功能的说明 ....................................... 10 3.2 eMMC GP功能的测试 ....................................... 11 4 eMMC RPMB功能的测试 ......................................... 13 4.1 eMMC RPMB功能的说明 ................................. 13 4.2 eMMC RPMB功能的测试 ................................. 15

This doc explain how to use S32G design studio and SDK, contributed by Gary.Yuan yuan.yuan@nxp.com.