Register Protection for MPC5746C These are the Modules on which I am implementing Locking mechanism under Register Protection for MPC5746C. 0xFFFB0140, /* CMU------------*/ 0xFFFB0040, /* FXOSC----------*/ 0xFFFB0180, /* MC_CGM --------*/ 0xFFFB8000, /* MC_ME ---------*/ 0xFFFA8000, /* MC_RGM --------*/ 0xFFF50000, /* MEMU_0 -------*/ 0xFFFB0080, /* PLLDIG --------*/ 0xFFFA0400, /* PMCDIG --------*/ 0xFFFC0000, /* SIUL2 ---------*/ 0xFFFB0100, /* SXOSC ---------*/ 0xFFF9C000 /* LPU_CTL -------*/ Sample 1: (0xFFFB0000, offset - 0x4, 32-bit protection) Register: Matches ME_MCTL (mode control register, 32-bit protection, offset 0x4 per Table 77-5). Base Address: 0xFFFB0000. Protection Size: 32 bits (all four bytes are protected). Calculations Normal Address: base + offset = 0xFFFB0000 + 0x4 = 0xFFFB0004 Mirrored Address (Area 3): base + 0x2000 + offset = 0xFFFB0000 + 0x2000 + 0x4 = 0xFFFB2004 Soft Lock Bits Address (Area 4): Offset in Area 4: offset/4 = 0x4 / 4 = 0x1. Address: base + 0x3800 + offset/4 = 0xFFFB0000 + 0x3800 + 0x1 = 0xFFFB3801. For a 32-bit register, all four SLBs (SLB0–SLB3) control the four bytes (e.g., 0x4 to 0x7). Soft Locking Option 1: Write to Mirrored Address: Write a 32-bit value to 0xFFFB2004 (e.g., 0x80000000 to initiate a mode transition; refer to MC_ME chapter for valid values). This updates ME_MCTL at 0xFFFB0004 and sets SLB0–SLB3 in the SLBRn register at 0xFFFB3801. Example: *(volatile uint32_t *)0xFFFB2004 = 0x80000000; Option 2: Direct SLB Write: Write to 0xFFFB3801 to set SLB0–SLB3. Write 0xFF (WE0–WE3=1, SLB0–SLB3=1) to lock all four bytes. Example: *(volatile uint8_t *)0xFFFB3801 = 0xFF; Unlocking Write 0xF0 to 0xFFFB3801 (WE0–WE3=1, SLB0–SLB3=0) to clear SLB0–SLB3, unlocking the register. Example: *(volatile uint8_t *)0xFFFB3801 = 0xF0; Hard Locking Write 0x00000001 to 0xFFFB3FFC to set GCR.HLB, locking SLBs until reset. Example: *(volatile uint32_t *)0xFFFB3FFC = 0x00000001; Below in an example of register set whose all 4 address set are enable and can be R/W. Below in an example of register set whose Base + offset & Mirror addresses are enabled and can be R/W and other addresses can’t be set. This poses a serious issue as SLB bits confirms soft locking and GCR bits are set to implement hard lock. For All MC_CGM caped registers I can find the same problem. What could be the reason for these different behavior. Some addresses can be modified and changed other are reserved. Re: Register Protection for MPC5746C Hello,
if I Hard lock any one module , all other modules are getting hard locked automatically, which raises issue in Low power mode. since I do not want FXOSC/SXOSC and CMU to be hard locked here.
The register protection is applied Pbridge.
And on the PBRIDGE is the MC_CGM module:
Which have then mapped peripherals under MC_CGM. Looks like you will need to use SLB instead of HLB to solve this.
As HLB will lock whole MC_CGM.
Best regards,
Peter Re: Register Protection for MPC5746C Hi Peter , Thank you for the help. I can configure Soft lock and monitor SLB for all modules now. I have another question regarding Hard Lock GCR bit. According to your explanation for all the MCCGM capped modules which are CMU,FXOSC,SXOSC, PLLDIG and MCCGM shall have one common base address , that is 0xFFFB0000. now according to section 77.1.1 Register protection configuration, the NOTE talks about operations in Low power mode. As I said , having the same base address , if I Hard lock any one module , all other modules are getting hard locked automatically, which raises issue in Low power mode. since I do not want FXOSC/SXOSC and CMU to be hard locked here. is there any way around this problem. Thanks and regards Re: Register Protection for MPC5746C Hello,
Here is the result of SLB for
CMU_LFREFR 32 - addresses base and offset
Base for CGM module is 0xFFFB_0000
CMU offset is 0x140
CGM LFREFR offset is 0x14C from module base
I set SLB for CMU_LFREFR via write to mirror
Best regards,
Peter Re: Register Protection for MPC5746C Hi , This is also not working . CMU_LFREFR 32 Offset 0xCh Protected size - 16 (Bytes 2 and 3) 0xFFFB0000, /* CMU----------*/ Base address -0xFFFB000C Mirror address -0xFFFB200C SLB - 0xFFFB3803 GCR - 0xFFFB3FFC Re: Register Protection for MPC5746C Hello,
Looking at simple test: MC_CMU - CSR
Base Address - 0xFFFB014C - This is offset address. Not Base.
Base for MC_CMU module is 0xFFFB 0140.
Mirror Address -0xFFFB214C
Would be base +offset + mirror
SLB -0xFFFB3943
Take as base address of whole CGM as present in ref manual:
So calculations are:
0xFFFB0000 + 3800 + position of SLB
GCR - 0xFFFB413C
Same as above
0xFFFB0000+3FF0
Best regards,
Peter
Re: Register Protection for MPC5746C Hi Peter , here are some samples where SLB and GCR are not working. can You please check this addresses and confirm if they show different behavior. if not then what could be the problem with these modules ? 1. MC_CMU - 0xFFFB0140 - { MODULE_CMU, 0xC,REG_SIZE_16}, CMU_LFREFR Base Address - 0xFFFB014C Mirror Address -0xFFFB214C SLB -0xFFFB3943 GCR - 0xFFFB413C 2. MC_CMU - 0xFFFB0140 { MODULE_CMU, 0x18,REG_SIZE_32}, CMU_MDR Base Address - 0xFFFB0158 Mirror Address - 0xFFFB2158 SLB - 0xFFFB3946 GCR - 0xFFFB413C 3. PLLDIG 0xFFFB0080 - { MODULE_PLLDIG, 0x20, REG_SIZE_16}, PLLDIG_PLLCR Base Address - 0xFFFB00A0 Mirror Address - 0xFFFB20A0 SLB - 0xFFFB0F5D GCR - 0xFFFB407C 4. PLLDIG 0xFFFB0080 - { MODULE_PLLDIG, 0x28,REG_SIZE_32}, PLLDIG_PLLDV Base Address - 0xFFFB00A8 Mirror Address - 0xFFFB20A8 SLB - 0xFFFB388A GCR - 0xFFFB407C 5. PMCDIG 0xFFFA0400 - { MODULE_PMCDIG, 0x0,REG_SIZE_32}, Base Address - 0xFFFA0400 Mirror Address - 0xFFFA2400 SLB - 0xFFFA3C00 GCR - 0xFFFA43FC 6. PMCDIG 0xFFFA0400 -{ MODULE_PMCDIG, 0x10,REG_SIZE_32}, Base Address - 0xFFFA0410 Mirror Address - 0xFFFA2410 SLB - 0xFFFA3C04 GCR - 0xFFFA43FC Re: Register Protection for MPC5746C Hello,
I have checked the PREG_PROT and it behave like described in reference manual:
on ME_CGM register SC_DC0:
Base : 0xFFFB0000 + Offset 7E8
Mirror: 0xFFFB07E8
= Base (0xFFFB0000) + Offset(7E8) + Mirror (0x2000)
In the example I have locked the SC_DC0 form ME_CGM module by Soft lock.
Here is the breakdown:
Area 4: is 1.5 KB and holds the Soft Lock Bits, one bit per byte in area 1. The four Soft Lock Bits associated with one module register word are arranged at byte boundaries in the memory map. The Soft Lock Bit registers can be directly written using a bit mask.
So you have to divide the area of Soft lock bits by 8 to see corresponding SLB settings.
Base (of module) + 3800 + (one bit per byte of area 1)
For Hard lock bit it is one for whole module.
Area 5 is 512 bytes large and holds the configuration bits of the protection mode. There is one configuration hard lock bit per module that prevents all further modifications to the Soft Lock Bits and can only be cleared by a system reset once set. The other bits, if set, will allow user access to the protected module.
Base (of module) 0xFFFB0000 + Offset 3FFC
As GCR is at end of area 5.
Best regards,
Peter Re: Register Protection for MPC5746C Hello,
I will test it and come back to you ASAP.
Best regards,
Peter
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