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S32K358 上的硬件触发信号出现问题 你好,恩智浦、 我在 S32K358 自定义板中的硬件触发信号功能方面遇到了问题。 我在 matlab 2024 中使用 MBDT v1.5。 为了有 3 个 pwm 信号,我已经配置了 EMIOS_1 的 3 个通道(ch_9、ch_11、ch_19),我把它们配置为 EMIOS_PWM_IP_MODE_OPWMT 以启用触发信号生成。 在 AdcHwTrigger 中,我配置了 3 个带有相应的 BTCU 源的硬件触发信号和 3 个 ADC_1 组,每个组都有一个注入信道。 这些频道也被相应的 Hw 触发信号 锁存。ADC_1 采用中断方式工作。 我还正确配置了平台 ISR 和 MCU 时钟。 在 simulink 模型中,我在状态流图每隔 50 毫秒调用一次的子系统中启用了通知和硬件触发信号。一旦转换了 adc 频道,应用程序就会调用 Interrupt Hw 回调,在该回调中禁用该组的通知和相对的 Hw 触发信号。 这是为 3 组中的每一组进行的。 这样,我就有了 3 个同时启动、周期相同(我的情况是 200Hz)的 pwm 信号,因此,根据我在 RM(64.3.1.9)上读到的信息同步触发信号的优先级) 我预计 BCTU 会同时接收 3 个触发信号,并对连接到最高优先级触发信号(我的例子为 BCTU_EMIOS_1_9)的 adc 通道进行转换,而其他(BCTU_EMIOS_1_11 和 BCTU_EMIOS_1_19) 则处于等待状态,等待轮到他们访问 ADC_1 并进行转换。 当执行与 BCTU_EMIOS_1_9 触发信号相关的转换时,我预计他的触发信号将在中断回调中被禁用,第二个待处理触发信号(在我的例子中为 BCTU_EMIOS_1_11)开始转换... 不幸的是,我看不到这种行为... 我只看到它对连接到最高优先级触发信号(在我的情况下为 BCTU_EMIOS_1_9)的 adc 进行转换,而忽略了其他的。 我是做错了什么还是误解了什么?如何才能实现上述行为描述? 附上 mex 文件 谢谢, Simon
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IP Camera live video displaying is hanging after some time using VPU of I.MX8QM board Hi, I am interfacing IP Camera to I.MX8QM board and I am using RTSP protocol. IP camera is h.264 encoded, for decoding in I.MX8QM board, I am doing in both CPU & VPU. In CPU case lot of latency is adding but video is not getting hanged but in VPU case latency is not there but after some time Video getting hanged. CPU(Software decoding): gst-launch-1.0 rtspsrc protocols=udp latency=0 drop-on-latency=true location=rtsp://bm904285:[email protected]:554/stream1 ! rtph264depay ! h264parse ! avdec_h264 ! queue max-size-buffers=1 leaky=downstream ! videoscale ! video/x-raw,width=640,height=360 ! videoconvert ! autovideosink sync=false VPU Decoding: gst-launch-1.0 rtspsrc protocols=udp latency=200 drop-on-latency=true udp-reconnect=true timeout=5000000000 location=rtsp://bm904285:[email protected]:554/stream1 ! rtph264depay ! h264parse config-interval=1 disable-passthrough=true ! queue max-size-buffers=0 max-size-bytes=0 max-size-time=0 ! v4l2h264dec capture-io-mode=4 output-io-mode=4 extra-controls="capture,buffer_count=12" ! queue max-size-buffers=8 leaky=downstream ! imxvideoconvert_g2d ! video/x-raw,width=1024,height=768 ! waylandsink sync=false qos=false Please helpus to resolve this Issue.   Re: IP Camera live video displaying is hanging after some time using VPU of I.MX8QM board Hello, For Input resolution 640x360, both software & Hardware decode is working but for 2560x1440 resolution decoding not working properly. What is the maximum capable H.264 decoder resolution. In Summary it is mentioned as 4K@30 but in simplified block diagram mentioned as "Mult-format Decode - 1080P@60". Please confirm. Re: IP Camera live video displaying is hanging after some time using VPU of I.MX8QM board Hello, The video hanging issue with VPU decoding is likely related to buffer handling in your GStreamer pipeline. When using hardware acceleration, proper buffer management is critical for maintaining stable video playback. Here are recommendations to resolve the hanging issue: 1. Modify your VPU decoding pipeline with these adjustments: ``` gst-launch-1.0 rtspsrc protocols=udp latency=0 drop-on-latency=true udp-reconnect=true timeout=5000000000 location=rtsp://USERNAME:PASSWORD@IP_ADDRESS:554/stream1 ! rtph264depay ! h264parse config-interval=1 ! queue ! v4l2h264dec capture-io-mode=4 output-io-mode=4 ! imxvideoconvert_g2d ! waylandsink sync=false ``` 2. Key changes to implement: - Use capture-io-mode=4 and output-io-mode=4 for dmabuf zero-copy operation - Replace queue max-size parameters with a simpler queue element - Use imxvideoconvert_g2d instead of plain videoconvert for hardware accelerated scaling - Set sync=false on waylandsink to prevent frame dropping 3. If the issue persists, try reducing the resolution or framerate from the camera source to reduce processing demands. 4. Ensure your system has the latest BSP updates as some VPU-related issues have been addressed in newer releases. The main difference between CPU and VPU decoding performance is that software decoding buffers more frames (causing higher latency but more stability), while hardware decoding processes frames more quickly but requires proper buffer management to prevent freezing. Regards Re: IP Camera live video displaying is hanging after some time using VPU of I.MX8QM board For Input resolution 640x360, both software & Hardware decode is working but for 2560x1440 resolution decoding not working properly. What is the maximum capable H.264 decoder resolution. In Summary it is mentioned as 4K@30 but in simplified block diagram mentioned as "Mult-format Decode - 1080P@60". Please confirm. Re: IP Camera live video displaying is hanging after some time using VPU of I.MX8QM board Hello, Please provide maximum capable H.264 decoder resolution. Thanks & Regards, Mallikarjuna.
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S32K344MINI-EVB Board Hello, I recently purchased the S32K344MINI-EVB evaluation board, but I noticed that the schematics and related hardware documentation are not yet available on the NXP website. Could you please let me know when the schematics, hardware design files, user manual, and any other supporting documents for this board will be published? If they are already available elsewhere, I would appreciate it if you could point me to the correct location. Thank you for your assistance. Re: S32K344MINI-EVB Board Hello @muab , Unfortunately, the hardware related documentation for this board has not been officially released yet. If you have access to such board, please double-check this request with your assigned Field Application Engineer (FAE)—either from NXP or your distributor. If you do not yet have a contact, we recommend reaching out to your local distributor for assistance. I apologize for any inconvenience. Best regards, Pavel Re: S32K344MINI-EVB Board Hi @muab , I see now the documentation is available on NXP website: https://www.nxp.com/webapp/Download?colCode=S32K344MINI-EVB-DESIGN-FILES
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[ABUSE] Post By: @JohnKlug / Board: imx-processors / Reported by: exizotk exizotk has reported the post Could not invoke dnf for external kernel module in Yocto kirkstone posted by @JohnKlug for the following reasons: Reason: Something else Details: https://www.isupportveterans.org/node/3042"> http://hubram.cz/content/pharmacy-online-0"> http://fictioneer.org/content/pharmacy-online-10"> http://onlyforsalebyowner.com/for-sale-by-owner-homes/mt/39"> https://obzorpoker.info/forum/pharmacy-online-3"> https://www.tundus.hu/gyik/pharmacy-online"> http://xn--80aah2bgapnqg.xn--p1ai/story/pharmacy-online"> http://onlyforsalebyowner.com/for-sale-by-owner-homes/mt/39"> http://old-bxl.jeunescathos.org/fr/content/pharmacy-online-35"> http://ysrp.bnl.bm/review/pharmacy-online-3"> https://www.globalrealtor.co.in/node/4201"> https://www.castnblastadvisor.com/outfitters/pharmacy-online-2"> https://www.geofak85.ru/pharmacy-online-2"> http://ph-ed-plus.nspu.ru/article/17928"> http://leninstatues.ru/photo/11958/pharmacy-online"> https://www.e123.hk/zh-hant/e-center/personal-wall/81576/933272"> https://www.siriuspup.com/breeders/pharmacy-online-1"> https://www.07acg.com/node/42611"> https://www.torontopersians.com/ads/pharmacy-online-11"> https://www.geofak85.ru/pharmacy-online-2"> https://rahuldolas.com/forum/general-discussion/topic/721/pharmacy-online"> https://oregonweddingday.com/your-couple-name-2379"> https://www.horecascout.nl/vacatures/5449/pharmacy-online"> http://alabasirah.com/node/8262"> https://facultypage.com/node/470"> https://superbia.lgbt/tridentlifting/1759116532"> https://www.castnblastadvisor.com/outfitters/pharmacy-online-2"> https://backend.dawahnigeria.com/audit/304772"> http://www.batshaw.qc.ca/fr/node/169"> https://mnbride.com/your-couple-name-2345"> https://www.drupalcamp.cr/es/node/4816"> https://californiaweddingday.com/your-couple-name-2353"> https://dev.worldwar1luton.com/forum-topic/pharmacy-online-12"> https://masters.adminskiracing.com/node/413297"> https://www.heilpraktikerausbildung24.de/node/124360"> https://enki.ua/advert/16929"> https://dev.worldwar1luton.com/forum-topic/pharmacy-online-12"> http://ysrp.bnl.bm/review/pharmacy-online-3"> https://www.onlyhomebuyers.com/for-sale-by-owner-homes/ok/83"> https://museusvalenciapre.grupotecopy.es/en/node/3706"> Post link: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/m-p/1627964#M203740 Post author: @JohnKlug | Email Author Reported by: exizotk | Email Reporter The reported post has 2 replies.
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[滥用] 发布者:@JohnKlug /板:imx-processors/举报人:eezqhca eezqhca 报告了 @JohnKlug 发表的帖子 Could not invoke dnf for external kernel module in Yocto kirkstone ,原因如下: 原因: 详情: < a href="https://www.castnblastadvisor.com/outfitters/pharmacy-online-5"> https://carros-usados.us/pharmacy-online-13"> https://www.trustcirclenetworks.org/issues/2216"> < a href="https://dev.beautynbrushes.com/services-provided/feed-braids-maroonimmortalep-0"> http://www.batshaw.qc.ca/fr/node/163"> < a href="http://alabasirah.com/node/8265"> https://www.availcalendar.com/calendar/25592"> https://californiaweddingday.com/your-couple-name-2365"> https://www.vgame.ca/node/46822"> https://www.aairlab.com/IDev/?q=node/260"> < a href="http://old.jeunescathos.org/fr/content/pharmacy-online-18"> https://golemobuchino.com/forumi/mahali/obshcho/pharmacy-online-8"> https://www.cableman.ru/node/84350"> http://polden.info/story/pharmacy-online-10"> < a href="https://www.ziveknihy.sk/audiokniha/pharmacy-online-1"> https://www.drupalcamp.cr/es/node/4820"> https://www.globalrealtor.co.in/node/4222"> < a href="http://sp-journal.ru/article/19183"> https://www.player1.app/team/post/190021839/1234"> https://www.turstory.ru/forum/turizm/splav/193132.html"> https://www.isupportveterans.org/node/3043"> http://hubram.cz/content/pharmacy-online-4"> < a href="http://www.gradspot.com/qa/pharmacy-online-4"> https://theanubianwar.com/node/6399"> http://www.le-cercle-des-sourires.fr/evnementmultisessions/pharmacy-online-0"> < a href="https://www.drupalcamp.cr/es/node/4820"> https://reflexologie-cerilly.fr/en/node/4250"> https://theanubianwar.com/node/6399"> https://www.spinsheet.com/racing-team-log/pharmacy-online-1"> http://alabasirah.com/node/8265"> https://reflexologie-cerilly.fr/en/node/4250"> https://www.geofak85.ru/pharmacy-online-0"> http://lsdsng.com/node/4266"> < a href="https://wibride.com/your-couple-name-2390"> https://theanubianwar.com/node/6399"> https://neweddingday.com/your-couple-name-2377"> https://sitepe.iiec.unam.mx/node/6205"> https://hetnieuweteamwerken.be/forums/forum/pharmacy-online-9"> https://app.feizufenqi.com/fp/content/pharmacy-online-9"> https://www.danduo168.com/en/artworks/692/pharmacy-online-4"> 发布链接: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/m-p/1627964#M203740 帖子作者 @JohnKlug|Email Author 报告人:eezqhca |Email Reporter 报告的帖子有 2 个回复。
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[乱用] 投稿者: @JohnKlug / ボード: imx-プロセッサ / 報告者: ynaxspoe ynaxspoe は、 @JohnKlug が投稿した 「Could not invoke dnf for external kernel module in Yocto kirkstone」という 投稿について、以下の理由で報告しました: 理由:嫌がらせ 詳細: 投稿リンク: https://community.nxp.com/t5/i-MX-Processors/Could-not-invoke-dnf-for-external-kernel-module-in-Yocto/mp/1627964#M203740 投稿者: @JohnKlug |メール著者 報告者: ynaxspoe |メールレポーター 報告された投稿には 2 件の返信があります。
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MCX-A53x Preliminary Documentation Dear Siemens Team, please find here the following documents: preliminary Datasheet pin list preliminary Reference Manual You can find details of features supported by the 10base-T1S DPHY inside the preliminary Reference Manual at the relevant section. IMPORTANT NOTICE: please bear in mind all documentation attached here is preliminary, subject to change, with missing information and likely containing mistakes. Thank you    Marco
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Brake Resistor in the inverter board Devkit MotorGD Hello NXP team, I hope this email find you well, I want to ask about the MOSFET connected to the Brake Resistor Terminal in the inverter board Devkit MotorGD as shown below. I find that, in its data sheet, its gate needs 10 V to drive the MOSFET, so how to provide such voltage from the microcontroller board MPC5744P to drive this MOSFET to operate the brake resistor. When I tried to drive it using 5V, its voltage dropped when connecting a brake resistor and it can't switch on and off.   Re: Brake Resistor in the inverter board Devkit MotorGD Hello Peter, -By "its voltage," I mean the MOSFET's gate voltage. The voltage on the pin G7 from the MCU board, which will be connected to the gate of the MOSFET on the inverter board, is nearly 5V, but when attaching the MCU board (MPC5744P) to the inverter board (DevkitMotorGD), even before connecting a brake resistor, the voltage of the pin G7 drops to half the value (around 2.5V), and then when connecting the brake resistor, this voltage can't drive the gate off the MOSFET, I think. -Regarding the value of brake resistance that I used, I used several resistances as shown below  - BTW, I intend to use the brake resistor as a dump load for the machine that will work as a generator Best Regards,  Ahmed Re: Brake Resistor in the inverter board Devkit MotorGD Hello, There is level shifter - by deafult set to 3.3V. Could you check if you have it at 5V? The selection of the brake resistor also depends on the power rating of the resistor. The smaller the resistance, the higher the power rating needs to be. It shouldn’t be too small because a large current can flow very quickly and destroy it. You also need to check and consider the power rating and maximum current of the MOSFET, because the current will flow through it as well, and it’s relatively weak in a small package (SOT-23). There are a few amps there… According to the SOA, you can go somewhere in the range of ±5 A, but I’m not sure if such a small package can dissipate heat fast enough for that current. If you want to use some other load instead of a brake resistor, it’s the same story. Best regards, Peter
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How to debug HSE firmware RAM code An exception is occurring in the HSE firmware. The HSE appears to load code into RAM and execute it; however, an exception is raised while the RAM code is running. Why is this exception occurring, and how should I proceed with debugging? The attachment contains the register dump and exception details captured at the time of the fault. Re: How to debug HSE firmware RAM code It does not seem to be code executed fro SRAM as it reports different PC address. Rather you exception handlers in SRAM
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iMX8MM Evk(HABv4) のセキュアブート こんにちは@Harvey021 現在、私は iMX8MM evk ボードに取り組んでおり、HABv4 を使用したセキュア ブートを実装しています。私は iMX Linux ユーザーズ ガイド (IMXLUG) の「セキュア ブートのための自動イメージ署名」に従って、必要なキー、証明書、SRK テーブル/ヒューズを生成しました。 しかし、これらのハッシュを SoC の SRK_HASH eFuse フィールドに書き込む必要があるため、これらのキーを使用してイメージに署名する方法については疑問があります。 添付の文書を確認して、文書に記載されているプロセスでこれらのキーを使用してイメージに自動的に署名CANるか、またはイメージに署名するために他のプロセスに従う必要があるかを明確にしていただけますか? よろしくお願いいたします。 マノジ・クマール Re: Secure boot on iMX8MM Evk(HABv4) こんにちは@Manoj_Kumar ドキュメント内のプロセスは問題ないようです。 キーをパスに入れて指定すると、ガイドに従ってビルドするだけでイメージが署名されます。 SRKハッシュヒューズのプログラム方法の詳細については、ガイドを参照してください。 よろしくお願いいたします。 Harvey
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当预分频器设置的值与 KPWM_Presca 不同时,IMXRT1062 上的 PWM 捕获已停止 您好, ,我遇到了一个问题,在配置四个 PWM 外围设备中任何一个的时钟分频器时,如果使用的值不是 kPWM_Prescale_Divide_1,则所选 PWM 外围设备的计数器根本不起作用。 我使用的是 imxrt1062 处理器和 MCUXpresso IDE v11.9.1 ,希望你们能尽快支持我。 下面是我配置和初始化 PWM 外围设备的代码片段。 静态 void pwm_init(void) { pwm_config_tpwmConfig; pwm_input_capture_param_tcaptureConfig; pwm_fault_param_tfaultConfig; /* 读取 PWM 默认配置 */ PWM_GetDefaultConfig(&pwmConfig); pwmConfig.时钟源= kPWM_BusClock; pwmConfig.预标度= kPWM_Prescale_Divide_2; pwmConfig.配对操作= kPWM_Independent; pwmConfig.初始化控制= kPWM_Initialize_LocalSync; pwmConfig.重载逻辑= kPWM_ReloadImmediate; pwmConfig.重新加载选择= kPWM_LocalReload; pwmConfig.重载频率= kPWM_LoadEveryOportunity; pwmConfig.强制触发= kPWM_Force_LocalSync; pwmConfig.启用调试模式= true; PWM_Init(PWM1_BASEADDR、 kPWM_Module_3,&pwmConfig); PWM_Init(PWM2_BASEADDR、 kPWM_Module_3,&pwmConfig); PWM_Init(PWM3_BASEADDR、 kPWM_Module_1,&pwmConfig); PWM_Init(PWM4_BASEADDR、 kPWM_Module_1,&pwmConfig); // 故障配置 PWM_FaultDefaultConfig(&faultConfig); /* 安装 PWM 故障保护 */ PWM_SetupFaults(PWM1_BASEADDR、 kPWM_Fault_0&faultConfig); PWM_SetupFaults(PWM1_BASEADDR、 kPWM_Fault_1&faultConfig); PWM_SetupFaults(PWM1_BASEADDR、 kPWM_Fault_2&faultConfig); PWM_SetupFaults(PWM1_BASEADDR、 kPWM_Fault_3&faultConfig); /* 为子模块 0/1/2 设置 PWM 故障禁用映射 */ PWM_SetupFaultDisableMap(PWM1_BASEADDR、 kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR、 kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR、 kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR、 kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); /* 安装 PWM 故障保护 */ PWM_SetupFaults(PWM2_BASEADDR、 kPWM_Fault_0&faultConfig); PWM_SetupFaults(PWM2_BASEADDR、 kPWM_Fault_1&faultConfig); PWM_SetupFaults(PWM2_BASEADDR、 kPWM_Fault_2&faultConfig); PWM_SetupFaults(PWM2_BASEADDR、 kPWM_Fault_3&faultConfig); /* 为子模块 0/1/2 设置 PWM 故障禁用映射 */ PWM_SetupFaultDisableMap(PWM2_BASEADDR、 kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR、 kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR、 kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR、 kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); /* 安装 PWM 故障保护 */ PWM_SetupFaults(PWM3_BASEADDR、 kPWM_Fault_0&faultConfig); PWM_SetupFaults(PWM3_BASEADDR、 kPWM_Fault_1&faultConfig); PWM_SetupFaults(PWM3_BASEADDR、 kPWM_Fault_2&faultConfig); PWM_SetupFaults(PWM3_BASEADDR、 kPWM_Fault_3&faultConfig); /* 为子模块 0/1/2 设置 PWM 故障禁用映射 */ PWM_SetupFaultDisableMap(PWM3_BASEADDR、 kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR、 kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR、 kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR、 kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); /* 安装 PWM 故障保护 */ PWM_SetupFaults(PWM4_BASEADDR、 kPWM_Fault_0&faultConfig); PWM_SetupFaults(PWM4_BASEADDR、 kPWM_Fault_1&faultConfig); PWM_SetupFaults(PWM4_BASEADDR、 kPWM_Fault_2&faultConfig); PWM_SetupFaults(PWM4_BASEADDR、 kPWM_Fault_3&faultConfig); /* 为子模块 0/1/2 设置 PWM 故障禁用映射 */ PWM_SetupFaultDisableMap(PWM4_BASEADDR、 kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR、 kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR、 kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR、 kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0| kPWM_FaultDisable_1| kPWM_FaultDisable_2| kPWM_FaultDisable_3); /* 为单次轮询配置 PWM 的捕获输入 */ captureConfig.captureInputSel= true; 捕捉配置。边缘0= kPWM_RiseAndFallEdge; 捕捉配置。边缘1= kPWM_Disable; captureConfig.enableOneShotCapture= false; captureConfig.edgeCompareValue= 1; PWM_SetupInputCapture(PWM1_BASEADDR、 kPWM_Module_3, kPWM_PwmA&captureConfig); PWM_SetupInputCapture(PWM2_BASEADDR、 kPWM_Module_3, kPWM_PwmA&captureConfig); PWM_SetupInputCapture(PWM3_BASEADDR、 kPWM_Module_1, kPWM_PwmA&captureConfig); PWM_SetupInputCapture(PWM4_BASEADDR、 kPWM_Module_1, kPWM_PwmA&captureConfig); PWM_SetPwmLdok(PWM1_BASEADDR、 kPWM_Control_Module_3,true); PWM_SetPwmLdok(PWM2_BASEADDR、 kPWM_Control_Module_3,true); PWM_SetPwmLdok(PWM3_BASEADDR、 kPWM_Control_Module_1,true); PWM_SetPwmLdok(PWM4_BASEADDR、 kPWM_Control_Module_1,true); PWM_StartTimer(PWM1_BASEADDR、 kPWM_Control_Module_3); PWM_StartTimer(PWM2_BASEADDR、 kPWM_Control_Module_3); PWM_StartTimer(PWM3_BASEADDR、 kPWM_Control_Module_1); PWM_StartTimer(PWM4_BASEADDR、 kPWM_Control_Module_1); }
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NXP(CTN730)プログラマモデルの推奨 私は緑色です。 私 MCU-Link Proの注文構成リストが必要です。NXP CTN730 にファームウェアをダウンロードするには、J-Link を使用する必要があることに注意してください。 ありがとうございます。 緑 通信と制御(I3C | I2C | SPI | FlexCAN | イーサネット | FlexIO) Re: NXP(CTN730) Programmer model recommendation こんにちは@greenyangMY CTN730 関連の設計リソースが必要な場合は、以下のリンクからチケットを送信してください。 NXP 開発者向け技術サポートとリソース | NXP セミコンダクターズ Re: NXP(CTN730) Programmer model recommendation こんにちは@greenyangMY 自分でボードを設計しましたか?インターフェースは次のようになります。 MCU-Link Pro を使用すると、このインターフェースを介して直接デバッグまたはダウンロードを行うことができます。
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フラッシュメモリの書き込みに関連する問題を修正するにはどうすればいいですか? c40(低レベルドライバ)でブートローダーを開発するつもりです 私は s32ds バージョン 3.6.1 と RTD 4.0.0 を使用しています。 MCUはS32K314です。そして、ブートローダーを作成するためにフラッシュメモリに書き込んでみようと思います。 1. フラッシュメモリの書き込みに関連するエラーを修正するにはどうすればよいですか? c40_IP と cache_IP をインストールします。 Re: how do i fix that is related to write flash memory? こんにちは@rlaxortnさん、 互換性の問題のようです。 RTD 4.0.0 リリース ノートによると、このリリースは S32DS 3.5 IDEs で開発およびテストされています。 互換性を確保するには、各 S32DS インストールに互換性のあるソフトウェア セットを 1 つだけ含める必要があります。 同じ IDEs 内に複数の RTD リリースをインストールしないでください。 必要に応じて、複数の個別の S32DS インストールを維持CAN。 よろしくお願いいたします。 ダニエル
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S32K312 チップは I3C をサポートしていますか? Re: Does the S32K312 chip support lin? こんにちは、 はい、S32K312 マイクロコントローラは LIN 通信をサポートしています。 S32K312 は S32K3 ファミリの一部であり、データシートとブロック図に示されているように LIN サポートが含まれています。 LIN 機能は通常、LIN モード用に構成された LPUART (低電力 UART) モジュールを使用して実装されます。 よろしくお願いいたします。 ピーター Re: Does the S32K312 chip support lin? こんにちは、 ご返信ありがとうございます。再度お聞きしたいのですが、S32K312 チップは LIN 通信をサポートしていますか? よろしくお願いいたします。 ジン Re: Does the S32K312 chip support I3C? こんにちは、 I3C が仕様から削除されたことがわかりました。 したがって答えはノーです。 よろしくお願いいたします。 ピーター
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About I2S signal bridge configuration on NXP RT595 Is it possible to internally route the I2S signals in the RT595 from the Flexcomm1 input pins J15 (I2S BCLK) and H12 (I2S WS) to the Flexcomm4 output pins A12 (BCLK) and B11 (WS)? If so, how should this be configured? HW connection: External I2S audio source -> RT595 I2S input -> RT595 I2S output -> External I2S Speaker AMP --RT595 I2S input side (Flexcomm1): I2S BCLK -> [J15] PIO0_7/FC1_SCK (FUNC1) I2S WS -> [H12] PIO0_8/FC1_TXD_SCL_MISO_WS (FUNC1) I2S Data -> [H17] PIO0_9/FC1_RXD_SDA_MOSI_DATA (FUNC1) --RT595 I2S output side (Flexcomm4): I2S BCLK -> [A12] PIO0_28/ I2S_BRIDGE_CLK_OUT (FUNC5) I2S WS -> [B11] PIO0_29/ I2S_BRIDGE_WS_OUT (FUNC5) I2S Data -> [D14]PIO0_30/FC4_RXD_SDA_MOSI_DATA (FUNC1) For BCLK and WS, we prefer to directly pass these native signals from the RT595 input pins (J15/H12) to the output pins (A12/B11), rather than regenerating them inside the RT595, to keep the “Ext. I2S → RT595 → Ext. AMP” signal path synchronized to the external BCLK/WS. Below is my current configuration; however, it is not working, and I do not observe any signal on A12/B11. 1. Set FC1 J15/H12 as FUNC1 in pin_mux.c 2. Set FC4 A12/B11 as FUNC5 3. Configure bridge ---------------------------------------------------------------- /* --- I2S BRIDGE: route external Flexcomm1 SCK/WS to Flexcomm4 and bridge pins --- */ I2S_BRIDGE_SetShareSignalSrc(kI2S_BRIDGE_ShareSet0, kI2S_BRIDGE_SignalSCK, kI2S_BRIDGE_Flexcomm1); I2S_BRIDGE_SetShareSignalSrc(kI2S_BRIDGE_ShareSet0, kI2S_BRIDGE_SignalWS, kI2S_BRIDGE_Flexcomm1); I2S_BRIDGE_SetFlexcommSignalShareSet(kI2S_BRIDGE_Flexcomm4, kI2S_BRIDGE_SignalSCK, kI2S_BRIDGE_ShareSet0); I2S_BRIDGE_SetFlexcommSignalShareSet(kI2S_BRIDGE_Flexcomm4, kI2S_BRIDGE_SignalWS, kI2S_BRIDGE_ShareSet0); /* --- Init RX Interface (I2S1, Slave, from External I2S) --- */ I2S_RxGetDefaultConfig(&rxFromExti2sConfig); rxFromExti2sConfig.masterSlave = kI2S_MasterSlaveNormalSlave; I2S_RxInit(I2S1, &rxFromExti2sConfig); /* --- Init TX Interface (I2S4, Slave, to speaker Amp) --- */ I2S_TxGetDefaultConfig(&txToAMPConfig); txToAMPConfig.masterSlave = kI2S_MasterSlaveNormalSlave; I2S_TxInit(I2S4, &txToAMPConfig); ---------------------------------------------------------------- Platform: RT595 (MIMXRT595SFFOCR / BGA249) SDK: v25.6 Any suggestion would be greatly appreciated. Audio(PDM | I2S | SAI) Re: About I2S signal bridge configuration on NXP RT595 Hi @PASA , Thank you so much for your interest in our products and for using our community. I have reviewed your code and I think there are a few parts that need to be double check. 1: I2S4 should be set as master. 2: Did you configure the CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMMX); 3: Did you use your customed board or NXP development board. I suggest you can refer to this SDK demo "evkmimxrt595_i2s_dma_transfer" Wish it helps you. If you still have question about it, please kindly let me know.  Best Regards MayLiu
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i.MX95 ドキュメント i.MX95 用のアプリケーション プロセッサ リファレンス マニュアルはありますか?IMX95RM.PDF? i.MX93 から i.MX95 に切り替えます。i.MX93 の場合は IMX93RM.PDF を使用しました。i.MX95 用のものが見つからないので、見つかるまでは行き詰まってしまいます。
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Datasheet or info about SC667116GBMLQ75 Hi, Is it possible to get info \ datasheet about this semiconductor SC667116GBMLQ75  Re: Datasheet or info about SC667116GBMLQ75 Hello, Sure, this is custom chip made for specific automotive customer. The datasheets and documentations are internal. You can request the documentation via NXP web page ticket. Make sure you have valid NDA signed with NXP which is minimum requirement for release of such documents. Best regards, Peter
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Enable Hardware Crypto Engine Hello sir,  Currently I am using NXP Layerscape 1046ARDB kit in which I am executing L2fwd-crypto code with the software crypto-device as INntel IPsec-mb. Also TLS is  running parallely to it for key exchange  Now I want to migrate my code to kit with an objective to use Hardware crypto engine. So following are my queries related to it. Q1) How can I enable the hardware crypto engine in the kit. I'm currently giving command as: meson setup build --crossfile config/arm/arm64 -dpaa-linux_gcc -Denabledrivers=bus/dpaa,mempool/dpaa,crypto/dpaa_sec But only in Drivers section dma,raw,crypto dpaa is coming but not in enabled drivers section. How to resolve it? Q2) In the earlier version of the DPDK KNI was provided that is not available in newer version. So what is the alternative provided for this? Re: Enable Hardware Crypto Engine Hello, I have enabled CAAM in my kernel module now. Now the problem I am encountering is :  Q1) (Last lines of the output dmesg | grep -i caam ) Device caam-keygen registered  caam_jr 17300000.jr : failed to flush job ring 2. probe of 17300000.jr failed with error -5.                                                                                                                                                                          Q2)  for af-xdp the traffic coming on port eno1 is handled like this  sudo ethtool -L eno1 combined 2 # Add a flow rule to direct TCP traffic destined for port 443 to RX queue 1 sudo ethtool -N eno1 flow-type tcp4 dst-port 443 action 1                                                                                                                                                                         ./dpdk_app ... --vdev="net_af_xdp0,iface=eno1,start_queue=1,queue_count=1" ... nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst, MAX_PKT_BURST); Here I am giving that specific portid on which data is coming. Please calrify the queries.                                                                                                                                                                                   Re: Enable Hardware Crypto Engine Hello, Q1) To enable the hardware crypto engine: The issue appears to be with your meson build command. For DPAA crypto acceleration support in DPDK, you need to properly include the DPAA Security driver. Check if you have the required dependencies installed and the correct Linux headers. The syntax in your command looks correct, but you may need to ensure your build environment has all necessary prerequisites. Try adding the full path to the DPAA SEC driver in your command: ``` meson setup build --crossfile config/arm/arm64_dpaa_linux_gcc -Denable_drivers=bus/dpaa,mempool/dpaa,crypto/dpaa_sec ``` If you still don't see it in the enabled drivers section, verify the DPAA crypto accelerator is properly initialized in your kernel and that the required DPDK libraries are properly installed. Q2) Regarding KNI (Kernel NIC Interface) alternatives: In newer DPDK versions, KNI has been deprecated and removed. The recommended alternatives are: 1. AF_XDP (Address Family eXpress Data Path) - Provides a high-performance packet processing interface 2. AF_PACKET - A standard socket interface for packet processing 3. Virtio-user - For userspace networking applications For your specific use case with TLS key exchange running in parallel with L2fwd-crypto, AF_XDP would likely provide the best performance characteristics as a KNI replacement.   Regards
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S32K314でのSE050E AEAD復号化 様 S32K314 プラットフォームで、SE050E を使用して TLS1.3 を開発しています。 TLS1.3ハンドシェイク中に、 AEAD(AES GCM)キーがトラフィックキーとしてインポートされます。 AEADOneShotコマンド(AES GCM計算)Se05x_API_AeadOneShot()が実行されます。 ただし、SE050 は NACK で I2C にアクセスできません。理由は分かりません。 この問題が発生する前は、I2C は正常に動作していました。S32K314 I2C の問題ですか? それとも SE050 の問題ですか? よろしくお願いします。 チャン < LOG > mbedtls_cipher_aead_decrypt 暗号 ctx(20427388) モード 6 [INF][devtask] 暗号 Aead OneGo 開始:0x204273a8 暗号モード:0xb0、OP タイプ:0x38 [INF][devtask] キーID: 0xef0003b7 [INF][devtask] aadLen: 5 (17 3 3 0...) [INF][devtask] nonceLen: 12 (67 bf 6f e0...) [INF][devtask] タグ長さ: 16 (49 5b 34 3d...) APDU TX 長さ=75: 80 03 11 38 00 00 42 41 04 EF 00 03 B7 42 01 B0 43 10 E0 5E 33 33 D5 52 0D C4 86 51 E8 E7 6E 0C 86 30 44 05 17 03 03 00 20 45 0C CC C3 95 FF 3A 88 9A A0 64 44 F2 52 46 10 97 C5 DA 87 CE F6 98 C9 DB E3 8D 81 F4 C0 A8 3E 00 00 _i2c_write() が失敗しました。最大再試行!!! < SW Code > i2c_error_t axI2CWrite(void *conn_ctx, unsigned char bus, unsigned char addr, unsigned char *pTx, unsigned short txLen) { Lpi2c_Ip_StatusType status; int i; curr_check_ticks = SYS_TMR_TickCountGet(); { status = Lpi2c_Ip_MasterSendDataBlocking( I2C_INSTANCE_1, pTx, txLen, true, /* send STOP */ 100000 ); if (status == LPI2C_IP_SUCCESS_STATUS) { return I2C_OK; } else { if (status == LPI2C_IP_RECEIVED_NACK_STATUS) return I2C_NACK_ON_ADDRESS; else { __printf("%s Failed(0x%x)\\r\\n", __func__, status); return I2C_FAILED; } } } } int phPalEse_i2c_write(void *pDevHandle, uint8_t *pBuffer, int nNbBytesToWrite) { unsigned int ret = I2C_OK, retryCount = 0; int numWrote = 0; pBuffer[0] = 0x5A; //Recovery if stack forgot to add NAD byte. do { /* 1ms delay to give ESE polling delay */ sm_sleep(ESE_POLL_DELAY_MS); ret = axI2CWrite(pDevHandle, I2C_BUS_0, SMCOM_I2C_ADDRESS, pBuffer, nNbBytesToWrite); if (ret != I2C_OK) { T_SMLOG_D("_i2c_write() error : %d ", ret); if ((ret == I2C_NACK_ON_ADDRESS) && (retryCount < MAX_RETRY_COUNT)) { retryCount++; /* 1ms delay to give ESE polling delay */ /*i2c driver back off delay is providing 1ms wait time so ignoring waiting time at this level*/ //sm_sleep(ESE_POLL_DELAY_MS); T_SMLOG_D("_i2c_write() failed. Going to retry, counter:%d !", retryCount); continue; } if (retryCount == MAX_RETRY_COUNT) __printf("_i2c_write() failed(0x%x). Max retry !!!(size:%d)\\r\\n", ret, nNbBytesToWrite); return -1; } else { numWrote = nNbBytesToWrite; //sm_sleep(ESE_POLL_DELAY_MS); break; } } while (ret != I2C_OK); return numWrote; } smStatus_t DoAPDUTxRx(pSe05xSession_t session_ctx, const tlvHeader_t *hdr, uint8_t *cmdBuf, size_t cmdBufLen, uint8_t *rspBuf, size_t *pRspBufLen, uint8_t length_extended) { smStatus_t apduStatus = SM_NOT_OK; ENSURE_OR_GO_EXIT(hdr != NULL); if (cmdBufLen > 0) { ENSURE_OR_GO_EXIT(cmdBuf != NULL); } ENSURE_OR_GO_EXIT(pRspBufLen != NULL); ENSURE_OR_GO_EXIT(rspBuf != NULL); #ifdef ENABLE_SM_APDU_MUTEX SM_MUTEX_LOCK(g_sm_apdu_mutex); #endif { if (cmdBufLen > 0) { if ((cmdBufLen < 0xFF) && !length_extended) { ENSURE_OR_GO_EXIT((MAX_APDU_BUFFER - 5) >= cmdBufLen); memmove((cmdBuf + 5), cmdBuf, cmdBufLen); memcpy(cmdBuf, hdr, 4); cmdBuf[4] = cmdBufLen; ENSURE_OR_GO_EXIT((UINT_MAX - 5) >= cmdBufLen); cmdBufLen += 5; } else { ENSURE_OR_GO_EXIT((MAX_APDU_BUFFER - 7) >= cmdBufLen); memmove((cmdBuf + 7), cmdBuf, cmdBufLen); memcpy(cmdBuf, hdr, 4); cmdBuf[4] = 0x00; cmdBuf[5] = 0xFFu & (cmdBufLen >> 8); cmdBuf[6] = 0xFFu & (cmdBufLen); ENSURE_OR_GO_EXIT((UINT_MAX - 7) >= cmdBufLen); cmdBufLen += 7; } } else { memcpy(cmdBuf, hdr, 4); cmdBufLen = 4; } if (length_extended) { ENSURE_OR_GO_EXIT((MAX_APDU_BUFFER - 2) >= cmdBufLen); ENSURE_OR_GO_EXIT((UINT_MAX - 2) >= cmdBufLen); cmdBuf[cmdBufLen++] = 0x00; cmdBuf[cmdBufLen++] = 0x00; } apduStatus = smComT1oI2C_TransceiveRaw(session_ctx->conn_context, cmdBuf, cmdBufLen, rspBuf, pRspBufLen); if (*pRspBufLen >= 2) { apduStatus = rspBuf[(*pRspBufLen) - 2] << 8 | rspBuf[(*pRspBufLen) - 1]; } } exit: #ifdef ENABLE_SM_APDU_MUTEX SM_MUTEX_UNLOCK(g_sm_apdu_mutex); #endif return apduStatus; } smStatus_t Se05x_API_AeadOneShot(pSe05xSession_t session_ctx, uint32_t objectID, SE05x_CipherMode_t cipherMode, const uint8_t *pInputData, size_t inputDataLen, const uint8_t *pAad, size_t aadLen, uint8_t *pIV, size_t IVLen, uint8_t *pTagData, size_t *pTagDataLen, uint8_t *pOutputData, size_t *pOutputDataLen, const SE05x_Cipher_Oper_OneShot_t operation) { smStatus_t retStatus = SM_NOT_OK; tlvHeader_t hdr = {{kSE05x_CLA, kSE05x_INS_CRYPTO, kSE05x_P1_AEAD, operation}}; //uint8_t cmdbuf[SE05X_MAX_BUF_SIZE_CMD]; size_t cmdbufLen = 0; uint8_t *pCmdbuf; int tlvRet = 0; //uint8_t rspbuf[SE05X_MAX_BUF_SIZE_RSP] = {0}; uint8_t *pRspbuf; size_t rspbufLen = MAX_APDU_BUFFER; SE05x_Result_t result; uint16_t ivlen16 = 0; size_t ivlen32 = IVLen; size_t rspIndex = 0; pCmdbuf = &session_ctx->apdu_buffer[0]; pRspbuf = &session_ctx->apdu_buffer[0]; if (IVLen > UINT16_MAX) { goto cleanup; } ivlen16 = (uint16_t)IVLen; tlvRet = TLVSET_U32("objectID", &pCmdbuf, &cmdbufLen, kSE05x_TAG_1, objectID); if (0 != tlvRet) { goto cleanup; } #if SSS_HAVE_SE05X_VER_GTE_07_02 tlvRet = TLVSET_CipherMode("cipherMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, ((cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV) ? kSE05x_CipherMode_AES_GCM : cipherMode)); #else tlvRet = TLVSET_CipherMode("cipherMode", &pCmdbuf, &cmdbufLen, kSE05x_TAG_2, cipherMode); #endif if (0 != tlvRet) { goto cleanup; } tlvRet = TLVSET_u8bufOptional("inputData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_3, pInputData, inputDataLen); if (0 != tlvRet) { goto cleanup; } tlvRet = TLVSET_u8bufOptional("AdditionalData", &pCmdbuf, &cmdbufLen, kSE05x_TAG_4, pAad, aadLen); if (0 != tlvRet) { goto cleanup; } if ((cipherMode == kSE05x_CipherMode_AES_GCM) || ((cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV) && (operation == kSE05x_Cipher_Oper_OneShot_Decrypt))) { tlvRet = TLVSET_u8bufOptional("IV", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, pIV, IVLen); if (0 != tlvRet) { goto cleanup; } } else { tlvRet = TLVSET_U16("IVLen", &pCmdbuf, &cmdbufLen, kSE05x_TAG_5, ivlen16); if (0 != tlvRet) { goto cleanup; } } if (operation == kSE05x_Cipher_Oper_OneShot_Decrypt) { if (pTagDataLen != NULL) { //__printf("%s tgaDataLen is selected\\r\\n", __func__); //if (pTagDataLen > 0 ) { tlvRet = TLVSET_u8bufOptional("tag", &pCmdbuf, &cmdbufLen, kSE05x_TAG_6, pTagData, *pTagDataLen); if (0 != tlvRet) { goto cleanup; } } } //retStatus = DoAPDUTxRx_s_Case4_ext(session_ctx, &hdr, session_ctx->apdu_buffer, cmdbufLen, pRspbuf, &rspbufLen); retStatus = DoAPDUTxRx(session_ctx, &hdr, session_ctx->apdu_buffer, cmdbufLen, pRspbuf, &rspbufLen, 1); if (retStatus == SM_OK) { retStatus = SM_NOT_OK; if (inputDataLen != 0) { tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_1, pOutputData, pOutputDataLen); if (0 != tlvRet) { goto cleanup; } } if (operation == kSE05x_Cipher_Oper_OneShot_Encrypt) { tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, pTagData, pTagDataLen); if (0 != tlvRet) { goto cleanup; } } if (operation == kSE05x_Cipher_Oper_OneShot_Decrypt) { tlvRet = tlvGet_Result(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_2, &result); if (0 != tlvRet) { goto cleanup; } if (result != kSE05x_Result_SUCCESS) { goto cleanup; } } if ((operation == kSE05x_Cipher_Oper_OneShot_Encrypt) && (cipherMode == kSE05x_CipherMode_AES_GCM_INT_IV)) { tlvRet = tlvGet_u8buf(pRspbuf, &rspIndex, rspbufLen, kSE05x_TAG_3, pIV, &ivlen32); if (0 != tlvRet) { goto cleanup; } } if ((rspIndex + 2) == rspbufLen) { retStatus = (smStatus_t)((pRspbuf[rspIndex] << 😎 | (pRspbuf[rspIndex + 1])); } } cleanup: return retStatus; } int sss_se05x_aead_one_go(mbedtls_cipher_context_t *ctx, const uint8_t *srcData, uint8_t *destData, size_t size, uint8_t *nonce, size_t nonceLen, const uint8_t *aad, size_t aadLen, uint8_t *tag, size_t *tagLen) { int retval = -1; smStatus_t status = SM_NOT_OK; /* Already saved aead cipher ctx */ sss_se05x_aead_t *context = (sss_se05x_aead_t *)ctx->cipher_ctx; size_t destDataLen = size; SE05x_CipherMode_t cipherMode = (context->algorithm == kAlgorithm_SSS_AES_GCM) ? kSE05x_CipherMode_AES_GCM : kSE05x_CipherMode_AES_GCM_INT_IV; SE05x_Cipher_Oper_OneShot_t OperType = (context->mode == kMode_SSS_Encrypt) ? kSE05x_Cipher_Oper_OneShot_Encrypt : kSE05x_Cipher_Oper_OneShot_Decrypt; // Not support decrypt with internal IV. SMLOG_I("Cipher Aead OneGo Start:0x%x Cipher Mode:0x%x, OP Type:0x%x", context->keyObject, cipherMode, OperType); SMLOG_I(" Key ID: 0x%x\\r\\n", context->keyObject->keyId); SMLOG_I(" aadLen: %d (%x %x %x %x...)", (size_t)aadLen , aad[0], aad[1], aad[2], aad[3]); SMLOG_I(" nonceLen: %d (%x %x %x %x...)", nonceLen, nonce[0], nonce[1], nonce[2], nonce[3]); SMLOG_I(" tagLen: %d (%x %x %x %x...)", *tagLen, tag[0], tag[1], tag[2], tag[3]); ENSURE_OR_GO_EXIT(context->keyObject != NULL); status = Se05x_API_AeadOneShot(context->keyObject->session, context->keyObject->keyId, cipherMode, srcData, size, aad, aadLen, nonce, nonceLen, tag, tagLen, destData, &destDataLen, OperType); if (status == SM_ERR_APDU_THROUGHPUT) { retval = kStatus_SSS_ApduThroughputError; goto exit; } SMLOG_I("Cipher Aead One Go Status: 0x%x\\r\\n", status); ENSURE_OR_GO_EXIT(status == SM_OK); retval = 0; exit: return retval; } int psa_mbedtls_gcm_auth_decrypt( mbedtls_cipher_context_t *ctx, size_t length, const unsigned char *iv, size_t iv_len, const unsigned char *add, size_t add_len, const unsigned char *tag, size_t tag_len, const unsigned char *input, unsigned char *output ) { int ret = 0; size_t TAG_SIZE = tag_len; /* should be */ ret = sss_se05x_aead_one_go( ctx, // AEAD context input, // srcData (ciphertext) output, // destData (plaintext) length, // size (uint8_t *)iv, // nonce iv_len, // nonceLen add, // aad add_len, // aadLen (uint8_t *)tag, // tag &TAG_SIZE // tagLen ); if (ret != 0) { ret = MBEDTLS_ERR_GCM_AUTH_FAILED; } return( ret ); } int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, const unsigned char *iv, size_t iv_len, const unsigned char *ad, size_t ad_len, const unsigned char *input, size_t ilen, unsigned char *output, size_t output_len, size_t *olen, size_t tag_len) { #if defined(MBEDTLS_CIPHER_MODE_AEAD) /* AEAD case: check length before passing on to shared function */ if (ilen < tag_len || output_len < ilen - tag_len) { return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; } return mbedtls_cipher_aead_decrypt(ctx, iv, iv_len, ad, ad_len, input, ilen - tag_len, output, olen, input + ilen - tag_len, tag_len); #else return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; #endif /* MBEDTLS_CIPHER_MODE_AEAD */ } Re: SE050E AEAD Decryption in S32K314 こんにちは@Changhawn S32K3 デバイス用の現在の MbedTLS ミドルウェア スタックは、HSE によって提供されるセキュリティ機能とともに、トランスポート層セキュリティ (TLS) プロトコル バージョン 1.2 をサポートしています。現時点では、TLS 1.3 は S32K3 デバイスではサポートされておらず、その実装はサポートの範囲外となります。 SE050 に関連する問題については、 Secure 認証コミュニティに質問を投稿してください。これらのデバイスの専任サポート チームがさらにサポートします。 BR、ヴェインB
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software can not login I'm using NXP's Guider to design the UI, but the current PC software keeps showing the message: 'Process not completed. The action wasn't completed. Please start the process again to continue.' Does anyone know why this is happening? Re: software can not login Hi @DO123  Can you provide more details? Picture or video? I want to reproduce this issue. BR Harry
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