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Schematic / AT-F DTS mismatch on S32G-VNP-RDB3 Evaluation Board

I am looking at the schematic and device tree for the arm trusted firmware on the S32G-VNP-RDB3 board and see what looks like a mismatch in netnames and the pinctrl functionality with respect to the PFE pins.

This is a pictue from the schematic showing that the RGMII_B_* net pins are labelled as PFE_MAC2_* on the S32G side.

Looking at the device tree and cross-referencing the S32G3_IOMUX.xlsx spreedsheet I see that they are actually mapped to PFE_MAC0_* internally.

Here is a snippet from the device tree @ https://github.com/nxp-auto-linux/arm-trusted-firmware/blob/0cd12bb2630a23e760683bf3d911e3c1e282efd5...

And here I added comments to show how the functional groups for the pins map according to the spreadsheet...

    pfe0_pins: pfe0 {
        pfe0_grp0 {
            pinmux = , /* PFE_MAC0_TX_EN_O */
                 ,    /* PFE_MAC0_TXD_O[1] */
                 ,    /* PFE_MAC0_TXD_O[2] */
                 ,    /* PFE_MAC0_TXD_O[3] */
                 ;    /* PFE_MAC0_TXD_O[0] */
            output-enable;
            slew-rate = ;
        };  

        pfe0_grp1 {
            pinmux = , /* GPIO / PFE_MAC0_RX_CLK_I */
                 ,     /* GPIO / PFE_MAC0_RXDV_I */
                 ,     /* GPIO / PFE_MAC0_RXD_I[0] */
                 ,     /* GPIO / PFE_MAC0_RXD_I[1] */
                 ,     /* GPIO / PFE_MAC0_RXD_I[2] */
                 ;     /* GPIO / PFE_MAC0_RXD_I[3] */
            input-enable;
            slew-rate = ;
        };  

        pfe0_grp2 {
            pinmux = ; /* PFE_MAC0_TX_CLK_O */
            output-enable;
            slew-rate = ;
            bias-pull-up;
        };  

        pfe0_grp3 {
            pinmux = , /* GPIO / PFE_MAC0_RX_CLK_I */
                 ,     /* GPIO / PFE_MAC0_RXDV_I */
                 ,     /* GPIO / PFE_MAC0_RXD_I[0] */
                 ,     /* GPIO / PFE_MAC0_RXD_I[1] */
                 ,     /* GPIO / PFE_MAC0_RXD_I[2] */
                 ;     /* GPIO / PFE_MAC0_RXD_I[3] */
        };  

    };

So my question is basically are the S32G side nets on the schematic mislabelled and should actually read PFE_MAC0_*? I am using this as the reference for a custom design and want to make sure I have the correct understanding. Thanks.

Re: Schematic / AT-F DTS mismatch on S32G-VNP-RDB3 Evaluation Board

Hello @minersrevolt ,

For what I can see you were able to solve your questions. Is that correct? if not, please let us know the exact open points or doubts you might still have so we can support you.

Thanks

Re: Schematic / AT-F DTS mismatch on S32G-VNP-RDB3 Evaluation Board

Looking at the Linux DTS looks like the Functional Groups actually match MAC2 so it is just the AT-F that is out of sync. https://github.com/nxp-auto-linux/linux/blob/adceb7e8fa72c4f26207356a5a33b55b0838717f/arch/arm64/boo...

	pfe2mdiob_pins: pfe2mdiob_pins {
		pfe2mdiob_grp0 {
			pinmux = ;
			output-enable;
			slew-rate = ;
		};


		pfe2mdiob_grp1 {
			pinmux = ;
			output-enable;
			input-enable;
			slew-rate = ;
		};


		pfe2mdiob_grp2 {
			pinmux = ;
		};
	};


	pfe2rgmiib_pins: pfe2rgmiib_pins {
		pfe2rgmiib_grp0 {
			pinmux = ,
				 ,
				 ,
				 ,
				 ;
			output-enable;
			slew-rate = ;
		};


		pfe2rgmiib_grp1 {
			pinmux = ,
				 ,
				 ,
				 ,
				 ,
				 ;
			input-enable;
			slew-rate = ;
		};


		pfe2rgmiib_grp2 {
			pinmux = ,
				 ,
				 ,
				 ,
				 ,
				 ,
				 ;
		};


		pfe2rgmiib_grp3 {
			pinmux = ;
			output-enable;
			slew-rate = ;
			bias-pull-up;
		};
	};