Linux-qoriq イメージの Yocto scarthgap ビルドが失敗する MACHINE 変数は、Yocto (scarthgap) 内の powerpc freescale 64bit コンパイラでコンパイルする 1024rdb-64b に設定されます。 私は、顧客のyoctoビルド環境の古い実装をダンフェルベースのシステムからscarthgapバージョンに移植しようとしています。 システムが構築されているので、いくつかの問題を修正することができましたが、linux-qoriqパッケージのビルドに関しては、ビルドは失敗します。ログを添付しました。 奇妙なことに、devshellに入り、顧客のdefconfigファイルを使用して同じコードをビルドすると、問題なくコンパイルされますが、bitbake -c compile linux-qoriqはコンパイルプロセスで確実に失敗することです。 これを分解または修正する方法についてのアドバイスは大歓迎です。 乾杯！！ Re:Linux-qoriqイメージのYocto scarthgapビルドが失敗する Dunfellのディストリビューションリリースがあり、これにはT1024が含まれています。このリリースのドキュメントについては、 これを参考にすることができます https://docs.nxp.com/bundle/GUID-E5527A77-2F97-4244-BF9C-D08F068EFD16/page/GUID-2BDBF943-FBB7-46C3-80B3-43A4BCBC6ABB.html ただし 、このリリースでは継続的なサポートはなく 、 NXPにはこの製品のSDKアップグレードプランもありません。 Re:Linux-qoriqイメージのYocto scarthgapビルドが失敗する MPUの部品番号を教えてください。

Does the iMX9332 processor have internal mac addresses? Hello everyone, I need to know if iMX9332 processor has internal MAC addresses (let's say ready for use) for the two Ethernet ports that it delivers, or it's necessary to add external EEPROMs. Regards, Roberto Re: Does the iMX9332 processor have internal mac addresses? yes imx93 has it Re: Does the iMX9332 processor have internal mac addresses? Yes and NO. MAC addresses U have to buy them and burn them U can burn then then in fuses.

IMX8QM MEK 如何在设备树中设置 lpuart0 你好， 我在设备树中配置 LPUART0 时遇到了困难。我最近开始使用 imx8 板，但难以理解设备节点中的时钟分配。 LPUART 是否需要 LPCG 模块？我如何知道 LPUART 所需的时钟？时钟说明符中的时钟 ID 是什么？您能推荐一些我可以阅读的文档吗？ 谢谢，如果这不是发布该问题的正确论坛，请告诉我。 回复：IMX8QM MEK 如何在设备树中设置 lpuart0 你好， 您可以使用我们已有的 LPUART0 定义作为参考，但请注意，在我们的 MEK 板中，我们使用此端口进行调试输出： https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi#L130 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8qm-mek.dts#L923 此外，关于论坛，对于 i.MX 处理器问题，我建议使用以下部分： https://community.nxp.com/t5/i-MX-Processors/bd-p/imx-processors 致以最诚挚的问候/问候， 阿尔多。

undefined LPUART_UART_IP_6_IRQHandler i am using s32k344. i add intctrl_ip, lpuart_uart, suil2_port drivers. and i set lpuart6 interrupt in intctrl_ip.  hander name is LPUART_UART_IP_6_IRQHandler. after generate code, i build source code.  and i got a error undefined LPUART_UART_IP_6_IRQHandler.  although i found LPUART_UART_IP_6_IRQHandler in Lpuart_Uart_Ip_Irq.c it is does not activated Lpuart_Uart_Ip_Irq function.  so do i have to make LPUART_UART_IP_6_IRQHandler external function? or can i know method LPUART_UART_IP_6_IRQHandler is being activated? thank. Re: undefined LPUART_UART_IP_6_IRQHandler Hi@rlaxortn you need to choose Lpuart_6

[i.MX93] play video(MP4) Hi, I want to play video on i.MX93 evk but failed. root@imx93evk:~# gplay-1.0 ../weston/videoplayback.mp4 FSL_GPLAY2_01.00_LINUX build on May 10 2023 01:50:04 playbin3 is enabled ====== AIUR: 4.8.0 build on May 10 2023 01:50:04. ====== Core: MPEG4PARSER_06.20.12 build on Feb 2 2023 06:07:55 file: /usr/lib/imx-mm/parser/lib_mp4_parser_arm_elinux.so.3.2 ------------------------ Track 00 [video_0] Enabled Duration: 0:04:43.016066000 Language: und Mime: video/x-h264, parsed=(boolean)true, alignment=(string)au, stream-format=(string)avc, width=(int)464, height=(int)360, framerate=(fraction)30000/1001, codec_data=(buffer)0142c016ffe1001a6742c016da0742ff97016a020202800001f480007530078b175001000468ce3c80 ------------------------ ------------------------ Track 01 [audio_0] Enabled Duration: 0:04:43.074467000 Language: und Mime: audio/mpeg, mpegversion=(int)4, channels=(int)2, rate=(int)44100, bitrate=(int)0, stream-format=(string)raw, codec_data=(buffer)12100000000000000000000000000000 ------------------------ ====== BEEP: 4.8.0 build on May 10 2023 01:50:04. ====== Core: AAC decoder Wrapper build on Jul 25 2022 15:45:05 file: /usr/lib/imx-mm/audio-codec/wrap/lib_aacd_wrap_arm_elinux.so.3 CODEC: BLN_MAD-MMCODECS_AACD_ARM_03.09.00_ARMV8 build on Sep 16 2022 13:23:31. ===!!! Current pulsesink device is alsa_output.platform-sound-xcvr.iec958-stereo !!!=== =========== fsl_player_play() ================== FSL_GPLAY2_01.00_LINUX build on May 10 2023 01:50:04 [h]display the operation Help [p]Play [s]Stop [e]Seek [a]Pause when playing, play when paused [v]Volume [m]Switch to mute or not [>]Play next file [<]Play previous file [r]Switch to repeated mode or not [u]Select the video track [Stop (No Repeated)][Vol=1.0][00:00:00/00:04:43] [d]Select the audio track [b]Select the subtitle track [n]Select adaptive playback track [f]Set full screen [z]resize the width and height [t]Rotate [c]Setting play rate [i]Display the metadata [x]eXit State changed: buffering State changed: playing [Playing (No Repeated)][Vol=1.0][00:04:42/00:04:43]EOS Found getNextItem No next item! No more media file, exit gplay! FSL_PLAYER_UI_MSG_EXIT Exit display thread fsl_player_deinit I follow the page here and found no change. https://docs.nxp.com/bundle/AN13917/page/topics/video_playback_local_gplay.html root@imx93evk:~# ./setup_video.sh [ 889.088365] imx-dwmac 428a0000.ethernet eth1: FPE workqueue stop [ 889.099820] audit: type=1334 audit(1720686677.319:22): prog-id=17 op=LOAD [ 889.110532] audit: type=1334 audit(1720686677.327:23): prog-id=18 op=LOAD [ 889.198447] imx-dwmac 428a0000.ethernet eth1: PHY [stmmac-1:01] driver [RTL8211F-VD Gigabit Ethernet] (irq=POLL) [ 889.208662] imx-dwmac 428a0000.ethernet eth1: configuring for phy/rgmii-id link mode root@imx93evk:~# gplay-1.0 ../weston/videoplayback.mp4 FSL_GPLAY2_01.00_LINUX build on May 10 2023 01:50:04 playbin3 is enabled ====== AIUR: 4.8.0 build on May 10 2023 01:50:04. ====== Core: MPEG4PARSER_06.20.12 build on Feb 2 2023 06:07:55 file: /usr/lib/imx-mm/parser/lib_mp4_parser_arm_elinux.so.3.2 ------------------------ Track 00 [video_0] Enabled Duration: 0:04:43.016066000 Language: und Mime: video/x-h264, parsed=(boolean)true, alignment=(string)au, stream-format=(string)avc, width=(int)464, height=(int)360, framerate=(fraction)30000/1001, codec_data=(buffer)0142c016ffe1001a6742c016da0742ff97016a020202800001f480007530078b175001000468ce3c80 ------------------------ ------------------------ Track 01 [audio_0] Enabled Duration: 0:04:43.074467000 Language: und Mime: audio/mpeg, mpegversion=(int)4, channels=(int)2, rate=(int)44100, bitrate=(int)0, stream-format=(string)raw, codec_data=(buffer)12100000000000000000000000000000 ------------------------ ====== BEEP: 4.8.0 build on May 10 2023 01:50:04. ====== Core: AAC decoder Wrapper build on Jul 25 2022 15:45:05 file: /usr/lib/imx-mm/audio-codec/wrap/lib_aacd_wrap_arm_elinux.so.3 CODEC: BLN_MAD-MMCODECS_AACD_ARM_03.09.00_ARMV8 build on Sep 16 2022 13:23:31. ===!!! Current pulsesink device is alsa_output.platform-sound-xcvr.iec958-stereo !!!=== [Stop (No Repeated)][Vol=1.0][00:00:00/00:04:43]=========== fsl_player_play() ================== FSL_GPLAY2_01.00_LINUX build on May 10 2023 01:50:04 [h]display the operation Help [p]Play [s]Stop [e]Seek [a]Pause when playing, play when paused [v]Volume [m]Switch to mute or not [>]Play next file [<]Play previous file [r]Switch to repeated mode or not [u]Select the video track [d]Select the audio track [b]Select the subtitle track [n]Select adaptive playback track [f]Set full screen [z]resize the width and height [t]Rotate [c]Setting play rate [i]Display the metadata [x]eXit State changed: buffering State changed: playing [Playing (No Repeated)][Vol=1.0][00:00:27/00:04:43]^C Aborted by signal[2] Interrupt... FSL_PLAYER_UI_MSG_EXIT Exit display thread fsl_player_deinit THANKS~~ Joe Re: [i.MX93] play video(MP4) LICENSE_FLAGS_ACCEPTED:append += "commercial" IMAGE_INSTALL:append = "gstreamer1.0-libav" PACKAGECONFIG:append_pn-gstreamer1.0-libav = "x264" This works, but need to fix dependency of other packages. But we will fix that later, thanks for help. THANKS~~ Joe Re: [i.MX93] play video(MP4) There is no hardware decoder for i.MX93.  The SW decoder can be enabled in the build by making the following changes to the  conf/local.conf file: LICENSE_FLAGS_ACCEPTED += "commercial" IMAGE_INSTALL:append = "gstreamer1.0-libav" PACKAGECONFIG:append_pn-gstreamer1.0-libav = "x264"

S32K344 フラッシュ動作と割り込み こんにちは、DFlash / PFlashが書き込みまたは消去操作を実行しているとき、すべての割り込みをしばらく無効にする必要があることについて質問がありますか? 例えば、C40_Ip_MainInterfaceSectorErase()またはC40_Ip_MainInterfaceWrite()より前のすべての割り込みを無効にし、操作が完了したらすべての割り込みを有効にします。 all interruptが無効になっている場合、何か問題はありますか? 日時:S32K344フラッシュの動作と割り込み コードがプログラムされたフラッシュモジュール(RWW)とは異なるフラッシュモジュールから実行されている場合、フラッシュプログラミング中に割り込みを処理できます。それ以外の場合は、RWWエラーを防ぐためにフラッシュプログラミング/消去前に割り込みを無効にする必要があります。

S32K344 Flash operation and interrupt Hello,I have question about When DFlash/PFlash is doing the write or erase operation,all interrupts must be disabled for awhile? For example,disable all interrupts before C40_Ip_MainInterfaceSectorErase() or C40_Ip_MainInterfaceWrite(),then enable all interrupts when operation is done. Is there have any problem if the all interrupt is not disabled? Re: S32K344 Flash operation and interrupt If code is being executed from different flash module than programmed (RWW) then interrupts can be handled during flash programming otherwise it is needed to disable interrupt before flash programming/erasing to prevent RWW error.

S32K344 secureBoot 在ASB模式下实施postBoot，SMR关联app，CR为HSE_CR_SANCTION_DIS_ALL_KEYS时。由于是并行方式所以HSE会释放core 0，同时进行SMR验证。我理解此时app代码已经运行，那么app里能不能通过某个寄存器标志知道SMR的验证结果是成功还是失败呢？

i.mx 93 TPM timer configuration I'm working with a SoM based on the i.mx 9352. I'm looking for a way on how to create a chain of TPM timers in the firmware for the Cortex-M core. In my case, I use TPM6_EXTCLK pin for receiving external clock source from a crystal and then it is used for generating signals on TMP6_CH1, TMP6_CH2 and TMP6_CH3. I want to use TMP6_CH0 as an external source for the TMP5. Is it possible to use an output of the TMP6_CH0 as a an external clock source for TMP5_EXTCLK? Or is this only possible by physically connecting the TMP6_CH0 and TMP5_EXTCLK pins? Maybe it is possible by using an external trigger source? It is mentioned in the RM for i.mx 93 that I should see the chip-specific TPM information for available external trigger options, but I don't know where to find this information - is it an extra document about i.mx 9352? Re: i.mx 93 TPM timer configuration Dear @Manuel_Salas , Clearly, thank you, then we will think about the physical routing in this case. But maybe you know where to find the information about the external trigger options for TPM? RM manual for i.mx 93 refers to the chip-specific TPM information, but I cannot find it anywhere: I've tried to search around the document, but seems this information is not available in the RM. Re: i.mx 93 TPM timer configuration Hello @Karr  Thank you for the clarification, I double checked and according the reference manual, there is not a way to do a "trigger" from TPMn to other TPM, it appears it must be a physical connection as you described. Best regards, --... ...-- Salas. Re: i.mx 93 TPM timer configuration Hello @Manuel_Salas, Thank you for the diagram! I used it to understand how I can clock my TIM6 by an external source, and it is a kind of working now. My current issue is that I don't know is it possible to clock TIM5 with an output channel of TIM6 (e.g. TIM6_CH0). To illustrate better what I'm trying to build I've made this picture based on your diagram: I see that TPM clock can be sourced either by an external clock source (case for TIM6) or by an external trigger source. And I thought that the external trigger source for TIM5 can be an output of the TIM6_CH0. But for now I see only one way how to do that - physically connect TIM6_CH0 pin to the TIM5_EXTCLK pin. Is there are some internal connections inside the MCU, which I can use instead of the physical connection? So basically I want to have TIM5 and TIM6 been synchronized, and use extra TIM5's channels for sending events based on the TIM6_CH0 output. Re: i.mx 93 TPM timer configuration Hello @Karr  Look the below Block diagram: In chapter 67.3.10.1 Counter Clock mode of reference manual is mentioned: SC[CMOD] either disables the TPM counter or enables one of the three possible clock sources for the TPM counter. After any reset, SC[CMOD] becomes 0, which disables the TPM counter. You can configure SC[CMOD] for one of the following counter clock sources: • Asynchronous counter clock • External clock input pin • External trigger source You can read or write to SC[CMOD] at any time. Disabling the TPM counter by writing 0 to SC[CMOD] does not affect the TPM counter value or other registers, but the TPM counter clock domain must acknowledge this disabling action before SC[CMOD] becomes 0. The external clock input and external trigger source pass through a synchronizer. The TPM counter clock clocks this synchronizer to ensure that counter transitions are properly aligned to counter clock transitions. Therefore, to meet Nyquist criteria, and also considering jitter, the frequency of the external clock source must be less than half of the counter clock frequency. Also, look the TRGSEL and TRGSRC bits on CONF register (67.7.1.16 Configuration (CONF)). I hope this information can helps to achieve your application. Best regards, --... ...-- Salas.

About the u-boot-imx*_sd_optee.imx Hi All,   I want to port optee os on imx6q SOC platform.I find some porting info in IMX_PORTING_GUIDE.pdf(UG10165) 5.3 OP-TEE booting flow Booting flow on i.MX 6 and i.MX 7 (Arm V7): Files and binaries required in the boot partition: • u-boot-imx*_sd_optee.imx: U-Boot binary specific to boot OP-TEE. Only booting from the SD card is supported for OP-TEE. • uTee-*: Self-extracting image containing the OP-TEE binary. I want to know how to generate the u-boot-imx*_sd_optee.imx image,and which uboot config file I can use. Re: About the u-boot-imx*_sd_optee.imx Hi @liuxing  You can use the one - mx6qpsabresd_optee_defconfig Send you more information in system email. Regards Harvey

Issues with meta-nxp-security-reference-design Hello, I just started to work on adding secure boot to my project (irst time and lot of reading). In the Linux User Guide, IMXLUG_6.6.23_2.0.0, from June 28 2024, section 10.9.1.3 Yocto setup for secure boot build, you cannot follow the steps due to a lacking manifest. Also, when I manually added the layer, the nxp-cst-signer.bb  is pointing towards CST_SIGNER ?= "git://[email protected]/imxs/cst-signer.git;protocol=ssh"  which I assume is a place where I should not have access. I guess it might be ok to point it towards https://github.com/nxp-imx-support/nxp-cst-signer.git instead? Is there a way to report such things, or is the forum the place to go? Are you using githubs issue tracker? Best regards Re: Issues with meta-nxp-security-reference-design Hi @malj,  Thank you for your report, the expert team will fix the link. In the meantime, you can use the GitHub link. git://github.com/nxp-imx-support/nxp-cst-signer.git;protocol=https Re: Issues with meta-nxp-security-reference-design Hi @malj,  Thank you for contacting NXP Support! I have reviewed the case and currently, I'm checking with the team for possible solutions.

Windows uuu 失败，错误：FB：未找到图像文件 摘要：在 Windows 中，当我尝试按照说明在 i.MX 8M mini IVKB 上安装 Linux BSP 时，UUU 给出“错误：FB：未找到图像文件” ： https://www.nxp.com/document/guide/getting-started-with-the-i-mx-8m-mini-evkb:GS-iMX-8M-Mini-EVK?section=embedded-linux&SAMLart=ST-AAF0E3YJDJej%2BJVBprc7Vu5rkUdez9xrG2lkcSkLOYnr1j9uf7bmooLH 说明如下： 将恩智浦Linux BSP镜像刻录到板上 > uuu.exe L5.4.70_2.3.0_images_MX8MMEVK.zip 打开开发板， uuu开始将图像复制到开发板。 完成后，将板断电，并参考启动开关设置，配置板从SD卡启动。 当然，我需要使用我下载的文件的名称，即LF_v6.6.23-2.0.0_images_IMX8MMEVK.zip ，它看起来不错，因为它是一个格式类似的名称。当我将其传递给 uuu 时，它显示： 我认为这意味着我应该输入命令（运行 uuu），然后打开电路板......这看起来很奇怪，但没关系。我不明白关于 SD 卡的最后一句话。我以为这会直接刻录到设备上 适用于 nxp imx 芯片的 uuu（通用更新实用程序）--libuuu_1.5.182-0-gda3cd53 成功 0 失败 0 等待已知 USB 设备出现... 错误：FB：未找到图像文件 准备 1/ 0 [==================100%==================] Http 下载\解压缩 令人困惑的杂乱信息。它显示“未找到图像文件”，然后显示一些关于准备的进度输出，看起来它已经完成了。也许“解压缩”表示正在解压缩输入文件。 但是，由于它完成得如此之快，我认为它失败了。我可能做错了什么？ 回复：Windows uuu 出现错误：FB：未找到图像文件 谢谢。这似乎确实是一个解决办法。 我不知道你说的“uuu.auto 或 uuu.auto-xxx 无法匹配预编译固件”是什么意思。我同意它确实不匹配。但我看不出它有什么理由不匹配。事实上，它应该匹配。我向恩智浦提交了工单来修复这个问题……但我并不指望它能被修复。 😉 我昨天自己也发现了这个问题。通过调试 uuu，我确定了它找不到的文件的名称，然后查看了 uuu.auto，因为我当天就发现那是 uuu 的配置文件。问题是，uuu 应该报告它找不到的文件的名称。不报告文件名是（程序及其程序员的）懒惰行为。

S32K144 SRAM address configuration Hi NXP team, We are currently using S32K144 and have encountered a problem. Could you please help us solve it? Thanks! From S32K1xx_Memory_Map.xlsx of the RM, the start address of SRAM_U is 0x2000_0000: Could m_data_2‘s ORIGIN in the link file S32K144_64_flash.ld of S32K144 be set arbitrarily? For example, can it be changed to be less than 0x2000_0000 as following? BTW, we made an initial attempt(change m_data_2‘s ORIGIN to 0x1FFFE000) and confirmed that the compilation could be successfully passed in the S32DS environment, and the generated program could be smoothly downloaded to the S32K144 product board with a normal running status. Thanks,  Alex Re: S32K144 SRAM address configuration Hi Senlent, OK got it, thanks a lot. Thanks, Alex Re: S32K144 SRAM address configuration Hi@AlexKlose There will be no error if you define it this way, and there will be no error if you download it to MCU. What I want to tell you is that we have some considerations when designing the link file in this way, and it is allocated according to SRAM_L and SRAM_U. Whether there are potential problems when you modify the link file in this way, you need to do sufficient testing yourself. Re: S32K144 SRAM address configuration Hi Senlent, Sorry, I still don't quite understand what you meant in the last post... I merely want to make sure whether this operation(m_data_2‘s ORIGIN to 0x1FFFE000) itself is legal or not. If not, we would try to optimize the code to reduce the size of the .bss section. Thanks, Alex Re: S32K144 SRAM address configuration Hi@AlexKlose Usually users may not pay attention to the fact that SRAM_L and SRAM_U are two different blocks. This needs to be noted when dealing with certain issues, such as ECC processing. Re: S32K144 SRAM address configuration Hi Senlent, Thanks for your quick response. Since SRAM_L and SRAM_U are two separate physical RAMs, is this operation (m_data_2‘s ORIGIN to 0x1FFFE000) compliant? What risks does it entail?  "which is more reasonable, but you will not get an error if you define it this way." That means we can still do it this way to expand the space of m_data_2  although this operation is not recommended? Thanks, Alex Re: S32K144 SRAM address configuration Hi@AlexKlose The reason why we define it this way is based on the physical address space of the two blocks of SRAM, which is more reasonable, but you will not get an error if you define it this way. For s32k144, the SRAM_L  address range is :0x1FFF8000~0x1FFFFFFF the SRAM_U address range is: 0x20000000~0x20006FFF 0x1FFFE000 is in the range SRAM_L, but it is not SRAM_U.

将比较器 (LPCMP) 输出路由至 eMIOS (IPWM 模式) 进行频率测量 大家好， 我正在尝试将比较器的输出路由到配置为 IPWM 模式的 eMIOS 通道，目的是测量比较器输出的频率。我已经设置了 TRGMUX 配置，如下所示，但我没有看到 eMIOS 通道 1 上出现预期的任何响应。 有人能帮我找出可能缺少什么或指导我如何正确实现此设置吗？ 提前谢谢！ 回复：将比较器（LPCMP）输出路由到eMIOS（IPWM模式）进行频率测量 我已经解决了这个问题。可以关闭相同的

MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found I am getting an error when I try to debug the Open LPC example "periph_blinky" on the LPCXpresso 1769 development board # OM13085 using LinkServer.  The error says: Could not determine GDB version using command: arm-none-eabi-gdb --version arm-none-eabi-gdb: error while loading shared libraries: libncursesw.so.5: cannot open shared object file: No such file or directory libncursesw.so.5 cannot be installed with apt because it is no longer available for Ubuntu 24.04. libncursesw6 is installed. Do you have any suggestions? Re: MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found I'm not familiar with the actual implementation of libncurses and the differences between 5 & 6,  so I cannot guarantee that your workaround is completely correct. The ABIs certainly differ even though the APIs might be largely the same. Note that we released MCUXpresso IDE v25.06 recently (MCUXpresso IDE v25.06 Now Available - NXP Community) and this is shipped with newer Arm GNU Toolchain that no longer depends on the libncurses 5. Best regards, Adrian Re: MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found After making symbolic links: libncursesw.so5->libnsursesw.so6 and libtinfo.so.5->libtinfo.so.6, the debugger worked.  The symbolic links need to be made in two places: /usr/lib/i386-linux-gnu, and also /usr/lib/x86_64-linux-gnu (this is for Ubuntu 24.04). Re: MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found When I make a symbolic link from libncursesw.so5->libnsursesw.so6, I get a new error: "Could not determine GDB version using command: arm-none-eabi-gdb --version arm-none-eabi-gdb: error while loading shared libraries: libtinfo.so.5: cannot open shared object file: No such file or directory" Re: MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found Hi @kk7xo  Based on your information,  arm-none-eabi-gdb (from older toolchains) was linked to libncursesw.so.5.   Ubuntu 24.04 moved forward to only libncursesw.so.6.   Can you try creating a fake symbol link to libncursesw. so. 6 ln -s libncursesw.so.6 libncursesw.so.5.   BR Harry Re: MCUXpresso V24.12 under Ubuntu 24.04 libncursesw.so.5 not found I'm not certain about this, but I think the problem is related to the version of Gnu tools that are bundled with MCUXpresso.  Apparently, gcc version 13 requires libncursesw.so.5, whereas gcc version 14 works with libncurses6.  Add to that the fact that the Ubuntu 24.04 distro does not include libncurses5.  This should be verified by someone at NXP before it is declared a valid fix.

[Security] Multiple Encryption/Decryption Interface Call Errors on D-Flash Dear NXPs: ARCH:S32K142 OS:None IDE：IAR arm 9.32.2 Bootloader- D-Flash-32K Background Reference：Solved: Re: [Security] D-Flash CSE driver encryption/decryption interface limitations - NXP Community CSEc Driver uses S32K SDK driver. After executing the encryption and decryption interface multiple times, a Hardfault error occurred. IHPRECISERR = 1 FORCED = 1 Test code:The encryption and decryption are called every 24ms, and a hardFault occurs after 42 executions. Q:It is speculated that it is related to the RAMization of the CSEC Driver function. How can I solve this problem? Re: [Security] Multiple Encryption/Decryption Interface Call Errors on D-Flash This matter has been resolved, this matter has been closed. Re: [Security] Multiple Encryption/Decryption Interface Call Errors on D-Flash Dear NXPS： After executing S32_SCB->ACTLR |= S32_SCB_ACTLR_DISDEFWBUF_MASK;, the Hardfault type is determined. Sat Jul 20, 2024 11:26:34: HardFault: Sat Jul 20, 2024 11:26:34: Forced escalated exception Sat Jul 20, 2024 11:26:34: BusFault fault: Sat Jul 20, 2024 11:26:34: Precise data error Sat Jul 20, 2024 11:26:34: BFAR is valid Sat Jul 20, 2024 11:26:34: Fault address BFAR: 0x12 Sat Jul 20, 2024 11:26:34: PC 0x10000b12 Sat Jul 20, 2024 11:26:34: SP 0x20002f50 Sat Jul 20, 2024 11:26:34: LR 0xffffffe9 Sat Jul 20, 2024 11:26:34: Vector table: 0x1fffc000 Sat Jul 20, 2024 11:26:34: Stopped by a vector catch: Sat Jul 20, 2024 11:26:34: BusFault fault escalated into HardFault Sat Jul 20, 2024 11:26:34: The BusFault handler is disabled Sat Jul 20, 2024 11:26:34: HardFault exception. Sat Jul 20, 2024 11:26:34: The processor has escalated a configurable-priority exception to HardFault. Sat Jul 20, 2024 11:26:34: Sat Jul 20, 2024 11:26:34: A precise data access error has occurred (CFSR.PRECISERR, BFAR) Sat Jul 20, 2024 11:26:34: At data address 0x12. Sat Jul 20, 2024 11:26:34: Sat Jul 20, 2024 11:26:34: Exception occurred at PC = 0x100012ce, LR = 0x10000ee1 Sat Jul 20, 2024 11:26:34: Sat Jul 20, 2024 11:26:34: See the call stack for more information. As mentioned above, looking forward to your help.

Changes in function ‘FLEXSPI_CheckAndClearError’ of from SDK2.9 to SDK2.16 for NXPRT1170 As the title says, in the SDK2.16 version of the MCU NXPRT1170 chip, compared with the SDK2.9 version, the Reset fifo processing has been deleted in the FLEXSPI_CheckAndClearError function of the fsl_flexspi.c file, but the reason for the deletion is unknown. Deleted Reset fifo processing code: base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; The FLEXSPI_CheckAndClearError function will check whether there is an error in the FLEXSPI_WriteBlocking, FLEXSPI_ReadBlocking and other functions. If an error is found, FLEXSPI_ClearInterruptStatusFlags(base, status); will be executed. I just don't know why the Reset fifo processing was deleted in SDK2.16? Re: Changes in function ‘FLEXSPI_CheckAndClearError’ of from SDK2.9 to SDK2.16 for NXPRT1170 Hi @mega32 , After confirming with experts that It is unnecessary to have FIFO cleaning in check and clean error, as Transfer(Non)Blocking clear the FIFOs prior each transfer. But for sure, clearing the FIFOs in case of an error removes any data (succesfully) received so far. It is being reset at the beginning. I do not say it is wrong, but it may be risky (error prone) to manipulate it in the middle of loops. We can see that before call this FLEXSPI_CheckAndClearError inside write or read blocking function, at the beginning of the FLEXSPI_TransferBlocking, it will reset the FIFO, so no need to reset it during the transfer process. Best regards, Gavin Re: Changes in function ‘FLEXSPI_CheckAndClearError’ of from SDK2.9 to SDK2.16 for NXPRT1170 Hi @mega32 , Thanks for your interest in NXP MIMXRT series! I need to internally confirm the reason for this modification, so please give some time. Thank you again for reporting this issue! Best regards, Gavin

LS1046A L1 および L2 キャッシュ ECC ECC は、LS1046A の L1 キャッシュと L2 キャッシュに対してデフォルトで有効になっていますか? この情報はレジスタL2CTLR_EL1に含まれていることは知っていますが、プログラムでこのレジスタにアクセスできるかどうか疑問に思います よろしくお願いいたします Re:LS1046A L1およびL2キャッシュECC こんにちは@Hector_Villarruel 、 ご返信ありがとうございます。L2CTLR_EL1 レジスタは、LS1046A リファレンス マニュアルに付属の ARM® Cortex-A72® MPCore プロセッサ TRM に示されています。いずれにせよ、ECCが常に有効になっていると述べていれば、そのようなレジスタをチェックする必要はなく、解決策としてあなたの返信を受け入れることができます 敬具

i.MX8ULP用eMMC使用に関するお問い合わせ i.MX8ULP Single Boot Modeのブートイメージの保存にeMMCを使用したいのですが。 ブートイメージを保存するeMMC領域を除いて、特定の空のメモリ領域があると思います。 特定の空のメモリ領域をアプリケーションのデータを保存する領域として使用できますか? eMMCは、データ保存用のフラッシュメモリだけでなく、ブートイメージ保存用のメモリも同時に使いたいです。

imx 6solo upgrade linux kernel to Linux 6.6.23_2.0.0？ HI All Our product uses the i.MX6Solo processor, and the original system is based on Linux kernel 4.9. We now need to upgrade to NXP's latest official release, Linux 6.6.36_2.1.0. As part of this upgrade, we also need to update Buildroot and U-Boot. Could you provide advice on which versions of Buildroot and U-Boot we should upgrade to? Alternatively, could you share any links or resources for reference? thanks！ regards jason i.MX6 All i.MX6SoloX Re: imx 6solo upgrade linux kernel to Linux 6.6.23_2.0.0？ thanks Re: imx 6solo upgrade linux kernel to Linux 6.6.23_2.0.0？ Hello, Yes, this will work. Best Regards, Zhiming Re: imx 6solo upgrade linux kernel to Linux 6.6.23_2.0.0？ my linux kernel version is : https://github.com/nxp-imx/linux-imx/tree/lf-6.6.36-2.1.0 my uboot version is https://github.com/nxp-imx/uboot-imx/tree/lf-6.6.36-2.1.0 is it ok? Re: imx 6solo upgrade linux kernel to Linux 6.6.23_2.0.0？ Hello, We can't recommend the buildroot version, you can use the L6.6.36 pair of uboot versions. https://github.com/nxp-imx/uboot-imx/tree/lf-6.6.36-2.1.0 Best Regards, Zhiming