Hello, I am using the S32K396 SDADC to measure two different frequencies of sine wave signals with the same peak-to-peak value, but the measured signals show varying degrees of attenuation. Specifically, when measuring a 1V 5kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1051/32768)×5=0.16V(1051/32768)×5=0.16V. When measuring a 1V 3kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1691/32768)×5=0.26V(1691/32768)×5=0.26V. My software configuration and code are as follows.
Here are my configuration and code.
/*==================================================================================================
* INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Clock_Ip.h"
#include "Sdadc_Ip.h"
#include "check_example.h"
#include "Siul2_Port_Ip.h"
#include "Siul2_Dio_Ip.h"
#include "IntCtrl_Ip.h"
#include "SGEN_conf.h"
/*==================================================================================================
* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/
/*==================================================================================================
* LOCAL MACROS
==================================================================================================*/
#define SDADC_INSTANCE_USED 0U /* The SDADC hardware instance used in the example */
#define DMA_CHANNEL_USED DMA_LOGIC_CH_0 /* The DMA logical channel used in the example */
#define NUM_SAMPLES 16U
#define GET_COMPLEMENT_OF_2(x) ((uint32)(~((uint32)(x)) + 1U))
#define SDADC_INVALID_DATA 0xFFFF
sint16 data[1700];
sint16 cali_data[1700];
uint16 cnt_data =0;
uint32 sfr_data=0;
#define SDADC_0 0U
/*==================================================================================================
* LOCAL CONSTANTS
==================================================================================================*/
/*==================================================================================================
* LOCAL VARIABLES
==================================================================================================*/
#define ADC_START_SEC_VAR_CLEARED_16_NO_CACHEABLE
#include "Adc_MemMap.h"
static volatile uint16_t ResultsBuffer[NUM_SAMPLES + 1U]; /* Plus 1 to check for overflow */
#define ADC_STOP_SEC_VAR_CLEARED_16_NO_CACHEABLE
#include "Adc_MemMap.h"
/*==================================================================================================
* GLOBAL CONSTANTS
==================================================================================================*/
/*==================================================================================================
* GLOBAL VARIABLES
==================================================================================================*/
/*==================================================================================================
* LOCAL FUNCTION PROTOTYPES
==================================================================================================*/
void fifo_notification(void);
/*==================================================================================================
* LOCAL FUNCTIONS
==================================================================================================*/
void fifo_notification(void)
{
//Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 1U);
Sdadc_Ip_GetConvData(SDADC_INSTANCE_USED,13,&data[cnt_data]);
//Sdadc_Ip_ApplyCalibration(SDADC_0,7,&data[cnt_data],&cali_data[cnt_data]);
//Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U);
cnt_data+=13;
if(cnt_data >= 1680)
{
sfr_data=Sdadc_Ip_GetStatusFlags(SDADC_INSTANCE_USED);
Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U);
}
}
int main(void)
{
/* Initialize clock driver */
Clock_Ip_Init(Clock_Ip_aClockConfig);
Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);
Siul2_Dio_Ip_WritePin(LED_PORT, LED_PIN, 0U);
SGEN_init_M1(3,8,SWG_TRIG_SW);
IntCtrl_Ip_Init(&IntCtrlConfig_0);
/* Initialize SDADC driver */
Sdadc_Ip_EnableInterruptEvents(SDADC_INSTANCE_USED,1);
Sdadc_Ip_Init(SDADC_INSTANCE_USED, &SdadcIpConfig_0);
// Sdadc_Ip_DoCalibration(SDADC_0);
/* Start DSPSS thread and SDADC conversion */
Sdadc_Ip_ReloadConversion(SDADC_INSTANCE_USED);
/* Wait until buffer is full: the last element was written by DMA */
while (1)
{
// Sdadc_Ip_SwTriggerConversion(SDADC_INSTANCE_USED);
}
}
I used the SDADC's FIFO interrupt to transfer the collected data to the data array, and the FIR filtering is not enabled in the SDADC. I measured a 1V 3kHz sine signal and a 1V 5kHz sine signal, and the obtained data arrays are plotted in the following images.
when measuring a 1V 5kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1051/32768)×5=0.16V(1051/32768)×5=0.16V. When measuring a 1V 3kHz sine signal, the peak-to-peak value obtained from the SDADC conversion is (1691/32768)×5=0.26V(1691/32768)×5=0.26V.
Could you please let me know if there is any configuration error?
Thank you for your reply. , I'll to to contact my NXP representative.
Hi again,
I'm glad to read that you have found the reason for the signal attenuation.
Regarding your issue with enabling FIR filter, I note you are using a board that is no available in the NXP page, which do not allow me to debug your issue on my side.
Is this issue is reproducible in the S32K396-BGA-DC1? If so, how?
If not, I'll need to ask you to contact your NXP representative or whoever provided you with the S32K396-LQFP-DC to follow up with your issue please. An apology for the inconvenience.
Have a nice day!
@_Leo_ ，Thank you for your reply. I found the reason for the signal attenuation; it is caused by the low-pass filter circuit in the signal input circuit. The development board I am using is the S32K396-LQFP-DC, and the filter circuit for the SDADC0 AN0 and AN1 channels is shown in the figure below.
Now, I am testing the AN_2 and AN_3 channels of SDADC0, and the input circuit is shown in the figure below：
I used the SDADC's FIFO interrupt to transfer the collected data to the data array, and the FIR filtering is not enabled in the SDADC. I measured a 2V 10kHz sine signal , and the obtained data arrays are plotted in the following images.
In this case, the SDADC works well; however, after enabling the FIR filter, the output data has issues. The conversion data read after filtering seems incomplete, and there is an abnormal downward offset in the signal, as shown in the figure below.
The schematic and code files for the development board are shown below.
Hi,
Thank you so much for your interest in our products and for using our community.
Please share your complete project in a zip, as we as HW (board connections) & SW (IDE and RTD versions) installation details in order to reproduce your issue from our side, like plug & play. Feel free to share any details to speed up the test and therefore the resolution of the problem.
Have a nice day!