GMAC0 in MII mode on s32g2 not getting the clk Hi All, We are working on a custom hardware platform based on s32g2. where we are trying to make GMAC0 Eth communication working. GMAC0 is connected to external PHY "DP83848Q" as in the attached schematic section: The DTS setting is as: &gmac0 { status = "okay"; clocks = <&clks S32CC_SCMI_CLK_GMAC0_AXI>, <&clks S32CC_SCMI_CLK_GMAC0_RX_MII>, <&clks S32CC_SCMI_CLK_GMAC0_TX_MII>; clock-names = "stmmaceth","rx_mii","tx_mii"; phy-interface-type = "mii"; pinctrl-names = "gmac_mii","gmac_mii"; pinctrl-0 = <&gmac0miic_pins>,<&gmac0mdioc_pins>; phy-mode = "mii"; phy-handle = <&gmac_mdio_a_phy1>; fixed-link { speed = <100>; full-duplex; }; }; &gmac0_mdio { status = "okay"; compatible = "snps,dwmac-mdio"; #address-cells = <0x01>; #size-cells = <0x00>; /* DP83848Q */ gmac_mdio_a_phy1: ethernet-phy@3 { device_type = "ethernet-phy"; compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x01>; ref-clock = <0x17d7840>; max-speed = <100>; full-duplex; }; gmac0mdioc_pins: gmac0mdioc_pins { gmac0mdioc_grp0 { pinmux = ; output-enable; slew-rate = ; }; gmac0mdioc_grp1 { pinmux = ; output-enable; input-enable; slew-rate = ; }; gmac0mdioc_grp2 { pinmux = ; }; }; gmac0miic_pins: gmac0miic_pins { gmac0miic_grp0 { pinmux = , , , , ; output-enable; slew-rate = ; }; gmac0miic_grp1 { pinmux = , , , , , , , , ; input-enable; slew-rate = ; }; gmac0miic_grp2 { pinmux = ; input-enable; bias-pull-up; }; gmac0miic_grp3 { pinmux = , , , , , , , , , ; }; }; ----------------------------------------------------------------------- hwconfig is " serdes0:mode=xpcs0&xpcs1,clock=int,skip=boot,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G The debug output shows that the clocks are not getting generated: dmesg | grep eth [ 0.000000] psci: probing for conduit method from DT. [ 2.409826] UDC core: g_ether: couldn't find an available UDC [ 2.561437] s32cc-dwmac 4033c000.ethernet: IRQ eth_wake_irq not found [ 2.561450] s32cc-dwmac 4033c000.ethernet: IRQ eth_lpi not found [ 2.561667] s32cc-dwmac 4033c000.ethernet: PTP uses main clock [ 2.561816] s32cc-dwmac 4033c000.ethernet: Can't set tx clock [ 2.561824] s32cc-dwmac: probe of 4033c000.ethernet failed with error -5 [ 5.174441] pfeng 46000000.pfe: PFEng ethernet driver loading ... cat /sys/kernel/debug/clk/clk_summary | grep gmac0_axi gmac0_axi 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep gmac0 gmac0_axi 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_rgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_rgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_ts 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep gmac0_axi gmac0_axi 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id Re: GMAC0 in MII mode on s32g2 not getting the clk hi @Joey_z Ok, thanks ... Looking for resolution soon. Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Sorry for the reply late.
I have known you post a new private ticket; we will continue to support you on it.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply.
I know that you used the customer board and the PHY not on our development board, so I cannot be easy to reset your hardware and help you to test.
I will discuss with the internal expert team to check if there are any other ways to help you.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk Hi Joey_z, >>>> Do you mean that you can use the MII mode of GMAC0 normally during using BSP38? yes >>> Which content of GMAC0 has been changed in BSP38 for your hardware? That we dont know because we dont have the sources/patch with us. What we have is only DTS file and we are expecting that with DTS change things should work, we are not expecting to hack the kernel code to make MII mode of GMAC0 to work and if that is the case we need NXP to support here because we are using BSP & SoC of NXP's Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply and the information.
Do you mean that you can use the MII mode of GMAC0 normally during using BSP38?
Which content of GMAC0 has been changed in BSP38 for your hardware? You can try to find those modified contents of BSP38 and refer to it to modify the BSP43. Mainly follow the content of dts/ATF/Kernel about GMAC0.
BR
Joey
Re: GMAC0 in MII mode on s32g2 not getting the clk Hello Joey_z The hardware we are using is enclosed one, its difficult to probe the signals. Moreover it is a working hardware using Linux BSP38. With the current BSP43 we are getting this issue. Regards, Misbah Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Sorry for the reply late.
Thank you for your detail information, I will help you to check it.
Also, could you use an oscilloscope to test the external clock of MII? Check if it is normal.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk Hi @Joey_z The below change you suggested is for bootloader, but we need the change in linux kernel, I tried to hardcode in "stmmac/dwmac-s32cc.c" the RX & TX clock to 25Mhz but it didnt solved the issue. Please suggest as how shall we proceed to make the below change to get the Rx clock configured for 25Mhz cat /sys/kernel/debug/clk/clk_summary | grep gmac0 gmac0_axi 2 2 0 400000000 0 0 50000 Y 4033c000.ethernet pclk gmac0_tx_mii 1 1 0 25000000 0 0 50000 Y 4033c000.ethernet tx_mii gmac0_rx_mii 1 1 0 125000000 0 0 50000 Y 4033c000.ethernet rx_mii Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply.
Try to remove the GMAC0 MII clock in your configuration.
&gmac0 { status = "okay"; phy-mode = "mii"; clocks = <&clks S32CC_SCMI_CLK_GMAC0_AXI>, <&clks S32CC_SCMI_CLK_GMAC0_RX_MII>, <&clks S32CC_SCMI_CLK_GMAC0_TX_MII>; clock-names = "stmmaceth", "rx_mii", "tx_mii"; phy-interface-type = "mii"; pinctrl-names = "gmac_mii","gmac_mii"; pinctrl-0 = <&gmac0mii_pins>,<&gmac0mdio_pins>; pinctrl-1 = <&gmac0mdio_pins>; phy-handle = <&mdio_a_phy3>;
fixed-link { speed = <100>; full-duplex; };
};
Also, you can try to modify the file of dtb to limit the clock to 25Mhz.
I hope your problem can be solved. I'm sorry that I have to take a vacation of over a week. If your problem still exists, you can create a new ticket and my colleagues will provide you with support, or wait for me to come back.
BR
Joey
Re: GMAC0 in MII mode on s32g2 not getting the clk Hi @Joey_z, The device tree entry in the ATS is as: &gmac0 { status = "okay"; phy-mode = "mii"; clocks = <&clks S32CC_SCMI_CLK_GMAC0_AXI>, <&clks S32CC_SCMI_CLK_GMAC0_RX_MII>, <&clks S32CC_SCMI_CLK_GMAC0_TX_MII>; clock-names = "stmmaceth", "rx_mii", "tx_mii"; phy-interface-type = "mii"; pinctrl-names = "gmac_mii","gmac_mii"; pinctrl-0 = <&gmac0mii_pins>,<&gmac0mdio_pins>; pinctrl-1 = <&gmac0mdio_pins>; phy-handle = <&mdio_a_phy3>; fixed-link { speed = <100>; full-duplex; }; }; &gmac0_mdio { mdio_a_phy3: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; ref-clock = <0x17d7840>; max-speed = <100>; full-duplex; }; }; What additional setting is needed to get the clk in u-boot for gmac0 ? "2. About your log, I can find the clock of MII has been configured in kernel, it is a good thing, you can try to set the gmac0_rx_mii to 25MHz." How shall i configure the gmac0_rx_mii to 25MHz ? Is it by hwconfig or dts ? Can you suggest Re: GMAC0 in MII mode on s32g2 not getting the clk hi，khan_misbah
Thank you for your reply and information.
1.Dose the clock configuration from ATF as below? I think you need not to use the SCMI for setting MII clock, the clock of MII from external PHY.
clocks = <&clks S32CC_SCMI_CLK_GMAC0_AXI>, <&clks S32CC_SCMI_CLK_GMAC0_RX_MII>, <&clks S32CC_SCMI_CLK_GMAC0_TX_MII>; clock-names = "stmmaceth", "rx_mii", "tx_mii";
2. About your log, I can find the clock of MII has been configured in kernel, it is a good thing, you can try to set the gmac0_rx_mii to 25MHz.
root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep gmac0 gmac0_axi 1 1 0 400000000 0 0 50000 Y 4033c000.ethernet stmmaceth gmac0_tx_mii 1 1 0 25000000 0 0 50000 Y 4033c000.ethernet tx_mii gmac0_rx_mii 1 1 0 125000000 0 0 50000 Y 4033c000.ethernet rx_mii
Hope this can help you.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk Hi @Joey_z The clock is getting generated by PHY (TX & RX) pls check the schematic section : Following is my DTS setting: &gmac0 { status = "okay"; phy-mode = "mii"; clocks = <&clks S32CC_SCMI_CLK_GMAC0_AXI>, <&clks S32CC_SCMI_CLK_GMAC0_RX_MII>, <&clks S32CC_SCMI_CLK_GMAC0_TX_MII>; clock-names = "stmmaceth", "rx_mii", "tx_mii"; phy-interface-type = "mii"; pinctrl-names = "gmac_mii","gmac_mii"; pinctrl-0 = <&gmac0mii_pins>,<&gmac0mdio_pins>; pinctrl-1 = <&gmac0mdio_pins>; phy-handle = <&mdio_a_phy3>; fixed-link { speed = <100>; full-duplex; }; }; &gmac0_mdio { mdio_a_phy3: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; ref-clock = <0x17d7840>; max-speed = <100>; full-duplex; }; }; --------------------------------------------------------------- getting the error in u-boot as: clk_enable(clk_rx) failed: -71 eth_eqos ethernet@4033c000: Failed to start clocks (err=-71) eqos_start_clks() failed: -71 What is missing so that gmac0 is not getting the clk: 14| GMAC_0_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015 15| GMAC_TS | FXOSC | 5.000 - 200.000 | 0.000 - 0.015 16| LIN | FXOSC | 125.000 | 62.500 17| QSPI_1X | FXOSC | 0.000 - 200.000 | 199.218 18| SDHC | FXOSC | 400.000 | 398.437 20| DDR | FIRC | 666.666 | 812.500 21| GMAC_0_RX | FXOSC | 2.500 - 125.000 | 47.851 While in the kernel i don't see this error & eth0 node is getting created as: Although ping is not working. But need to fix the issue in u-boot first. root@s32g2-vcup-platform:~# cat /sys/kernel/debug/clk/clk_summary | grep gmac0 gmac0_axi 1 1 0 400000000 0 0 50000 Y 4033c000.ethernet stmmaceth gmac0_tx_mii 1 1 0 25000000 0 0 50000 Y 4033c000.ethernet tx_mii gmac0_rx_mii 1 1 0 125000000 0 0 50000 Y 4033c000.ethernet rx_mii gmac0_tx_rmii 0 0 0 25000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_rgmii 0 0 0 25000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_rgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_tx_sgmii 0 0 0 25000000 0 0 50000 Y deviceless no_connection_id gmac0_rx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id gmac0_ts 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply and informaion.
Refer to your log, the clock is not correctly setting thought the external PHY.
1.About the GMAC0, your pin using is correct.
2.You can try to check the clock the PHY clock, make sure the TX/RX from the PHY and useful.
Hope this can help you.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk Hi Joey, For your reference ... -------------------------- mdio list pfeng-mdio-1: 1b - Generic PHY <--> pfe1 pfeng-mdio-2: 1b - Generic PHY <--> pfe2 => mii info PHY 0x1B: OUI = 0x06EC, Model = 0x03, Rev = 0x01, 10baseT, HDX => ver verifclk version => verifclk CMU | Monitored | Reference | Expected | Verified ID | clock | clock | range (MHz) | range (MHz) -----|--------------|-----------|---------------------|-------------------- 0| FXOSC | FIRC | 40.000 | 39.062 1| FIRC | FXOSC | 45.600 - 50.400 | 48.080 2| SIRC | FXOSC | 0.032 | 0.031 Timeout while measuring the frequency of FTM_0_REF 3| FTM_0_REF | FXOSC | 40.000 | 0.000 Timeout while measuring the frequency of FTM_1_REF 4| FTM_1_REF | FXOSC | 40.000 | 0.000 5| XBAR_DIV3 | FIRC | 133.333 | 132.812 6| XBAR_M7_0 | FIRC | 400.000 | 406.250 7| XBAR_DIV3 | FXOSC | 133.333 | 132.812 8| XBAR_M7_1 | FIRC | 400.000 | 406.250 9| XBAR_M7_2 | FIRC | 400.000 | 406.250 10| PER | FIRC | 80.000 | 78.125 11| SERDES_REF | FXOSC | 100.000 - 125.000 | 99.609 12| FLEXRAY_PE | FXOSC | 40.000 | 0.000 - 0.015 13| CAN_PE | FXOSC | 80.000 | 47.851 14| GMAC_0_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015 15| GMAC_TS | FXOSC | 5.000 - 200.000 | 0.000 - 0.015 16| LIN | FXOSC | 125.000 | 62.500 17| QSPI_1X | FXOSC | 0.000 - 200.000 | 199.218 18| SDHC | FXOSC | 400.000 | 398.437 20| DDR | FIRC | 666.666 | 812.500 21| GMAC_0_RX | FXOSC | 2.500 - 125.000 | 47.851 22| SPI | FXOSC | 100.000 | 47.851 27| A53_CORE | FXOSC | 1000.000 | 1000.000 28| A53_CORE | FIRC | 1000.000 | 1000.000 39| PFE_SYS | FXOSC | 300.000 | 300.781 46| PFE_MAC_0_TX | FXOSC | 2.500 - 312.500 | 0.000 - 0.015 47| PFE_MAC_0_RX | FXOSC | 2.500 - 312.500 | 47.851 48| PFE_MAC_1_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015 49| PFE_MAC_1_RX | FXOSC | 2.500 - 125.000 | 47.851 50| PFE_MAC_2_TX | FXOSC | 2.500 - 125.000 | 0.000 - 0.015 51| PFE_MAC_2_RX | FXOSC | 2.500 - 125.000 | 47.851 Re: GMAC0 in MII mode on s32g2 not getting the clk Hi Joey, I made the following change: mc_cgm6: mc_cgm6@4053c000 { compatible = "nxp,s32cc-mc_cgm6"; reg = <0x0 0x4053c000 0x0 0x3000>; assigned-clocks = <&plat_clks S32G_CLK_MC_CGM6_MUX0>, <&plat_clks S32G_CLK_MC_CGM6_MUX1>, <&plat_clks S32G_CLK_MC_CGM6_MUX2>, <&plat_clks S32GEN1_CLK_GMAC0_TS>; assigned-clock-parents = <&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI4>, //<&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI5>, <&plat_clks S32GEN1_CLK_GMAC0_EXT_TX>, <&plat_clks S32GEN1_CLK_GMAC0_EXT_RX>; assigned-clock-rates = <0>, <0>, <0>, <200000000>; }; Now i am getting error in RX clock as: Net: Enable protocol@14 failed clk_enable(clk_rx) failed: -71 eth_eqos ethernet@4033c000: Failed to start clocks (err=-71) eqos_start_clks() failed: -71 Found PFE version 0x50300 (S32G2) Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you reply and more information.
If you set the GMAC0 as the MII mode, you should use the ext clock for GMAC0_TX_CLK.
Please check your GMAC0 clock setting, the MUX1 of CGM6 should chose the ext clk.
About the file of s32g3.dtsi, you can try to modify the cgm6 configuration.
Hope this can help you.
BR
Joey
Re: GMAC0 in MII mode on s32g2 not getting the clk Hello Joey_z Please find the log for the u-boot command executed as below: ---------------------------------------------------------------------------- DRAM: 3.5 GiB Inside dm_init_and_scan............ PFE2 PHY reset PFE1 PHY reset GMAC0 PHY reset PFE0 RX enable Core: 314 devices, 25 uclasses, devicetree: board MMC: FSL_SDHC: 0 Loading Environment from SPIFlash... SF: Detected mt35xu01gbba with page size 256 Bytes, erase size 4 KiB, total 128 MiB *** Warning - bad CRC, using default environment Failed to configure XPCS0_1 Failed to update XPCS1 for SerDes0 Failed to configure XPCS1_1 Failed to update XPCS1 for SerDes1 In: serial@401c8000 Out: serial@401c8000 Err: serial@401c8000 Board revision: RDB2 Net: Enable protocol@14 failed clk_enable(clk_rx) failed: -71 eth_eqos ethernet@4033c000: Failed to start clocks (err=-71) eqos_start_clks() failed: -71 Found PFE version 0x50300 (S32G2) pfeng pfeng-base: Uploading CLASS firmware pfeng pfeng-base: EMAC0 block was initialized pfeng pfeng-base: EMAC1 block was initialized pfeng pfeng-base: EMAC2 block was initialized pfeng pfeng-base: Enabling the CLASS block pfeng pfeng-base: PFE Platform started successfully (mask: 7) eth1: pfe0s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem s32cc_serdes_phy serdes@44180000: Stable RX detected on XPCS1 after 0 µs , eth2: pfe1s32cc_serdes_phy serdes@40480000: Using mode 3 for SerDes subsystem s32cc_serdes_phy serdes@40480000: Stable RX detected on XPCS1 after 1 µs , eth3: pfe2 Hit any key to stop autoboot: 0 => clk dump Rate Usecnt Name ------------------------------------------ 40000000 0 |-- fxosc@40050000 51000000 0 |-- firc 32000 0 |-- sirc 20000000 0 |-- ftm0_ext 20000000 0 |-- ftm1_ext 125000000 0 |-- gmac0_ext_rx 125000000 0 |-- gmac0_ext_tx 50000000 0 |-- gmac0_rmii_ref 200000000 0 |-- gmac0_ext_ts 100000000 0 |-- serdes_100_ext 125000000 0 |-- serdes_125_ext 125000000 0 |-- serdes0_lane0_ext_cdr 125000000 0 |-- serdes0_lane0_ext_tx 125000000 0 |-- serdes0_lane1_ext_cdr 125000000 0 |-- serdes0_lane1_ext_tx 125000000 0 |-- serdes1_lane0_ext_cdr 125000000 0 |-- serdes1_lane0_ext_tx 125000000 0 |-- serdes1_lane1_ext_cdr 125000000 0 |-- serdes1_lane1_ext_tx 1 0 |-- pfe_mac0_rmii 1 0 |-- pfe_mac1_rmii 1 0 |-- pfe_mac2_rmii 1000000000 0 |-- a53 400000000 2 |-- serdes_axi 51000000 2 |-- serdes_aux 133333333 2 |-- serdes_apb 100000000 2 |-- serdes_ref 80000000 0 |-- ftm0_sys 40000000 0 |-- ftm0_ext 80000000 0 |-- ftm1_sys 40000000 0 |-- ftm1_ext 133333333 0 |-- flexcan_reg 133333333 0 |-- flexcan_sys 80000000 0 |-- flexcan_can 200000000 0 |-- flexcan_ts 62500000 0 |-- linflex_xbar 125000000 1 |-- linflex_lin 0 0 |-- gmac0_ts 125000000 0 |-- gmac0_rx_sgmii 0 0 |-- gmac0_tx_sgmii 125000000 0 |-- gmac0_rx_rgmii 0 0 |-- gmac0_tx_rgmii 125000000 0 |-- gmac0_rx_rmii 0 0 |-- gmac0_tx_rmii 125000000 0 |-- gmac0_rx_mii 0 0 |-- gmac0_tx_mii 400000000 0 |-- gmac0_axi 100000000 0 |-- spi_reg 100000000 0 |-- spi_module 133333333 0 |-- qspi_reg 133333333 0 |-- qspi_ahb 400000000 0 |-- qspi_flash2x 200000000 2 |-- qspi_flash1x 400000000 0 |-- usdhc_ahb 133333333 0 |-- usdhc_module 400000000 1 |-- usdhc_core 32000 0 |-- usdhc_mod32k 133333333 0 |-- ddr_reg 800000000 0 |-- ddr_pll_ref 800000000 0 |-- ddr_axi 400000000 0 |-- sram_axi 133333333 0 |-- sram_reg 133333333 0 |-- i2c_reg 133333333 0 |-- i2c_module 66666666 0 |-- siul2_reg 51000000 0 |-- siul2_filter 133333333 0 |-- crc_reg 133333333 0 |-- crc_module 100000000 0 |-- eim0_reg 100000000 0 |-- eim0_module 66666666 0 |-- eim123_reg 66666666 0 |-- eim123_module 66666666 0 |-- eim_reg 66666666 0 |-- eim_module 66666666 0 |-- fccu_module 51000000 0 |-- fccu_safe 66666666 0 |-- rtc_reg 32000 0 |-- rtc_sirc 51000000 0 |-- rtc_firc 133333333 0 |-- swt_module 51000000 0 |-- swt_counter 133333333 0 |-- stm_module 133333333 0 |-- stm_reg 133333333 0 |-- pit_module 133333333 0 |-- pit_reg 400000000 0 |-- edma_module 400000000 0 |-- edma_ahb 80000000 1 |-- sar_adc_bus 66666666 0 |-- cmu_module 66666666 0 |-- cmu_reg 133333333 0 |-- tmu_module 133333333 0 |-- tmu_reg 133333333 0 |-- flexray_reg 0 0 |-- flexray_pe 66666666 0 |-- wkpu_module 66666666 0 |-- wkpu_reg 66666666 0 |-- src_module 66666666 0 |-- src_reg 66666666 0 |-- src_top_module 66666666 0 |-- src_top_reg 133333333 0 |-- ctu_module 80000000 0 |-- ctu_ctu 200000000 0 |-- dbg_sys4 400000000 0 |-- dbg_sys2 400000000 0 |-- m7 133333333 0 |-- dmamux_module 133333333 0 |-- dmamux_reg 500000000 0 |-- gic_module 133333333 0 |-- mscm_module 133333333 0 |-- mscm_reg 133333333 0 |-- sema42_module 133333333 0 |-- sema42_reg 66666666 0 |-- xrdc_module 66666666 0 |-- xrdc_reg 0 0 |-- clkout0 0 0 |-- clkout1 100000000 0 |-- usb_mem 32000 0 |-- usb_low 0 0 |-- pfe0_rx_sgmii 0 0 |-- pfe0_tx_sgmii 0 0 |-- pfe0_rx_rgmii 0 0 |-- pfe0_tx_rgmii 0 0 |-- pfe0_rx_rmii 0 0 |-- pfe0_tx_rmii 0 0 |-- pfe0_rx_mii 0 0 |-- pfe0_tx_mii 0 0 |-- pfe1_rx_sgmii 0 0 |-- pfe1_tx_sgmii 0 0 |-- pfe1_rx_rgmii 0 0 |-- pfe1_tx_rgmii 0 0 |-- pfe1_rx_rmii 0 0 |-- pfe1_tx_rmii 0 0 |-- pfe1_rx_mii 0 0 |-- pfe1_tx_mii 0 0 |-- pfe2_rx_sgmii 0 0 |-- pfe2_tx_sgmii 0 0 |-- pfe2_rx_rgmii 0 0 |-- pfe2_tx_rgmii 0 0 |-- pfe2_rx_rmii 0 0 |-- pfe2_tx_rmii 0 0 |-- pfe2_rx_mii 0 0 |-- pfe2_tx_mii 300000000 1 |-- pfe_axi 300000000 0 |-- pfe_apb 600000000 1 |-- pfe_pe 0 0 |-- pfe_ts 80000000 0 |-- llce_can_pe 200000000 0 |-- llce_sys 80000000 0 `-- llce_per 1000000000 0 |-- a53 400000000 2 |-- serdes_axi 51000000 2 |-- serdes_aux 133333333 2 |-- serdes_apb 100000000 2 |-- serdes_ref 80000000 0 |-- ftm0_sys 40000000 0 |-- ftm0_ext 80000000 0 |-- ftm1_sys 40000000 0 |-- ftm1_ext 133333333 0 |-- flexcan_reg 133333333 0 |-- flexcan_sys 80000000 0 |-- flexcan_can 200000000 0 |-- flexcan_ts 62500000 0 |-- linflex_xbar 125000000 1 |-- linflex_lin 0 0 |-- gmac0_ts 125000000 0 |-- gmac0_rx_sgmii 0 0 |-- gmac0_tx_sgmii 125000000 0 |-- gmac0_rx_rgmii 0 0 |-- gmac0_tx_rgmii 125000000 0 |-- gmac0_rx_rmii 0 0 |-- gmac0_tx_rmii 125000000 0 |-- gmac0_rx_mii 0 0 |-- gmac0_tx_mii 400000000 0 |-- gmac0_axi 100000000 0 |-- spi_reg 100000000 0 |-- spi_module 133333333 0 |-- qspi_reg 133333333 0 |-- qspi_ahb 400000000 0 |-- qspi_flash2x 200000000 2 |-- qspi_flash1x 400000000 0 |-- usdhc_ahb 133333333 0 |-- usdhc_module 400000000 1 |-- usdhc_core 32000 0 |-- usdhc_mod32k 133333333 0 |-- ddr_reg 800000000 0 |-- ddr_pll_ref 800000000 0 |-- ddr_axi 400000000 0 |-- sram_axi 133333333 0 |-- sram_reg 133333333 0 |-- i2c_reg 133333333 0 |-- i2c_module 66666666 0 |-- siul2_reg 51000000 0 |-- siul2_filter 133333333 0 |-- crc_reg 133333333 0 |-- crc_module 100000000 0 |-- eim0_reg 100000000 0 |-- eim0_module 66666666 0 |-- eim123_reg 66666666 0 |-- eim123_module 66666666 0 |-- eim_reg 66666666 0 |-- eim_module 66666666 0 |-- fccu_module 51000000 0 |-- fccu_safe 66666666 0 |-- rtc_reg 32000 0 |-- rtc_sirc 51000000 0 |-- rtc_firc 133333333 0 |-- swt_module 51000000 0 |-- swt_counter 133333333 0 |-- stm_module 133333333 0 |-- stm_reg 133333333 0 |-- pit_module 133333333 0 |-- pit_reg 400000000 0 |-- edma_module 400000000 0 |-- edma_ahb 80000000 1 |-- sar_adc_bus 66666666 0 |-- cmu_module 66666666 0 |-- cmu_reg 133333333 0 |-- tmu_module 133333333 0 |-- tmu_reg 133333333 0 |-- flexray_reg 0 0 |-- flexray_pe 66666666 0 |-- wkpu_module 66666666 0 |-- wkpu_reg 66666666 0 |-- src_module 66666666 0 |-- src_reg 66666666 0 |-- src_top_module 66666666 0 |-- src_top_reg 133333333 0 |-- ctu_module 80000000 0 |-- ctu_ctu 200000000 0 |-- dbg_sys4 400000000 0 |-- dbg_sys2 400000000 0 |-- m7 133333333 0 |-- dmamux_module 133333333 0 |-- dmamux_reg 500000000 0 |-- gic_module 133333333 0 |-- mscm_module 133333333 0 |-- mscm_reg 133333333 0 |-- sema42_module 133333333 0 |-- sema42_reg 66666666 0 |-- xrdc_module 66666666 0 |-- xrdc_reg 0 0 |-- clkout0 0 0 |-- clkout1 100000000 0 |-- usb_mem 32000 0 |-- usb_low 0 0 |-- pfe0_rx_sgmii 0 0 |-- pfe0_tx_sgmii 0 0 |-- pfe0_rx_rgmii 0 0 |-- pfe0_tx_rgmii 0 0 |-- pfe0_rx_rmii 0 0 |-- pfe0_tx_rmii 0 0 |-- pfe0_rx_mii 0 0 |-- pfe0_tx_mii 0 0 |-- pfe1_rx_sgmii 0 0 |-- pfe1_tx_sgmii 0 0 |-- pfe1_rx_rgmii 0 0 |-- pfe1_tx_rgmii 0 0 |-- pfe1_rx_rmii 0 0 |-- pfe1_tx_rmii 0 0 |-- pfe1_rx_mii 0 0 |-- pfe1_tx_mii 0 0 |-- pfe2_rx_sgmii 0 0 |-- pfe2_tx_sgmii 0 0 |-- pfe2_rx_rgmii 0 0 |-- pfe2_tx_rgmii 0 0 |-- pfe2_rx_rmii 0 0 |-- pfe2_tx_rmii 0 0 |-- pfe2_rx_mii 0 0 |-- pfe2_tx_mii 300000000 1 |-- pfe_axi 300000000 0 |-- pfe_apb 600000000 1 |-- pfe_pe 0 0 |-- pfe_ts 80000000 0 |-- llce_can_pe 200000000 0 |-- llce_sys 80000000 0 |-- llce_per => => print hwconfig hwconfig=serdes0:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs0_1:speed=1G;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_1:speed=1G; => mii info PHY 0x1B: OUI = 0x06EC, Model = 0x03, Rev = 0x01, 10baseT, HDX => mdio list pfeng-mdio-1: 1b - Generic PHY <--> pfe1 pfeng-mdio-2: 1b - Generic PHY <--> pfe2 => Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply.
Refer to you Kernel log, the Gmac0 do not connect with PHY.
Could you test the GMAC0 function in uboot and provide more information to us.
1.Check the GMAC0 clock in uboot to use the command of clk dump.
=> dump clk
2.Check the PHY of connection state with GMAC0, using the command of mii infro and mdio list in uboot.
=> print hwconfig
=> mii infro
=> mdio list
3.If connect GMAC0 with PHY successfully, could you please set Ip to Gmac0 and test the ping function.
BR
Joey Re: GMAC0 in MII mode on s32g2 not getting the clk Hello, We are using Linux BSP43 running on A53 core as OS. We are not running M7 . Re: GMAC0 in MII mode on s32g2 not getting the clk hi,khan_misbah
Thank you for your reply.
Which version of BSP are you using? And do you use the multi-core or only A core？
BR
Joey
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