Clarification on MCAL portpin Id Hi Team, We are configuring the port module during that PortPin Id has been assigning, From the user manual value will be assigned to the symbolic name what exactly does it mean? Since the S32K322 PTE6 is 84 pin in the microcontroller but portpin Id is showing in the MCAL configuration has 66? Please do clarify the same.   Re: Clarification on MCAL portpin Id Hi @Thiru2483  The PortPin Id parameter in the Port driver configuration is simply an internal numerical identifier that becomes associated with a symbolic name. Its value is assigned automatically in the order in which you configure the pins, starting from 1 and increasing sequentially. This number does not match the actual physical pin on the MCU. BR, VaneB

RT1064 GUI-Guider LVGL 性能调整 我们有一款基于 MIMXRT1064-EVK 设计的产品。我们使用 GUI-Guider 设计基于 LVGL 的应用程序，与 GUI-Guider 示例项目使用的屏幕类型相同。我们正在努力寻找性能改进方法，并看到了这篇关于可提高性能的系统级更改的文章： https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/LVGL-Benchmark-Performance-Optimization/ta-p/2252208。除此以外，是否还可以调整 LVGL 配置设置以提高性能？ 我们注意到，在基于 GUI-Guider 生成的项目的项目中，即使屏幕是静态的，不需要更新 GUI 元素，LVGL 性能监测器报告的 CPU 使用率也相当高。有没有任何 LVGL 设置可以减少重绘的次数？ Re: RT1064 GUI-Guider LVGL performance tweaks 嗨，@aanderson-eemn、 GUI 指南用户指南（GUIGU IDERUG_1.10.1：GUI Guider v1.10.1 用户指南 | 恩智浦半导体）有关于性能优化的特定章节，但您之前分享的知识库文章已经探讨了大多数建议。我建议遵循这两份文档，以提高 LVGL 应用程序的性能。 BR, Edwin. Re: RT1064 GUI-Guider LVGL performance tweaks @EdwinHz谢谢你的建议。我们发现在同步动态随机存取存储器(SDRAM)中运行应用程序可以显著提高性能，但是我在生成从同步动态随机存取存储器(SDRAM)运行应用程序的十六进制文件时遇到了很多问题。基准测试性能优化文档描述了使用安全配置工具创建基于同步动态随机存取存储器\(SDRAM\)的固件映像的过程，该工具似乎可以生成适合串行下载器模式的映像：https://docs.mcuxpresso.nxp.com/secure/latest/06_processor_specific_workflow.html#image-running-from-external-sdram。但是，我们将使用 jLink 直接刷新我们的设备，因此我们需要我们的镜像包含启动头文件、ivt、dcd 等...我找到了这篇文章，描述了如何手动将这些部分重新添加到链接器脚本中：https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/I-MX-RT-How-to-boot-to-SDRAM/ta-p/1125054 但我没有任何收获。你能否提供一些指导，说明如何生成一个可以使用 JLink 刷新、从 同步动态随机存取存储器(SDRAM) 运行应用程序的二进制？ 以下是我认为最接近实现这一目标的步骤，供参考： 1. 从 RT1064-EVK 板上使用 mcuxpresso SDK V25.06.00 的 iled_blinky 项目开始。 将 `XIP_BOOT_HEADER_DCD_ENABLE=1` 和 `SKIP_SYSCLK_INIT` 添加到预处理器定义中 3. 检查"在托管链接器脚本中将应用程序链接到 RAM" 4. 删除 `PROGRAM_FLASH` 内存区域，将 `BOARD_SDRAM` 内存区域移至列表顶部 5. 运行编译来生成链接器文件 6. 取消选中 " 管理链接器脚本 " 然后将启动头文件/ivt/boot_data/data/dcd_data 部分重新添加到链接器脚本中

Clarification on Bootloader Flow: MCUboot_opensource and OTA Examples Hello, I am working with the NXP SDK for the i.MX RT platform and I noticed that the SDK provides multiple bootloader-related examples, such as mcuboot_opensource and ota_mcuboot_basic. From my understanding, the boot flow seems to be as follows: The mcuboot_opensource project is programmed first and acts as the main bootloader. The ota_mcuboot_basic example is then used to handle firmware updates. Finally, the OTA process updates the actual user application firmware. So effectively, there appear to be three components involved: MCUboot bootloader (mcuboot_opensource) OTA update application (ota_mcuboot_basic) Final user application firmware I would like to confirm if this understanding is correct. Specifically: Is mcuboot_opensource always required as the base bootloader for OTA examples like ota_mcuboot_basic? Does ota_mcuboot_basic act as the main application that gets updated, or is it only a reference example for implementing OTA updates in a custom application? In a real product, would we typically keep MCUboot as the bootloader and replace ota_mcuboot_basic with our own application? Any clarification on the correct boot flow and how these examples are intended to be used in a production setup would be very helpful. Thank you. Re: Clarification on Bootloader Flow: MCUboot_opensource and OTA Examples Hi @Bhumika18, hope you are doing well. Is mcuboot_opensource always required as the base bootloader for OTA examples like ota_mcuboot_basic?   Yes, as it contains the required source code for MCUboot to work properly. Does ota_mcuboot_basic act as the main application that gets updated, or is it only a reference example for implementing OTA updates in a custom application?   It is a reference application that implements OTA updates, therefore you would use the same logic into a custom application to enable OTA updates.   In a real product, would we typically keep MCUboot as the bootloader and replace ota_mcuboot_basic with our own application? Yes, just make sure that you maintain the OTA functionalities of the mentioned example in order to be able to do the OTA in your custom application.   Please let me know if this information clears out your doubts.

RT1064 GUI-Guider LVGL performance tweaks We have a product designed based off of the MIMXRT1064-EVK. We're using GUI-Guider to design LVGL based applications for the same type of screen that the GUI-Guider example projects use. We're working on finding performance improvements and came across this post about system level changes that can improve performance: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/LVGL-Benchmark-Performance-Optimization/ta-p/2252208 . In addition to these, are there LVGL configuration settings that can be adjusted for performance gains? We noticed that in the projects based on the GUI-Guider generated project the CPU usage as reported by the LVGL performance monitor is fairly high even when the screen is static and no GUI elements need updating. Are there any LVGL settings that can reduce the amount of redrawing that's happening? Re: RT1064 GUI-Guider LVGL performance tweaks Hi @aanderson-eemn, The GUI Guider User Guide (GUIGUIDERUG_1.10.1: GUI Guider v1.10.1 User Guide | NXP Semiconductors) has a specific section on performance optimizations, but most of the recommendations are already explored by the knowledge base article that you previously shared. My recommendation would be to follow both of these documentations to increase performance of your LVGL application. BR, Edwin. Re: RT1064 GUI-Guider LVGL performance tweaks @EdwinHz Thank you for the advice. We have found that running the application in SDRAM has resulted in a noticeable increase in performance, but I have been having a lot of trouble generating a hex file that runs the application from SDRAM. The benchmark performance optimization document described a process for creating a SDRAM-based firmware image using the secure provisioning tool that seems to generate an image suitable for the serial downloader mode: https://docs.mcuxpresso.nxp.com/secure/latest/06_processor_specific_workflow.html#image-running-from-external-sdram . However, we will be flashing our device directly using a JLink, so we need our image to include the boot header, ivt, dcd etc... I found this article describing how to manually re-add those sections to the linker script: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/I-MX-RT-How-to-boot-to-SDRAM/ta-p/1125054 , but I didn't have any luck. Could you provide some guidance for how I can generate a binary file that I can flash using a JLink, that runs the application from SDRAM? For reference here are the steps that I think come closest to achieving this: 1. starting with the iled_blinky project on the RT1064-EVK board with mcuxpresso SDK V25.06.00 . 2. add `XIP_BOOT_HEADER_DCD_ENABLE=1` and `SKIP_SYSCLK_INIT` to the preprocessor defines 3. check "Link application to RAM" in managed linker script 4. delete `PROGRAM_FLASH` memory region and move `BOARD_SDRAM` memory region to the top of the list 5. run a build to generate the linker file 6. uncheck "manage linker script" and re-add the boot header/ivt/boot_data/dcd_data sections to the linker script

ブートローダフローの説明: MCUboot_opensource と OTA の例 こんにちは、 私は i.MX RT プラットフォーム用の NXP SDK を使用していますが、SDK にはmcuboot_opensourceやota_mcuboot_basicなど、ブートローダ関連の複数の例が提供されていることに気付きました。 私の理解では、ブートフローは次のようになります。 mcuboot_opensourceプロジェクトが最初にプログラムされ、メインのブートローダとして機能します。 次に、 ota_mcuboot_basic の例を使用してファームウェアの更新を処理します。 最後に、OTA プロセスによって実際のユーザー アプリケーション ファームウェアが更新されます。 つまり、実際には 3 つの要素が関係しているようです。 MCUboot ブートローダー (mcuboot_opensource) OTAアップデートアプリケーション（ota_mcuboot_basic） 最終ユーザーアプリケーションファームウェア この理解が正しいかどうか確認したいと思います。具体的には： ota_mcuboot_basicのような OTA の例の場合、ベース ブートローダとしてmcuboot_opensource が常に必要ですか? ota_mcuboot_basic は更新されるメインアプリケーションとして機能しますか、それともカスタムアプリケーションで OTA 更新を実装するための参照例にすぎませんか? 実際の製品では、通常、MCUboot をブートローダーとして保持し、 ota_mcuboot_basic を独自のアプリケーションに置き換えますか? 正しいブートフローと、これらの例を本番環境でどのように使用するかについての説明があれば、非常に役立ちます。 よろしくお願いします。 Re: Clarification on Bootloader Flow: MCUboot_opensource and OTA Examples こんにちは@Bhumika18さん、お元気でいらっしゃることを願っています。 ota_mcuboot_basic のような OTA の例の場合、ベース ブートローダーとして mcuboot_opensource が常に必要ですか? はい、MCUboot が正しく動作するために必要なソース コードが含まれています。 ota_mcuboot_basic は更新されるメインアプリケーションとして機能しますか、それともカスタムアプリケーションで OTA 更新を実装するための参照例にすぎませんか? これは OTA アップデートを実装するリファレンス アプリケーションであるため、OTA アップデートを有効にするには、同じロジックをカスタム アプリケーションに使用します。 実際の製品では、通常、MCUboot をブートローダーとして保持し、ota_mcuboot_basic を独自のアプリケーションに置き換えますか? はい、カスタム アプリケーションで OTA を実行できるようにするには、前述の例の OTA 機能を維持するようにしてください。 この情報で疑問が解消されたかどうかお知らせください。

RT1176 PMIC_ON_REQ goes low after 5mS We are currently verifying that our design meets the power up sequence per the reference manual.  We are bypassing the internal DC/DC and all power rails come up in the correct sequence.  However, we have an intermittent issue that occurs sometimes during a brief power cycle.  The root cause appears to be the RT1176 "PMIC_ON_REQ" going low, about 5 mS after "VDD_SNVS_IN" goes high. I can't seem to find anywhere in the reference manual that explains the cases when "PMIC_ON_REQ" would go low.  There is one mention of when the "DCDC_IN" goes below 2.6V that will cause “PMIC_ON_REQ to go low.  However, "PMIC_ON_REQ" still goes low and stays low even though “VDD_SNVS_IN” and “DCDC_IN” have remained stable throughout powerup.  i.MXRT Re: RT1176 PMIC_ON_REQ goes low after 5mS I found that I wasn't handling the RT1176 POR_B (pin T10) according to the MCU’s power sequencing specifications.  The MCU reference manual states that the POR_B must remain low until all the power rails are stable.  In my case, I inadvertently had the input to POR_B indirectly dependent on the PMIC_ON_REQ.  The details aren't important but I basically had a sort of a circular logic going on. In other words, POR_B was glitching during the power up and was telling the MCU to reset before it had a chance to power up.  I also slowed down my overall power sequencing timing, allowing some margin for each of the power rails to come up and waited awhile before pulling POR_B high.  Here is a plot of my sequencing that is working now ("MCU_RESET is the name I gave POR_B): Re: RT1176 PMIC_ON_REQ goes low after 5mS Hi mckaylund , Did you ever figure this out? I have the exact same issue with the PMIC_ON_REQ going low after ~5 ms. Re: RT1176 PMIC_ON_REQ goes low after 5mS Could you expound on your comment about the relationship between ON/OFF and PMIC_REQ_ON? I have hardware that more consistently shows PMIC_REQ_ON going low after 5mS.  How is the ON/OFF signal linked to the PMIC_REQ_ON dropping low after 5mS after initial power-up?  I haven't seen any specific mention of this behavior related to power sequencing.  The consistency of the 5mS seems like the outcome of some logic rather than a transient voltage/current blip on the ON/OFF or PMIC_REQ_ON.  I've included two oscilloscope screen captures of our power sequence which also includes the ONOFF signal.  In one capture, I have tied ONOFF to ground via a 6.6K ohm, and the other screen capture is with the ONOFF left unconnected for the MCU internal pullup control. Could you clarify where the series resistor should be placed: ON/OFF or PMIC_REQ_ON?  Re: RT1176 PMIC_ON_REQ goes low after 5mS Hi @mckaylund , ON/OFF is used to switch PMIC_REQ_ON to control power modes. A 4.7-kΩ to 10-kΩ series resistor can be used when the current drain is critical. Regards, Jing

KW47: wireless_ranging_bm の RF スイッチングの例 こんにちは、 wireless_ranging_bm の例を実行するときに RF スイッチングは発生しますか?はいの場合、 1) RF_GPIO_4(PTD1) と RF_GPIO_5(PTD2) はどのように構成されますか?コードをトレースしましたが、これらの 2 つのピンのピン構成は見つかりませんでした。 2) 切り替えを制御しているのは誰ですか?（測距デモアプリまたはNBU） よろしくお願いします。 Re: KW47: RF switching on wireless_ranging_bm example こんにちは、 あなたの調子が良いといいのですが。 アンテナ切り替えを使用する測距操作の場合、測距シーケンス マネージャ (RSM) は、ローカリゼーション コントロール (LCL) モジュールに切り替えトリガーを提供します。詳細については、KW47 リファレンス マニュアルの 52.4.4.2 トランシーバを参照してください。 wireless_rangingの例では、RFスイッチのピン構成はpin_mux.cで定義されています。関数 BOARD_InitRFSwitchControlPins()。KW47-LOC は、異なる RF_GPO および pin-mux 設定 (PTD1、PTD2、PTD3) のセットを使用します。BLE ローカリゼーション アプリケーションのデバッグ GPIO およびアンテナ切り替え IO を設定する API PLATFORM_InitLcl を参照してください。PTD1、PTD2、PTD3 のセットアップが含まれています。 よろしくお願いします、 アナ・ソフィア。

i.MX93 RAW10 capture issue – only first line valid (IMX219 + ISI) Hello, I am currently debugging a RAW capture issue on i.MX93 (FRDM-iMX93) using a Sony IMX219 sensor and would appreciate any guidance on how to further debug or resolve this problem. Setup: SoC: i.MX93 Sensor: IMX219 Format: RAW10 (SRGGB10_1X10) Capture via mxc-isi → /dev/video0 Kernel: 6.12.20 (NXP BSP based) Media topology: The media graph looks correct and all links are enabled. The active pipeline is: Device topology entity 1: crossbar (3 pads, 3 links, 1 route) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 routes: 0/0 to 2/0 [ACTIVE] pad0: SINK, MUST_CONNECT stream 0 format SRGGB10_1X10 3280x2464 field none connected from csidev-4ae00000.csi pad1 pad1: SINK, MUST_CONNECT connected from mxc_isi.output pad0 pad2: SOURCE stream 0 format SRGGB10_1X10 3280x2464 field none connected to mxc_isi.0 pad0 entity 5: mxc_isi.0 (2 pads, 2 links, 0 routes) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev1 pad0: SINK stream 0 format SRGGB10_1X10 3280x2464 field none compose bounds 0,0 3280x2464 compose 0,0 3280x2464 connected from crossbar pad2 pad1: SOURCE stream 0 format SRGGB10_1X10 3280x2464 field none crop bounds 0,0 3280x2464 crop 0,0 3280x2464 connected to mxc_isi.0.capture pad0 entity 8: mxc_isi.0.capture (1 pad, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 pad0: SINK connected from mxc_isi.0 pad1 entity 16: mxc_isi.output (1 pad, 1 link) type Node subtype V4L flags 0 pad0: SOURCE connected to crossbar pad1 entity 23: csidev-4ae00000.csi (2 pads, 2 links, 1 route) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev2 routes: 0/0 to 1/0 [ACTIVE] pad0: SINK stream 0 format SRGGB10_1X10 3280x2464 field none connected from imx219 2-0010 pad0 pad1: SOURCE stream 0 format SRGGB10_1X10 3280x2464 field none connected to crossbar pad0 entity 28: imx219 2-0010 (1 pad, 1 link, 0 routes) type V4L2 subdev subtype Sensor flags 0 device node name /dev/v4l-subdev3 pad0: SOURCE stream 0 format SRGGB10_1X10 3280x2464 colorspace raw, full-range crop bounds 8,8 3280x2464 crop 8,8 3280x2464 connected to csidev-4ae00000.csi pad0 Streaming starts successfully and runs at about 15 fps. Capture command used: v4l2-ctl -d /dev/video0 --set-fmt-video=width=3280,height=2464,pixelformat=RG10 --stream-mmap --stream-count=1 --stream-to=raw10.raw Streaming to /dev/null also works and reports approximately 15.00 fps. Issue description: This is the RAW frame I captured. Although streaming succeeds, the dumped RAW image contains valid data only in the first line. The rest of the frame appears invalid or constant. This behavior is consistent across multiple captures. Questions: Are there any known issues on i.MX93 ISI when capturing RAW formats (especially RAW10) where only the first line is written correctly? Could this be related to: Bytes-per-line or stride mismatch? CSI-2 packet handling such as line length or short packets? ISI RAW packing or memory write configuration? Are there recommended debug points such as registers, trace events, or driver logs in: CSI-2 RX ISI Crossbar that could help identify why only one line is captured correctly? Any hints, references, or similar experiences would be very helpful. Thank you in advance for your support. Best regards, Minh Re: i.MX93 RAW10 capture issue – only first line valid (IMX219 + ISI) Hello, You're successfully hitting 15 fps, the CSI-2 receiver is seeing the Start and End of Frame packets, but the ISI is likely discarding the rest of the payload because the line length doesn't match the programmed width or the 32-byte alignment requirements of the NXP DMA engine. Check your byte CareCredit com sperline calculation for RAW10—if the ISI is expecting a specific packing format and gets a different byte count, it often stops writing to memory after the first line to prevent buffer corruption. I’d recommend checking the CSI-2 RX error registers for CRC/ECC flags and ensuring the ISI is in full bypass mode, as any attempt at internal color processing on RAW10 will cause the pipeline to stall or misbehave. Re: i.MX93 RAW10 capture issue – only first line valid (IMX219 + ISI) it seems you capture resolution bigger than 2k, how about capturing 1080P? if you need capture resolution bigger than 2k, you need change the ISI driver about chain buffer

ScriptGUI3, MC33777BT (EVBMA777T3) and BMA6402SA (KIT6X02AP2T1) Hi, I am trying to run some demo scripts in SCriptGUI3 (3.55) to read back registers from EVBMA777T3. I am using the KIT6X02AP2T1 to interface the TPL3. From the source code it seems that BMS6402 is supported, but the script (777_uc1_precise_current_meas.txt) doesn't work. Am I doing something wrong? Re: ScriptGUI3, MC33777BT (EVBMA777T3) and BMA6402SA (KIT6X02AP2T1) Hello Crt33   Could you send your file so we can check if there are any relevant changes?   Thanks for your understanding. I will be waiting for your response Have a great day and best of luck. Re: ScriptGUI3, MC33777BT (EVBMA777T3) and BMA6402SA (KIT6X02AP2T1) Hi, in my previous post I listed the wrong file. I used SCRIPT_uc1_current_measurement.txt which should auto-detect the PHY, not the 777_uc1_precise_current_meas.txt. The output (error) is fine. I am attaching the file. Re: ScriptGUI3, MC33777BT (EVBMA777T3) and BMA6402SA (KIT6X02AP2T1) Hi, I have spent the last day trying to run at least some example script from the ScriptGUI3 using KIT6X02AP2T1 and EVBMA777T3. Since that didn't work I modified the script to access at least some registers from the BMA6402SA gateway on the KIT6X02AP2T1.  I tried to init the PHY as bms6402 and as mc33665a as the device info register is the same. In first case I get a python error initializing the PHY. In the second case the initialization goes well, but I don't get back the response. Please see attached screenshoots.  What am I doing wrong or what is the trick using ScriptGUI3 and BMA6402 on KIT6X02AP2T1? In theory it should work. The kardware is fine as I can use the KIT6X02AP2T1 to interface BMA7118 using EvalGUI8. Thanks

Can someone please explain to me what "/0Z" is in TJA1463AT/0Z? I've been trying to find PCN for the subject in NXP homepage, but can't it yet. CAN Re: Can someone please explain to me what "/0Z" is in TJA1463AT/0Z? Thank you~ Re: Can someone please explain to me what "/0Z" is in TJA1463AT/0Z? Hi, There is no PCN available for the new TJA1463AT. The full orderable part number is TJA1463AT/0Z where /0 just indicates the first revision of TJA1463AT and Z indicates reel packing (Reel 13" Q1/T1 in Sulfur Barrier Bag). BR, Tomas

小規模組み込みプロジェクトに最適なAI搭載ノートPC こんにちは、皆さん 私はいくつかの小規模な組み込み AI プロジェクト (センサ データ プロセッシング、軽量ビジョン モデル、エッジ推論) に取り組んでおり、この種の作業に適した AI ノートPCに関する議論を始めるのは有益だと思いました。 組み込み開発では、必ずしもゲームレベルのパワーは必要ありません。さらに重要なのは (私の経験では)、CPU パフォーマンス、統合型またはエントリーレベルの GPU/NPU サポート、効率的な熱管理、長いバッテリ寿命のバランスです。最高の AI ノートPCは、日常のワークフローを遅くすることなく、TensorFlow Lite、PyTorch、OpenVINO、組み込み SDK などのツールを IDE と一緒に快適に処理できます。 私は特に、次のような機能を備えたノートPCに興味があります。 組み込みボードのクロスコンパイルとフラッシュ ローカルモデルのトレーニングまたは微調整（小規模データセット） 電力を大量に消費せずに AI アクセラレーションをサポート 開発ワークフローのための安定した Linux 互換性 組み込み AI プロジェクトに AI ノートPCを使用している場合は、次の情報を共有してください。 ノートPCの仕様とOS どのような組み込みプロジェクトを構築しているか ドライバ、AIフレームワーク、熱マネジメントに関する問題 実際の経験やコミュニティからの推奨事項から学ぶことを楽しみにしています。

The "Software License and Support Options" cannot be found in the personal interface. As shown in the figure, there is no "Software License and Support" option on this page. But for the others, the NXP interface has this option.As shown below. Re: The "Software License and Support Options" cannot be found in the personal interface. Thank you for your reply. I have solved this problem. Re: The "Software License and Support Options" cannot be found in the personal interface. Hi @Aoyng, Could you please share which specific software you are trying to access? Please try going to "Profile > Apps and Services > Software > Software Licensing and Support".   Best regards, Julián

S32DS V2.2 ライセンスの有効期限が切れます S32 Design Studio for ARM v2.2 ライセンスの有効期限が切れました。延長を手伝っていただけますか？ありがとう！ ID: 1A99-90A8-2F06-339B 回复： S32DS V2.2 License expiring S32DSの有効期限は155日後と表示されています。有効期限を事前に延長することは可能でしょうか？ありがとうございます！

SPI Driver - Slave mode only supports 1 bit mode Hi, A customer found the following limitation in the SPI MCAL RTD driver. Could you please help explain this limitation? According to the RM, slave mode does support more than 1-bit mode. I checked this in S32K3_S32M27x Real-Time Drivers AUTOSAR R23-11 Version 7.0.0. Best regards, Felipe Priority: MEDIUM RTD Source: Direct Customer Re: SPI Driver - Slave mode only supports 1 bit mode Hi @FelipeGarcia , I didn't find any limitation that indicates slave just can operate in 1 bit mode from RM or the configuration. SW team said that they will try to verify to see if have any limitation. If not, maybe they will remove this note in UM. You can follow this topic via the ticket: ARTDCC2-1387. Best regards, Nhi

LPC5411x PLL settings Hi  In my current project, I am using the PLL module of the LPC5411x. According to Section 6.5.49.6 of the datasheet, the N, M, and P values of the PLL must be calculated before being written into the corresponding registers. However, in SDK_2_9_0_LPCXpresso54114, the calculation code for NDEC, MDEC, and PDEC is not implemented; instead, the SDK directly writes manually pre‑calculated values into the syspllndec register, as shown below. (I want set M=75, so I need to calculate MDEC=9637 manually and set it to SYSCON_SYSPLLSSCTRL0_MDEC) May I ask whether there are plans to add the calculation functions in SDK for NDEC, MDEC, and PDEC in future SDK releases? Currently, setting NDEC, MDEC, and PDEC is not intuitive and is difficult to maintain, as every change to M, N, or P requires recalculating the corresponding NDEC, MDEC, and PDEC values manually. Thanks LPC54xxx Re: LPC5411x PLL settings Hi @yhc123  Thanks for your post. Currently, there are no plans to release a new SDK version for the LPC5411. Any required calculation would need to be implemented on your side. We apologize for the inconvenience this may cause.

A53側からHSEにアクセス中に再起動の問題が観察されました こんにちは、 顧客: ボッシュ HSE FW バージョン - HSE_FW_S32G3XX_9_2_63_0 A53 側から HSE にアクセスすると、再起動の問題が発生しています。MU 割り当ての詳細は次のとおりです。 • MU0とMU3 に割り当てられている M7側 • MU1とMU2 に割り当てられている A53側 M7側手順: 1. MUをアクティブに設定して有効にし、ドメインを0に割り当てました 2. mu0経由で送信される他のMUをアクティブ化する要求 テスト結果: M7 側からすべての MU に問題なくアクセスできます。 A53側の手順： 1. ホストVMでMU2、ゲストVMでMU1を使用してHSEドライバを有効にする s32-hse -v -i200 -m1 -o16 -c16 & -> A53 ゲストVM s32-hse -v -i200 -m2 -o32 -c16 & -> A53 ホストVM 2. MU2チャネル/dev/hse/32経由でHSE fwバージョンを読み取るためのサンプルテストアプリケーションをホストVMに作成しました。 テスト結果: サンプル アプリケーションから hse インターフェイス (/dev/hse/32) を開こうとするたびに、ボードが再起動されます。 sharedMemChunkSize が 0 に設定されていないことを確認しました (すべての MU インターフェイスの sharedMemChunkSize フィールドが 0 に等しい場合、XRDC は無効になります)。sharedMemChunkSize = 0 で再テストしたところ、前述の変更で同じ結果が見られました。 参考までにログを添付します: BSSM: 有効 HSE_FW 優先度: 重要 Re: Restart issue observed while accessing HSE from A53 side とりあえずこの問題は解決しました。これは、Bosch を代表して QNX チームに提起されたものです。しかし、チームはこの問題がHSEファームウェアに関連していると指摘しました。

Unable to install SECRDR S32K1 in S32DS 3.6.6 I installed S32DS 3.6.6, and noticed there were no project examples for S32K1 devices.   So I went to install new software, and I used the jar file DesignStudio_updatesite.zip: Then I selected the applicable items: When I proceed, there is a message at the bottom about "Cannot perform operation": Followed by a "Remediation Page": In the end, one of the packages is installed, but I do not find the project examples for S32K1xx in New | S32DS Project from Example. Is something wrong with 3.6.6, or with the Designupdate archive? Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Thank you Peter. 3.6.0 was released November 2024.  Is it really true that RTD is unsupported in 3.6.1 through 3.6.6??? I'm not sure how users are supposed to know based on what you underlined that RTD is not supported by later versions of S32DS, as that is not explicit.  From a user perspective, 3.6.1 - 3.6.6 are therefore useless if you need RTD.  That is hard because there are really a lot of needed updates through 3.6.6. Thanks, Matt Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Hello, I installed S32DS 3.6.6, and noticed there were no project examples for S32K1 devices. The examples are part of RTDs or SDKs and will become available once you install the driver package. Before you install the RTD, check the requirements for particular driver package. Use extension and updates for install of updatesite zip packages: Here is the guide: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32DS-Extensions-amp-Updates-Explanation-and-How-To-Use/ta-p/1128543 I do not have S32DS installed so I cant confirm if QLP3 is not working on S32DS 3.6.6. But always refer to the release notes on each package you are going to install to prevent issues. Best regards, Peter Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 In desperation I tried the older 3.0.0 QLP02 RTD drivers, and they worked!  3.0.0 QLP03 is BROKEN. Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Here is a more detailed error: Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Not sure if this is related -  Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Hello, I really cannot speak for SW team, but from my experience the compatibility is always the main issue between RTD and S32DS. 3.6.0 was released November 2024. Is it really true that RTD is unsupported in 3.6.1 through 3.6.6??? I never tied it so I cannot confirm this. But it should be possible to run it also on 3.6.6. @jiri_kral can you comment here? Also project examples are usually part of basic major version of RTD,. Best regards, Peter Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 We are really stuck.  We are unable to install a working combination of S32DS, GCC, and RTD.   If there is a magic combination of versions that is known good, please advise. Re: Unable to install SECRDR S32K1 in S32DS 3.6.6 Hello, I was speaking with S32DS team. “It is necessary to use the base version without any patches. You currently has Patch 03 installed, but this patch is intended to be applied only on top of the official release. Furthermore, these patch versions have not been formally tested.” Best regards, Peter

S32K146 の CAN-FD 5 Mbps サポート NXPチームの皆様、こんにちは。 私はS32K146 MCU を使用しており、達成可能な最大 CAN-FD データ フェーズ ビット レートを確認したいと思います。 私の設定: MCU: NXP S32K146 (CAN-FD対応FlexCAN) CANソースクロック: 80 MHz PLL出力 CAN-FDデータフェーズビットレートを5Mbpsに設定しようとしています Re: CAN‑FD 5 Mbps Support on S32K146 こんにちは、 章 55.3.11.1 クロック ドメインとデバイス RM の制限では、達成可能な最大データ フェーズ ビット レートを計算するための式を示します。あなたがおっしゃった 5Mbps は可能です。 ビットレートパラメータの計算には以下のカリキュレータを使用することができます。 https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MPC5xxx-S32Kxx-LPCxxxx-CAN-CAN-FD-ビットタイミング計算/ta-p/1119319 BR、ペトル

S32K312 BCTU FIFO/loop switch (non AUTOSAR prj) Hello, I've read so many posts regarding BCTU topic and examples too, but I'm a bit confused about best configuration for my purpose. Into my project I have 2 system statuses: 1- (DC brushed motor PWM active) ADC acquisitions triggered by Emios_1_12 PWM in order to read motor current and other channels synchronized with PWM frequency (and duty) 2- (no actuation) I'd like to acquire same channels from ADC continously without interruptions and then I'll read via SW only the channel that I need for a particular task. My analysis: Mode 1: BCTU HW triggered and list with all needed channels Mode 2: BCTU triggered started once via SW and with loop mode active, in order to let conversions run continously. I need to switch between these two modes (by disabling HW trigger or stopping loop mode), so I'd like to know which is the best solution and maybe alternatives. My question is related also to which destination to use for results: for mode 2 I'd use ADC registers and then read with Adc_Sar_Ip_GetConvResultsToArray() API. For mode 1 I haven't found a way to specify an interrupt callback when all acquisistions of the channel list is done (independently from ADC instance) because I noted that it is possible to specify a "List last conversion notification" into "Bctu ADC Notifications" (NXP Configuration tool - MEX file) but I'll have an interrupt for each ADC (2 in my case), instead I'd like to have a single interrupt for all conversions of the list finished: for this reason I'm thinking to use FIFO and watermark.  For internal policy, I can't share my entire project at the moment. Channels added into screenshots are both on ADC1 just for testing, but then I'll have to add other channels from ADC0. Thanks Re: S32K312 BCTU FIFO/loop switch (non AUTOSAR prj) Hi @Drifter22, I think both modes are fairly common applications, and I see no issue with applying them to your routine.  For Mode 1, I recommend configuring FIFO + Watermark, as this would enable you to raise an interrupt for a completed "set" of ADC channels. Just keep in mind that notifications are done in a N + 1 logic, meaning that if you have watermark set to 3, notification is called when there are 4 entries in the FIFO and you can do 4 readings of FIFO. For Mode 2, I think you have two choices. Either SW-triggered BCTU as you've mentioned or continuous ADC scanning (if you do not need various ADC instances). You can use either Adc_Sar_Ip_GetConvData or Adc_Sar_Ip_GetConvResultsToArray to extract the channel result, There are various BCTU + ADC examples in our community, which may prove useful: S32M27x/S32K3 – eMIOS/BTCU/ADC/DMA – [RTD600] [RTD400 LLD]K344 Center Aligned PWM Trigger ADC BCTU S32K3 Motor control SW examples Example S32K312 PIT BTCU ADC-1 BCTU_ADC_DATA_REG DMA DS3.5 RTD300 Best regards, Julián

Flexcomm I2Sによる同期DSD(PDM)再生 LPC5528 を使用して Hi-Fi USB オーディオ インターフェースを実装することを計画しました。このようなアプリケーションには、いわゆる「DSD ネイティブ」出力が必要です。 基本的に、これは I2S SCK に類似したビットクロックを備えた 2 つの同期 PDM オーディオ出力 DSDA/DSDB です。 リファレンス・マニュアルに記載されているように、LPC5528 には I2S 信号共有と呼ばれる機能があり、異なる Flexcomm I2S インターフェースが同じ SCK/WS/DATAIN などを共有できるようになります。 2 つの Flexcomm インターフェイスを I2S Tx として設定し、そのうちの 1 つをマスターとして設定し、同じ SCK を共有すると、それらは完全に同期され、DSD オーディオ インターフェイスのタイミング要件を満たすことができますか? ヒント: DSD オーディオ インターフェイスの一般的なタイミング要件については、 CS43198 データシートの23 ページを参照してください。 全般 LPC55xx ペリフェラル USB 用户论坛 Re: Synchronized DSD(PDM) Playback with Flexcomm I2S こんにちは@nonameC_さん、 可能であれば、RM の 35.3 章「基本構成」をこの機能の構成ガイドとして使用できます。ただし、次の点に注意してください。 注: 信号共有接続はレジスタ値が変更されると行われ、 同期はデータ ストリームの開始前に行う必要があります。 両方のモジュールを同期させたままにするには、この投稿に記載されている提案に従うことができます。この投稿では、この目的のために DATAPAUSE メカニズムを使用しています。 また、データシートのセクション 11.10 に記載されている I2S ペリフェラルの動的制限にも留意してください。 他にご質問がございましたらお知らせください。 BR ハビブ