Multi Source Translation Content

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Multi Source Translation Content

讨论

排序依据:
Starting GStreamer with systemd. There is an issue starting GStreamer with systemd. Entering the following command produces an error message and the video doesn't appear. Help me find a solution. root@imx8mpevk:~# systemctl start myservice root@imx8mpevk:~# systemctl status myservice * myservice.service - test service Loaded: loaded (/etc/systemd/system/myservice.service; disabled; preset: disabled) Active: active (running) since Tue 2024-05-14 02:12:25 UTC; 7s ago Main PID: 834 (myservice.sh) Tasks: 2 (limit: 5574) Memory: 5.1M CGroup: /system.slice/myservice.service |-834 /bin/bash /home/root/myservice.sh `-841 sleep 10 May 14 02:12:25 imx8mpevk systemd[1]: Started test service. May 14 02:12:25 imx8mpevk myservice.sh[834]: gst start!! May 14 02:12:25 imx8mpevk myservice.sh[835]: Setting pipeline to PAUSED ... May 14 02:12:25 imx8mpevk myservice.sh[835]: Failed to set pipeline to PAUSED. May 14 02:12:25 imx8mpevk myservice.sh[835]: Setting pipeline to NULL ... May 14 02:12:25 imx8mpevk myservice.sh[835]: Freeing pipeline ... The same shell script works fine when executed in the console, I can see the video. root@imx8mpevk:~# ./myservice.sh gst start!! Setting pipeline to PAUSED ... Pipeline is live and does not need PREROLL ... Pipeline is PREROLLED ... Setting pipeline to PLAYING ... New clock: GstSystemClock [ 1033.191967] bypass csc [ 1033.194381] input fmt YUV4 [ 1033.197096] output fmt YUYV Redistribute latency... 0:00:00.8 / 99:99:99. Here is my "myservice.service" and "myservice.sh" file. myservice.service [Unit] Description=GStreamer After=multi-user.target [Service] Type=simple User=root ExecStart=/home/root/myservice.sh RemainAfterExit=yes GuessMainPID=no myservice.sh #!/bin/bash export XDG_RUNTIME_DIR=/run/user/0/ echo gst start!! gst-launch-1.0 v4l2src device=/dev/video2 ! waylandsink Please help!! Re: Starting GStreamer with systemd. Although no one was interested, I found a solution on my own and have summarized it here. myprogram.service [Unit] Description=My Last Service After=weston.service [Service] User=root Environment="WAYLAND_DISPLAY=/run/wayland-0" Environment="XDG_RUNTIME_DIR=/run/user/$(id -u root)" ExecStart=/home/root/run.sh Restart=on-failure StandardOutput=journal StandardError=journal [Install] WantedBy=multi-user.target run.sh echo Start GST!! gst-launch-1.0 v4l2src device=/dev/video2 ! waylandsink Register service systemctl daemon-reload systemctl enable myprogram.service This way, it works well for me. When I reboot, the camera screen comes up automatically.
查看全文
systemd で GStreamer を起動します。 systemdでGStreamerを起動する際に問題があります。 次のコマンドを入力すると、エラーメッセージが表示され、ビデオが表示されません。 解決策を見つけるのを手伝ってください。 root@imx8mpevk:~# systemctl start myservice root@imx8mpevk:~# systemctl status myservice * myservice.service - テストサービス 読み込み済み: 読み込み済み (/etc/systemd/system/myservice.service; 無効; プリセット: 無効) アクティブ: 2024年5月14日火曜日02:12:25 UTC以降にアクティブ(実行中)。7秒前 メインPID:834(myservice.sh) タスク: 2 (制限: 5574) メモリ:5.1M CGroup: /system.slice/myservice.service |-834 /bin/bash /home/root/myservice.sh '-841 スリープ 10 5月14日02:12:25 imx8mpevk systemd [1]:テストサービスを開始しました。 5月14日 02:12:25 imx8mpevk myservice.sh[834]:GST開始!! 5月14日02:12:25 imx8mpevk myservice.sh[835]:パイプラインを一時停止するように設定しています... 5月14日02:12:25 imx8mpevk myservice.sh[835]:パイプラインを一時停止に設定できませんでした。 5月14日02:12:25 imx8mpevk myservice.sh[835]:パイプラインをNULLに設定しています... 5月14日 02:12:25 imx8mpevk myservice.sh[835]:パイプラインの解放... 同じシェルスクリプトをコンソールで実行すると正常に動作し、ビデオを見ることができます。 root@imx8mpevk:~# ./myservice.sh GSTスタート!! パイプラインを一時停止するように設定しています... パイプラインは稼働しており、PREROLLは必要ありません... パイプラインは事前に展開されています... パイプラインを PLAYING に設定しています ... 新しいクロック: GstSystemClock [ 1033.191967] バイパスCSC [ 1033.194381] 入力fmt YUV4 [ 1033.197096] 出力fmt YUYV レイテンシの再配分... 0:00:00.8 / 99:99:99. これが私の「myservice.service」ですと "myservice.sh"ファイル。 myservice.service [Unit] Description=GStreamer After=multi-user.target [Service] Type=simple User=root ExecStart=/home/root/myservice.sh RemainAfterExit=yes GuessMainPID=no myservice.sh #!/bin/bash export XDG_RUNTIME_DIR=/run/user/0/ echo gst start!! gst-launch-1.0 v4l2src device=/dev/video2 ! waylandsink 助けてください!! Re: systemd で GStreamer を起動します。 誰も興味を示さなかったのですが、自分で解決策を見つけ、ここにまとめました。 myprogram.service 【ユニット】 description=私の最後のサービス アフター=weston.service 【サービス】 ユーザー=ルート 環境="WAYLAND_DISPLAY=/run/wayland-0" 環境="XDG_RUNTIME_DIR=/run/user/$(id -u root)" ExecStart=/home/root/run.sh 再起動=失敗時 StandardOutput=ジャーナル StandardError=ジャーナル [インストール] WantedBy=マルチユーザー.ターゲット run.sh エコースタートGST!! GSTローンチ-1.0v4l2src device=/dev/video2 !ウェイランドシンク サービス登録 systemctl デーモン-リロード systemctl enable myprogram.service このように、それは私にとってうまくいきます。再起動すると、カメラの画面が自動的に出ます。
查看全文
S32K312-Problem with C40CheckLockDomainID function Hello When I looked at the C40 function, I found that there is such a judgment in the function C40_Ip_CheckLockDomainID: if ((uint32)VirtualSector != FLS_MAX_VIRTUAL_SECTOR) This judgment means that the parameter VirtualSector passed in cannot be equal to FLS_MAX_VIRTUAL_SECTOR, but the value of the FLS_MAX_VIRTUAL_SECTOR macro is 271, which is a legal Sector. So is this judgment incorrect? The attachment is a screenshot of the function logic and macro, please check it out. BestRegards Simon Re: S32K312-Problem with C40CheckLockDomainID function Hi @VaneB  OK, I'll contact you again if I run into problems. BestRegards Simon Re: S32K312-Problem with C40CheckLockDomainID function Hi @Simon-Liu  At the moment we do not have any bug reports related to this function. So, we do not recommend modifying. If you encounter a problem, let us know so the information can be sent to the corresponding team. Re: S32K312-Problem with C40CheckLockDomainID function Hi @VaneB  If my understanding is correct, there is something wrong with the logic in the code now, right? How to modify it? BestRegards Simon Re: S32K312-Problem with C40CheckLockDomainID function Hi @VaneB  I have mentioned it many times. According to the current logic, if the actual domain ID obtained through C40_Ip_CheckLockDomainID_CheckRegister() is 0, STATUS_C40_IP_SUCCESS will be returned directly, and it will not be judged at all whether the actual domain ID matches the provided domain ID value. Re: S32K312-Problem with C40CheckLockDomainID function Hi @Simon-Liu  The C40_Ip_CheckLockDomainID function will return a STATUS_C40_IP_ERROR if the actual domain obtained by C40_Ip_CheckLockDomainID_CheckRegister() and the operation performed to assign a value to LockDomainIDValue does not match the provided domain ID value (DomainIdValue). Re: S32K312-Problem with C40CheckLockDomainID function Hi @VaneB  The situation I mentioned before is that you enable XRDC and change the domain, and the MasterID is 0, then ERROR should be returned the next time you access using another MasterID, but according to the current logic, SUCCESS is returned because TempLockMasterRegister is 0. Re: S32K312-Problem with C40CheckLockDomainID function Hi @Simon-Liu  No, if TempLockMasterRegister is 0, the return value of the function will be STATUS_C40_IP_SUCCESS. You should not have any problems. Unless you enable XRDC and change the domain and this domain does not match the value you gave to DomainIdValue, if this is the case the function will return STATUS_C40_IP_ERROR. Re: S32K312-Problem with C40CheckLockDomainID function Hi @VaneB  So if this is the case, would something go wrong: XRDC is enabled, and the MasterID locking Flash is 0. In this case, the value of the variable TempLockMasterRegister is also 0. Re: S32K312-Problem with C40CheckLockDomainID function Hi @Simon-Liu  I had consulted the corresponding team about this topic.  These conditions are considered just when XRDC is enabled and the PFLASH domain has been changed. Otherwise, the domain will always be 0.  Re: S32K312-Problem with C40CheckLockDomainID function @VaneB  So what should the logic of this judgment be? How to modify it? Re: S32K312-Problem with C40CheckLockDomainID function Hello @VaneB  The variable TempLockMasterRegister does not correspond to the value of PFCBLKn_SPELOCK, but the value of PFCBLK_LOCKMASTER_S, so the condition (TempLockMasterRegister!=0U) only means that the value of MasterID is not 0. What can this be used to determine? BestRegards Simon Re: S32K312-Problem with C40CheckLockDomainID function @Simon-Liu  You are correct TempLockMasterRegister corresponds to PFCBLKU_LOCKMASTER_S or PFCBLKn_LOCKMASTER_Sn, this register provides the status of the sector program/erase lock bit domain ID owner (PFCBLKn_SPELOCK or PFCBLKU_SPELOCK). Re: S32K312-Problem with C40CheckLockDomainID function Hello, @VaneB  There is another problem of this function: There is such a judgment in the function C40_Ip_CheckLockDomainID (the complete code is as shown in the attached picture): if ( (0U != (CheckRegister & C40_Ip_u32BitPosition)) && (TempLockMasterRegister != 0U) ) My understanding of this is that if the SETSLOCK of the corresponding Sector is not set to 1, or the value of LOCKMASTER is 0, it means that the Sector is not locked/protected and can be erased. I have questions about the second condition of this judgment. Why does the value of LOCKMASTER 0 also mean that the Sector is not locked? The MasterID may also be 0 (as shown in the attached picture). Is this judgment condition written wrong? BestRegards Simon Re: S32K312-Problem with C40CheckLockDomainID function Hi, @VaneB  Thank you for your reply. Will this error be corrected in subsequent RTD releases? BestRegards, Simon Re: S32K312-Problem with C40CheckLockDomainID function Hi @Simon-Liu  Sorry for the inconvenience. These are typos, please make sure that FLS_MAX_VIRTUAL_SECTOR located in C40_Ip_Cfg.h has the same value as the C40_UTEST_ARRAY_0_S000 and that C40_SECTOR_ERROR is one value greater than C40_UTEST_ARRAY_0_S000.  For example instead of: #define FLS_MAX_VIRTUAL_SECTOR (271U) … #define C40_UTEST_ARRAY_0_S000 (272U) #define C40_SECTOR_ERROR (272U) Needs to be: #define FLS_MAX_VIRTUAL_SECTOR (272U) … #define C40_UTEST_ARRAY_0_S000 (272U) #define C40_SECTOR_ERROR (273U) Note: every time you update the code by ConfigTool these will return to their original value so you will have to change again.  B.R. VaneB 
查看全文
LPC860のI3C通信、リード動作で受信データが重複する LPCXpresso860-MAX BOARDのI3Cモジュールを使用し、I3Cをコントローラとして設定すると、リード動作で受信データが重複します。I2Cモードでは2回、I3C SDRモードでは3回繰り返します。たとえば、「0xAA 0xBB 0xCC 0xDD」が送信されると、「0xAA 0xAA 0xBB 0xBB」が受信されます。 しかし、オシロスコープでSCL信号を測定すると、受信したデータは正確です。rxfifoのカウントレジスタは、オシロスコープですぐに減少するのではなく、SCL信号でオシロスコーププローブを使用するとすぐに減少することがわかりました。 読み取り操作で受信したデータが重複する原因は何ですか? LPC800 日時:LPC860のI3C通信、読み取り操作で受信データが重複する STM32H5を使用すると、同じ問題は発生しません。不思議です。
查看全文
LPC860的I3C通信,读取操作中接收数据重复 当使用LPCXpresso860-MAX BOARD的I3C模块,并将I3C配置为控制器时,在读取操作中接收的数据会被复制。在 I2C 模式下,它重复两次,在 I3C SDR 模式下,它重复三次。例如,发送“0xAA 0xBB 0xCC 0xDD”时,接收“0xAA 0xAA 0xBB 0xBB”。 但用示波器测量SCL信号时,接收到的数据是正确的。我们发现,如果没有示波器,rxfifo 的计数寄存器不会立即减少,但是如果在 SCL 信号中使用示波器探头,则会立即减少。 什么原因导致读取操作中接收的数据重复? LPC800 回复:LPC860的I3C通信,读取操作中接收的数据重复 当我使用 STM32H5 时,没有出现同样的问题。这很奇怪。
查看全文
I3C communication of LPC860, received data are duplicated in read operation When use I3C module of LPCXpresso860-MAX BOARD, and I3C configured as a controller, received data are duplicated in read operation. In I2C mode, it repeats two times, in I3C SDR mode, it repeats three times. For example, when "0xAA 0xBB 0xCC 0xDD" are sent, "0xAA 0xAA 0xBB 0xBB" are received. But when measure SCL signal with an oscilloscope, the received data are correct. We found that the count register of rxfifo didn't decrease immediately whithout an oscilloscope, but decrease immediately whith an oscilloscope probe in SCL signal. what causes received data to be duplicated in read operation? LPC800 Re: I3C communication of LPC860, received data are duplicated in read operation when I use STM32H5,it doesn't have the same issue. It is strange. Re: I3C communication of LPC860, received data are duplicated in read operation Hi @Travel  The duplication of received data in read operations when using the I3C module of the LPCXpresso860-MAX board could be due to several potential issues. Since you've observed that the received data are correct when measuring the SCL signal with an oscilloscope, but the count register of rxfifo doesn't decrease immediately without the oscilloscope, it suggests that the issue might be related to the electrical characteristics of the bus or the timing of the read operation. Here are some possible causes for the duplication of data: 1. Electrical Noise or Interference: Without the oscilloscope probe, there might be more electrical noise on the bus, which could cause the I3C controller to erroneously detect additional start or stop conditions, leading to duplicated data. The capacitive load introduced by the oscilloscope probe might help to stabilize the signal and reduce noise. 2. Bus Timing Issues: The I3C protocol has specific timing requirements for start, address, and data phases. If the bus timing is not properly configured or if there are delays due to software overhead, it could cause the controller to mistakenly interpret a single data packet as multiple packets. 3. Incorrect Configuration: If the I3C module is not correctly configured as a controller, or if there are settings that are not properly adjusted for the specific mode of operation (I2C or I3C SDR), it could lead to unexpected behavior during data transfer. Hope this will help you. BR Hang
查看全文
S32K3 GPIO DC electrical specifications When i applied an varying voltage from 0 to 3.3V to controller Pin, The microcontroller taking 1.65 as Input high. Also when i decrease high to low (Ie, 3.3V to 0V) at 1.58V microcontroller took as Input Low. As per data sheet, For 3.3V microcontroller Input high voltage is 0.7 VDD to VDD and Input low is 0V to 0.3 VDD. 1, Why microcontroller taking 1.65 as Input high? Any software setting required to change or not? 2, What will actually happen in between an voltage comes VIL and VIH? 3, What is the transition voltage of microcontroller? Re: S32K3 GPIO DC electrical specifications Hi @Chinnan, You could set your desired voltage input as a reference by configuring an ADC and using that value as a low or high. Best regards, Julián Re: S32K3 GPIO DC electrical specifications Is there any way in the software that any input voltage between 0.3VDD to 0.65VDD on the GPIO pin can be taken as low or high? Re: S32K3 GPIO DC electrical specifications Hi @Chinnan, You can find inside the following document, section "Input Characteristics": AN2434: Input/Output Pin Drivers on HCS12 Family MCUs, which still applies to S32K3 family: When defining VIH or VIL, it is generally set at 70% or 30% of VDD so it is guaranteed that the input reads either LOW or HIGH when input passes those thresholds levels. Many factors affect the transition voltage level for the MCU, such as temperature. That is why a specific transition voltage is not specified, it is not possible to predict which logic level the MCU will interpret. Best regards, Julián Re: S32K3 GPIO DC electrical specifications The Microcontroller was S32K322NHT0MPAST  100 Pin HDQFP
查看全文
S32DS 更新 RTD5.0 并编译 non_cacheable_bss 溢出错误 嗨,技术官员们, 我已经在 S32K3XX_S32M27X_RTD4.4 中开发了一个 S32M27x 项目,该项目正在运行。 但是我安装了RTD5.0之后,将项目SDK更改为RTD5.0,更新源代码并重建项目。我遇到了如图所示的 non_cacheable_bss 溢出问题。 我比较了 RTD5(右)和 RTD4(左)之间的地图文件。我发现这是因为 DET 添加了许多全局变量。DET 是自动生成的。我该如何解决这个问题?
查看全文
S32K3 GPIO DC电气规格 当我向控制器引脚施加从 0 到 3.3V 的变化电压时,微控制器将 1.65 作为输入高电平。另外,当我将 1.58V 的高电平降至低电平(即 3.3V 降至 0V)时,微控制器将其视为输入低电平。 根据数据表,对于 3.3V 微控制器,输入高电压为 0.7 VDD 至 VDD,输入低电压为 0V 至 0.3 VDD。 1、为什么单片机要把1.65作为输入高电平?是否需要更改任何软件设置? 2、电压达到VIL和VIH之间究竟会发生什么? 3、单片机的转换电压是多少? 回复:S32K3 GPIO DC电气规格 软件中是否有任何方法可以将 GPIO 引脚上 0.3VDD 至 0.65VDD 之间的任何输入电压视为低或高? 回复:S32K3 GPIO DC电气规格 微控制器是S32K322NHT0MPAST 100针HDQFP
查看全文
S32K3 GPIO DC電気仕様 0〜3.3Vの可変電圧をコントローラーピンに印加すると、マイクロコントローラーは入力ハイとして1.65を取ります。また、1.58Vでハイからロー(つまり、3.3Vから0V)に下げると、マイクロコントローラーは入力ローとして取ります。 データシートによると、3.3Vマイクロコントローラの場合、入力高電圧は0.7VDDからVDDで、入力LOWは0Vから0.3VDDです。 1、なぜマイクロコントローラーは入力ハイとして1.65を取るのですか?変更する必要があるソフトウェア設定はありますか? 2、電圧がVILとVIHの間に実際に何が起こるのですか? 3、マイクロコントローラーの遷移電圧はどれくらいですか? Re:S32K3 GPIO DC電気仕様 ソフトウェアには、GPIOピンの0.3VDDから0.65VDDまでの入力電圧を低または高にする方法はありますか? Re:S32K3 GPIO DC電気仕様 マイクロコントローラは100ピンHDQFP S32K322NHT0MPAST されました
查看全文
How to display multi-language on the screen with LVGL using Gui Guider? Now I'm going to develop a product with displaying multi-language (such as Chinese, English, Russian, etc.) on the LCD screen using LVGL. I wonder if there is a way to set widgets' texts with parameters? Like define a series of parameters about language and use them set text content: /* --------------------------- Code example --------------------------- */ typedef struct {     char *itemChinese,     char *itemEnglish, } param_language_t; param_language_t param_language = {     .itemChinese = "你好",     .itemEnglish = "Hello", }; lv_label_set_text_fmt(ui->screen_main_label_hello, "%s", param_language.itemEnglish); /* --------------------------- Code example --------------------------- */ Or just using a middleware named lv_i18n, which also needs using parameters to set widgets text. Re: How to display multi-language on the screen with LVGL using Gui Guider? Hello @ChesterLee , I'm glad to help you. I will feed back your suggestion. Any new issues, welcome to create a new thread. BRs, Celeste Re: How to display multi-language on the screen with LVGL using Gui Guider? Hi @Celeste_Liu , Tks for your kindly reply. I wish Gui Guider could support more languages in the future. Anyway, tks a lot! Best Regard Chester Re: How to display multi-language on the screen with LVGL using Gui Guider? Hello @ChesterLee , Thanks for your post. According to GUI Guider v1.8.1 User Guide, currently the GUI Guider IDE only supports two language: English and Chinese. However, this can be achieved by developing custom code. The following is an example. For the detailed description of this example, you can refer to the section of "7.10 How to develop a multi - language application". Hope it helps. Best Regards, Celeste
查看全文
Unable to connect S32 debug probe to S32K344 Hi, I am trying to use an S32 debug probe to connect to our custom S32K344 board in DS. Although the connection test passes, the device and core do not appear in the debugger configuration window. When I check the available list, only S32G2/3 options are shown. I have already installed the S32K development package and upgraded to the latest S32K RTD version. Can anyone advise on how to get the probe working with the S32K MCU?" Thanks, XD Re: Unable to connect S32 debug probe to S32K344 Hi According to the information in chapter 2.1 Release content of S32K3xx_Development_Package_Release_Notes_3.5.13_RTM.pdf, S32 Debug Probe does not seem to support S32K344. 2.1 Release content • Support for wizards creating application and library projects for the S32K3xx processor family • GCC version 10.2.0 20200910, build 1728 revision g5963bc8. • GCC version 9.2.0 20190812 build 1649 revision gaf57174. • Green Hills 2021.1.4 compiler support. • WindRiver DIAB 7.0.6 compiler support. • IAR 8.50.10 compiler support. • PEmicro debug probes support for RAM and FLASH configurations (Integrate new PnE 5.8.7 into S32K3xx development package) • Lauterbach probe support for running from RAM and FLASH • IAR debugger support. • TASKING debugger support. • Segger debugger support. • VDK Debugger support • S32 Configuration Tools support (Pins, Clocks, Peripherals, DCD (DCF Tool), IVT). Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
查看全文
Inquiry About Error Occurring When Deleting Pins in S32DS3.5 RTD 4.0.0 Hello, I have a question about assigning pins using S32DS3.5 RTD 4.0.0, and I would like to ask for your help. [Image 1] In Image 1, you can see the default PTA0 GPIO pin and the PTE26 pin that I configured. At this stage, there are no particular errors. [Image 2] In Image 2, I deleted the PTA0 pin since it is not being used. [Image 3] [Image 4] However, as shown, an error occurs. This error seems to indicate an issue with the Siul2_Port module, as demonstrated in [Image 3] and [Image 4]. Why does this error occur?
查看全文
i.MXRT 102x spread spectrum How do I configure spread spectrum for the MIMXRT1021DAG5A? There is no CCM_ANALOG_PLL_SYS_SS register in the clocks tool to enable it. I have selected PLL2 and input some test values. The values appear to change the board.c file to match, but there is no way to enable this feature from the tools (that I have found). I am using: MCUXpresso IDE v11.9.0 [Build 2144] [2024-01-05] i.MXRT 102x Re: i.MXRT 102x spread spectrum Just wanted to be sure I hadn't missed where this was set. The 1176 had support so thought the 102x series would as well. Re: i.MXRT 102x spread spectrum Hi @joshgentrycargt, I'm afraid that currently there isn't any way of enabling the Spread Spectrum using Clocks Config. This would have to be enabled manually using the CCM_ANALOG_PLL_SYS_SS register. Sorry for the inconvenience this may cause. BR, Edwin.
查看全文
カスタム imx93 ベースのボード用の u-boot の構築 lpddr4x_timing.cを更新しました既存の board/freescale/imx93_evk u-boot ソース フォルダ内の spl.c は、カスタム DRAM と PMIC の統合を反映します。フラッシュバイナリファイルをビルドし、eMMCストレージに正常にデプロイすることができました。 u-bootのカスタムボード構成を作成するためのガイダンスはありますか? 私は、以下に概説する手順を使用して、ソースツリーでカスタムボードの別の構成を作成しようとしています。 cp -R board/freescale/imx93_evk board/freescale/imx93_som cp include/configs/imx93_evk.h include/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi この内容で board/freescale/imx93_som/Kconfig を更新しました。 if TARGET_IMX93_11X11_SOM config SYS_BOARD default "imx93_som" config SYS_VENDOR default "freescale" config SYS_CONFIG_NAME default "imx93_som" choice prompt "Select DDR Type" default IMX93_EVK_LPDDR4X if TARGET_IMX93_11X11_SOM config IMX93_EVK_LPDDR4X bool "Using LPDDR4X Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4X timing and 0.6V VDDQ config IMX93_EVK_LPDDR4 bool "Using LPDDR4 Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4 timing and 1.1V VDDQ endchoice endif arch/arm/mach-imx/imx9/Kconfig を更新し、以下の追記を行いました: ... config TARGET_IMX93_11X11_SOM bool "imx93_11x11_som" select OF_BOARD_FIXUP select IMX93 ... source "board/freescale/imx93_som/Kconfig" ... arch/arm/dts/Makefile を更新し、カスタム dts ファイルのエントリを追加しました: dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ imx93-11x11-som.dtb \ imx93-14x14-evk.dtb \ imx93-9x9-qsb.dtb \ imx93-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-11x11-evk.dtb \ imx91p-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-9x9-qsb-spinand.dtb .configを更新しましたファイルに次の変更を加えます。 29,30c29,30 < CONFIG_SYS_BOARD="imx93_evk" < CONFIG_SYS_CONFIG_NAME="imx93_evk" --- > CONFIG_SYS_BOARD="imx93_som" > CONFIG_SYS_CONFIG_NAME="imx93_som" 195c195 < CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" --- > CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-som" 202c202 < CONFIG_TARGET_IMX93_11X11_EVK=y --- > # CONFIG_TARGET_IMX93_11X11_EVK is not set 206,207c206 < CONFIG_IMX93_EVK_LPDDR4X=y < # CONFIG_IMX93_EVK_LPDDR4 is not set --- > CONFIG_TARGET_IMX93_11X11_SOM=y 431c430 < CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" --- > CONFIG_DEFAULT_FDT_FILE="imx93-11x11-som.dtb" 936c935 < CONFIG_OF_LIST="imx93-11x11-evk" --- > CONFIG_OF_LIST="imx93-11x11-som" 938c937 < CONFIG_SPL_OF_LIST="imx93-11x11-evk" --- > CONFIG_SPL_OF_LIST="imx93-11x11-som" ただし、ビルドを作成しようとすると、次のエラーが発生します。 ... AR spl/fs/built-in.o LDSのspl/u-boot-spl.lds LDのSPL / UブートSPL aarch64-poky-linux-ld.bfd: board/freescale/imx93_som/spl.o: 関数 'spl_dram_init' 内: /home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76: 'dram_timing' への未定義の参照 aarch64-poky-linux-ld.bfd: /home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76: 'dram_timing' への未定義の参照 make[2]: *** [/home/user/controls/Uboot/user-som/source/scripts/Makefile.spl:528: spl/u-boot-spl] エラー 1 make[1]: *** [/home/user/controls/Uboot/user-som/source/Makefile:2044: spl/u-boot-spl] エラー 2 make [1]:ディレクトリ '/home/user/controls/Uboot/user-som/artifacts'を離れます make: *** [Makefile:177: sub-make] エラー 2 make: ディレクトリ '/home/user/controls/Uboot/user-som/source' を離れます 何か見落としたことはありましたか? どんな意見でも大歓迎です、前もって感謝します。 Re: カスタム imx93 ベースのボードのための u-boot の構築 以下は、赤で欠落しているステップです。 cp -R ボード/フリースケール/imx93_evk/ ボード/フリースケール/imx93_som MVボード/フリースケール/imx93_som/imx93_evk.Cボード/フリースケール/imx93_som/imx93_som.c cp include/configs/imx93_evk.h include/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi これらの変更についても言及するのを忘れていました。 diff --git a/board/freescale/imx93_som/Makefile b/board/freescale/imx93_som/Makefile index b6b978dd..4710b954 100644 --- a/board/freescale/imx93_som/Makefile +++ b/board/freescale/imx93_som/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx93_evk.o +obj-y += imx93_som.o ifdef CONFIG_SPL_BUILD obj-y += spl.o Re: カスタム imx93 ベースのボードのための u-boot の構築 こんにちは @abt、 私は現在同じ問題で立ち往生しています、あなたはあなたの欠けたステップが何であったか覚えていますか? Re: カスタム imx93 ベースのボードのための u-boot の構築 私の問題は解決しました。一歩足りなかった。
查看全文
Building u-boot for a custom imx93 based board I have updated lpddr4x_timing.c and spl.c in the existing board/freescale/imx93_evk u-boot source folder to reflect custom DRAM and PMIC integrations. I was able to build the flash binary file and successfully deploy it on the eMMC storage.  Is there any guidance for creating a custom board configuration for u-boot?  I have been trying to create a separate configuration for the custom board, in the source tree, using the  steps outlined below: cp -R board/freescale/imx93_evk board/freescale/imx93_som cp include/configs/imx93_evk.h include/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi Updated board/freescale/imx93_som/Kconfig with this content: if TARGET_IMX93_11X11_SOM config SYS_BOARD default "imx93_som" config SYS_VENDOR default "freescale" config SYS_CONFIG_NAME default "imx93_som" choice prompt "Select DDR Type" default IMX93_EVK_LPDDR4X if TARGET_IMX93_11X11_SOM config IMX93_EVK_LPDDR4X bool "Using LPDDR4X Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4X timing and 0.6V VDDQ config IMX93_EVK_LPDDR4 bool "Using LPDDR4 Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4 timing and 1.1V VDDQ endchoice endif Updated arch/arm/mach-imx/imx9/Kconfig with the following addition: ... config TARGET_IMX93_11X11_SOM bool "imx93_11x11_som" select OF_BOARD_FIXUP select IMX93 ... source "board/freescale/imx93_som/Kconfig" ... Updated arch/arm/dts/Makefile and added an entry for a custom dts file: dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ imx93-11x11-som.dtb \ imx93-14x14-evk.dtb \ imx93-9x9-qsb.dtb \ imx93-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-11x11-evk.dtb \ imx91p-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-9x9-qsb-spinand.dtb Updated .config file with the following changes: 29,30c29,30 < CONFIG_SYS_BOARD="imx93_evk" < CONFIG_SYS_CONFIG_NAME="imx93_evk" --- > CONFIG_SYS_BOARD="imx93_som" > CONFIG_SYS_CONFIG_NAME="imx93_som" 195c195 < CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" --- > CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-som" 202c202 < CONFIG_TARGET_IMX93_11X11_EVK=y --- > # CONFIG_TARGET_IMX93_11X11_EVK is not set 206,207c206 < CONFIG_IMX93_EVK_LPDDR4X=y < # CONFIG_IMX93_EVK_LPDDR4 is not set --- > CONFIG_TARGET_IMX93_11X11_SOM=y 431c430 < CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" --- > CONFIG_DEFAULT_FDT_FILE="imx93-11x11-som.dtb" 936c935 < CONFIG_OF_LIST="imx93-11x11-evk" --- > CONFIG_OF_LIST="imx93-11x11-som" 938c937 < CONFIG_SPL_OF_LIST="imx93-11x11-evk" --- > CONFIG_SPL_OF_LIST="imx93-11x11-som" However, I get the following error when trying to make a build: ... AR spl/fs/built-in.o LDS spl/u-boot-spl.lds LD spl/u-boot-spl aarch64-poky-linux-ld.bfd: board/freescale/imx93_som/spl.o: in function `spl_dram_init': /home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76: undefined reference to `dram_timing' aarch64-poky-linux-ld.bfd: /home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76: undefined reference to `dram_timing' make[2]: *** [/home/user/controls/Uboot/user-som/source/scripts/Makefile.spl:528: spl/u-boot-spl] Error 1 make[1]: *** [/home/user/controls/Uboot/user-som/source/Makefile:2044: spl/u-boot-spl] Error 2 make[1]: Leaving directory '/home/user/controls/Uboot/user-som/artifacts' make: *** [Makefile:177: sub-make] Error 2 make: Leaving directory '/home/user/controls/Uboot/user-som/source' Did I miss anything?  Any input appreciated, thanks in advance. Re: Building u-boot for a custom imx93 based board I would try updating some additional variables in .config file as shown below: CONFIG_DEFAULT_DEVICE_TREE="imx93-som" CONFIG_OF_LIST="imx93-som" CONFIG_SPL_OF_LIST="imx93-som" Regards Re: Building u-boot for a custom imx93 based board Hi @abt  I am currently stuck at the same error you got : aarch64-poky-linux-ld.bfd: board/freescale/imx93_som/spl.o: in function `spl_dram_init': /home/user/uboot-imx-2023.04-A1/board/freescale/imx93_som/spl.c:78:(.text.spl_dram_init+0xc): undefined reference to `dram_timing' aarch64-poky-linux-ld.bfd: /home/user/uboot-imx-2023.04-A1/board/freescale/imx93_som/spl.c:78:(.text.spl_dram_init+0x10): undefined reference to `dram_timing' make[1]: *** [scripts/Makefile.spl:528: spl/u-boot-spl] Error 1 I have added the missing step in red and also updated the Makefile as you have mentionned before but still stuck at the same error. Is there any other missing step  for resolving this error please ? Re: Building u-boot for a custom imx93 based board Here is the missing step in red: cp -R board/freescale/imx93_evk/ board/freescale/imx93_som mv board/freescale/imx93_som/imx93_evk.c board/freescale/imx93_som/imx93_som.c cp include/configs/imx93_evk.h include/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi I forgot to also mention these changes: diff --git a/board/freescale/imx93_som/Makefile b/board/freescale/imx93_som/Makefile index b6b978dd..4710b954 100644 --- a/board/freescale/imx93_som/Makefile +++ b/board/freescale/imx93_som/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx93_evk.o +obj-y += imx93_som.o ifdef CONFIG_SPL_BUILD obj-y += spl.o Re: Building u-boot for a custom imx93 based board Hi @abt, I'm currently stuck at the same problem, do you recall what your missing step was? Re: Building u-boot for a custom imx93 based board Hi @abt, What was the missing step? Thanks in advance. Re: Building u-boot for a custom imx93 based board My problem has been solved. I was missing a step.
查看全文
为基于 imx93 的定制主板构建 u-boot 我已经更新了lpddr4x_timing.c并在现有的board/freescale/imx93_evk u-boot 源文件夹中使用spl.c来反映自定义 DRAM 和 PMIC 集成。我能够构建闪存二进制文件并成功将其部署到 eMMC 存储上。 有没有为 u-boot 创建自定义板配置的指导? 我一直在尝试使用下面概述的步骤在源树中为自定义板创建单独的配置: cp -R board/freescale/imx93_evk board/freescale/imx93_som cp include/configs/imx93_evk.h include/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi 使用以下内容更新board/freescale/imx93_som/Kconfig : if TARGET_IMX93_11X11_SOM config SYS_BOARD default "imx93_som" config SYS_VENDOR default "freescale" config SYS_CONFIG_NAME default "imx93_som" choice prompt "Select DDR Type" default IMX93_EVK_LPDDR4X if TARGET_IMX93_11X11_SOM config IMX93_EVK_LPDDR4X bool "Using LPDDR4X Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4X timing and 0.6V VDDQ config IMX93_EVK_LPDDR4 bool "Using LPDDR4 Timing and PMIC voltage" select IMX9_LPDDR4X help Select the LPDDR4 timing and 1.1V VDDQ endchoice endif 更新了arch/arm/mach-imx/imx9/Kconfig ,并添加了以下内容: ... config TARGET_IMX93_11X11_SOM bool "imx93_11x11_som" select OF_BOARD_FIXUP select IMX93 ... source "board/freescale/imx93_som/Kconfig" ... 更新了arch/arm/dts/Makefile并添加了自定义 dts 文件的条目: dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ imx93-11x11-som.dtb \ imx93-14x14-evk.dtb \ imx93-9x9-qsb.dtb \ imx93-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-11x11-evk.dtb \ imx91p-9x9-qsb-ontat-wvga-panel.dtb \ imx91p-9x9-qsb-spinand.dtb 更新了 .config文件有以下更改: 29,30c29,30 < CONFIG_SYS_BOARD="imx93_evk" < CONFIG_SYS_CONFIG_NAME="imx93_evk" --- > CONFIG_SYS_BOARD="imx93_som" > CONFIG_SYS_CONFIG_NAME="imx93_som" 195c195 < CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" --- > CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-som" 202c202 < CONFIG_TARGET_IMX93_11X11_EVK=y --- > # CONFIG_TARGET_IMX93_11X11_EVK is not set 206,207c206 < CONFIG_IMX93_EVK_LPDDR4X=y < # CONFIG_IMX93_EVK_LPDDR4 is not set --- > CONFIG_TARGET_IMX93_11X11_SOM=y 431c430 < CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" --- > CONFIG_DEFAULT_FDT_FILE="imx93-11x11-som.dtb" 936c935 < CONFIG_OF_LIST="imx93-11x11-evk" --- > CONFIG_OF_LIST="imx93-11x11-som" 938c937 < CONFIG_SPL_OF_LIST="imx93-11x11-evk" --- > CONFIG_SPL_OF_LIST="imx93-11x11-som" 但是,当我尝试构建时出现以下错误: ... AR spl/fs/built-in.o LDS spl/u-boot-spl.lds LD spl/u-boot-spl aarch64-poky-linux-ld.bfd: board/freescale/imx93_som/spl.o: 在函数“spl_dram_init”中: /home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76: 对“dram_timing”未定义引用 aarch64-poky-linux-ld.bfd:/home/user/controls/Uboot/user-som/source/board/freescale/imx93_som/spl.c:76:对“dram_timing”未定义引用 make[2]: *** [/home/user/controls/Uboot/user-som/source/scripts/Makefile.spl:528: spl/u-boot-spl] 错误 1 make[1]: *** [/home/user/controls/Uboot/user-som/source/Makefile:2044: spl/u-boot-spl] 错误 2 make[1]: 离开目录‘/home/user/controls/Uboot/user-som/artifacts’ make:*** [Makefile:177:sub-make] 错误 2 make: 离开目录‘/home/user/controls/Uboot/user-som/source’ 我遗漏了什么吗? 任何意见都值得赞赏,提前致谢。 回复:为基于 imx93 的定制主板构建 u-boot 这是红色标记的缺失步骤: cp -R 板/飞思卡尔/imx93_evk/ 板/飞思卡尔/imx93_som mv 板/freescale/imx93_som/imx93_evk.c 板/freescale/imx93_som/imx93_som.c cp 包括/configs/imx93_evk.h 包括/configs/imx93_som.h cp arch/arm/dts/imx93-11x11-evk.dts arch/arm/dts/imx93-11x11-som.dts cp arch/arm/dts/imx93-11x11-evk-u-boot.dtsi arch/arm/dts/imx93-11x11-som-u-boot.dtsi 我忘了提及这些变化: diff --git a/board/freescale/imx93_som/Makefile b/board/freescale/imx93_som/Makefile index b6b978dd..4710b954 100644 --- a/board/freescale/imx93_som/Makefile +++ b/board/freescale/imx93_som/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx93_evk.o +obj-y += imx93_som.o ifdef CONFIG_SPL_BUILD obj-y += spl.o 回复:为基于 imx93 的定制主板构建 u-boot 你好@abt , 我目前遇到同样的问题,你还记得你缺少什么步骤吗? 回复:为基于 imx93 的定制主板构建 u-boot 我的问题已经解决了。我漏掉了一步。
查看全文
S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hello all. I have the lpi2c_master-s32k144 example compiled and running, i have added an infinite loop to keep sending a packet out on ID 0x01 which i can see on my picoscope fine, but i have tried to add some data to the buffer to send and regardless of how try to load the buffer up, i still get no data in the buffer. Modified code below if someone can point me in the right direction please. Thanks Rich #define TRANSFER_SIZE (8u) /*! \brief The main function for the project. \details The startup initialization sequence is the following: * - __start (startup asm routine) * - __init_hardware() * - main() * - PE_low_level_init() * - Common_Init() * - Peripherals_Init() */ int main(void) { /* Allocate memory for the LPI2C driver state structure */ lpi2c_master_state_t lpi2c1MasterState; /* Declaration of the LPI2C transfer buffer */ uint8_t buffer[TRANSFER_SIZE]; uint8_t data[8]; /* Variable used for the loop that initializes the data buffer */ uint16_t i; /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ #ifdef PEX_RTOS_INIT PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */ #endif /*** End of Processor Expert internal initialization. ***/ /* Initialize and configure clocks * - Configure system clocks and dividers * - Configure LPI2C clock gating * - see clock manager component for details */ CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT); CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT); /* Initialize pins * - Configure LPI2C pins * - See PinSettings component for more info */ PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr); /* Initialize LPI2C Master configuration * - Slave address 0x01 * - Fast operating mode, 400 KHz SCL frequency * - See LPI2C components for configuration details */ LPI2C_DRV_MasterInit(INST_LPI2C1, &lpi2c1_MasterConfig0, &lpi2c1MasterState); // Set I2C Address to 0x01 LPI2C_DRV_MasterSetSlaveAddr(INST_LPI2C1,0x01,false); /* Initialize the data buffer */ for (i = 0u; i < TRANSFER_SIZE; i++) { buffer[i] = i; } /* Send a packet of data to the bus slave */ LPI2C_DRV_MasterSendData(INST_LPI2C1, buffer, TRANSFER_SIZE, true); /* Clear the buffer to prepare it for the next operation */ // for (i = 0u; i < TRANSFER_SIZE; i++) // { // buffer[i] = 0u; // } for(;;) // MAIN LOOP { uint8_t data[] = {1,2,3,4,5,6,7,8}; // LPI2C_DRV_MasterSendData(INST_LPI2C1, buffer, TRANSFER_SIZE, true); LPI2C_DRV_MasterSendData(INST_LPI2C1, data, 8, true); } /* Request data from the bus slave */ //LPI2C_DRV_MasterReceiveDataBlocking(INST_LPI2C1, buffer, TRANSFER_SIZE, true, OSIF_WAIT_FOREVER); /* End of the driver example */ /*** Don't write any code pass this line, or it will be deleted during code generation. ***/ /*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/ #ifdef PEX_RTOS_START PEX_RTOS_START(); /* Startup of the selected RTOS. Macro is defined by the RTOS component. */ #endif /*** End of RTOS startup code. ***/ /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ for(;;) { if(exit_code != 0) { break; } } return exit_code; /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ } /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ /* END main */ /*! ** @} */ /* ** ################################################################### ** ** This file was created by Processor Expert 10.1 [05.21] ** for the Freescale S32K series of microcontrollers. ** ** ################################################################### */ Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi @RML_SPARKY  The I2C protocol requires a receiver and transmitter to archive a successful communication.  The acknowledgment takes place after every byte. The acknowledge bit lets the receiver signal to the transmitter that the byte was successfully received and another byte may be sent. So, as you are not configuring the slave the master remains waiting for the missing acknowledge of the slave.  Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi,  I have been doing some further testing with the i2C_pal_s32k144 on S32DS 3.4 and latest SDK,  If i comment out the i2c slave initialization line as shown below i get the exact behaviour i am observing, where the master will only send the address and not what is in the transmit buffer. Unfortunately i cannot use LPI2C as master because FLEXIO does not support the slave feature. Why does the I2C Master code require the slave to be configured? Thanks Rich Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi  I have now downloaded S32DS 3.4, installed the SDK 4.0.3 and re written the example , i still get no data being sent over I2C, only the address appears on the picoscope. Project attached,  Thanks Rich Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi @RML_SPARKY  As the SDK version used is an old version, could you please test with the latest SDK version (v4.0.3 supported by S32DS 3.4) or with the Real-Time Drivers for S32K1 (v2.0.0 supported by S32DS 3.5)?  Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi VaneB, have you had any success on this?  I have also simplified the i2c PAL example to just a master using the LPI2C pins . I see the address being sent over the i2c bus on my picoscope, but no date being sent with it. I have attached the project here. Thanks Rich Re: S32K144EVB LPI2C_master_s32k144 issue modifying to add data to the send packets Hi @RML_SPARKY  Looks like you are using an older version of the S32K1 SDK, please verify if, with the latest SW release, you have the same behavior. Also, could you share your project so we can test it from our side? B.R. VaneB
查看全文
Freertos LWIP http server without external SDRAM I am using iMXRT1021 with a custom board and I am having trouble with the http server example. My board does not have an external SDRAM and  I am using the freertos sdk example simply changing the memory sequence and and some pins. I can compile and run it but I cannot have any ethernet activity and I never receive a packet, With the baremetal example all works fine... Is possible to have this kind of application with a board without external memory? Regards. Stefano 回复: Freertos LWIP http server without external SDRAM Hi @stefanardo , If your project is based on the MCUXpresso IDE, you can easily delete the SDRAM space and modify NCACHE_REGION to a piece of space from OCRAM. Please run your project after making this change and try it again, see these two links: 1. NCACHE_REGION issue on RT1024 - NXP Community 2. 已解决: NCACHE region in internal RAM IMXRT1021 - NXP Community Best regards, Gavin
查看全文
LPC824 - Setting Code Read Protection (CRP) Hello! I was hoping to understand more about the Code Read Protection on the LPC824 microcontroller. From what I've been reading, it sounds like the Code Read Protection isn't a dedicated register, but rather just a specific location in memory. Is this correct? Why it matters to me - I have a production released binary that was compiled without "Enable automatic placement of Code Read Protection field in image" selected. I'd like to enabled Code Read Protection after programming the binary. If I simply write 0x87654321 to memory location 0x02FC, is it possible that I overwrite a functional part of my binary? Thank you! LPC800 Re: LPC824 - Setting Code Read Protection (CRP) Hello @kwagner  No, wont' corrupt your software. The important is please read CRP level definition carefully and config  the right CRP. BR Alice Re: LPC824 - Setting Code Read Protection (CRP) Hi Alice, Thanks for the information! If I overwrite memory locations 0x02FC - 0x02FF in my binary, is that dangerous? Is this memory location specifically set aside for CRP or could this corrupt my software? Thanks! Re: LPC824 - Setting Code Read Protection (CRP) Hello @kwagner  1)"From what I've been reading, it sounds like the Code Read Protection isn't a dedicated register, but rather just a specific location in memory. Is this correct?" ->> Yes. 2) The minimum size of flash write and erase is 64 bytes.  Recommend you read out flash, then change the CRP configuration. Then program the whole flash again using new image. BR Alice
查看全文