android UI format not match issue on imx7d android-pie Hi,        I'm porting a new LCD to my imx7d DIY development board. kernel: 4.14 android: 9       Screen size is 320x240, physical format is RGB565. And I get a very weird issue. The main screen and some android applications can showing correctly. But some android applications are not refresh.       If I do further debugging, I can find in FbDisplay.cpp, the updateScreen() function report buffer format is RGBA8888 but config format is RGB565, so the refresh operation is stopped.      If I force the  getBE().mRenderEngine =          RE::impl::RenderEngine::create(HAL_PIXEL_FORMAT_RGBA_8888  to be  getBE().mRenderEngine =             RE::impl::RenderEngine::create(HAL_PIXEL_FORMAT_RGB_565 those android application can show on the screen, but red and blue pixel are oppsite. If I use this method, I can't monitor the screen on my PC. I want to know what thing cause this format not match issue and how do I perfectly fix it? Re: android UI format not match issue on imx7d android-pie Hi Zhiming,     Thank you with your suggestion. I already find out a solution to fix that issue. By rotate the screen orientation in kotlin project. Probably, layout height is too long for android framework to resize. I should change the width:height in my layout. Regards! PatrickZ Re: android UI format not match issue on imx7d android-pie Hello, As my understanding about surfaceflinger, the surfaceflinger is a Render Engine, it receives the operations from application layer  and then call the fbdisplay to display. So the issue could from application layer, the app tells Render Engine how to render a frame. I don't think the Render Engine is designed for one pixel format, the pixel format should be set from the app layer. Best Regards, Zhiming Re: android UI format not match issue on imx7d android-pie Hi Zhiming,     Do you mean it might be something wrong in the android kotlin application? The config.format in Fbdisplay is all right, and I think the issue is comes from surfaceflinger. The buffer.format remains RGBA8888. Regards! Patrick Zhang Re: android UI format not match issue on imx7d android-pie Hello, This may have something to do with the code of the application that is having problems, the application is using 32bit data, so in the HAL layer code the return is RGB888. You need to look at the code of the application again to try to fix the problem. https://github.com/nxp-imx-android/android-imx_platform_hardware_imx/blob/p9.0.0_2.3.4/display/display/FbDisplay.cpp#L457C1-L462C6 Best Regards, Zhiming

S32G3 RDB3 flash RGB_LED_M7 project to QSPI Hi, I’m using Design Studio 3.5 to build the RGB_LED_M7 project and have followed the software enablement guide to update the linker script. I used the IVT tools to generate a blob image, and the SD card image worked well. However, when I tried generating the QSPI image, it didn’t work—the LEDs didn’t blink at all. I made sure to change the interface selection to QSPI and selected the MX25UM51245G in S32Flashtool. I’ve attached both screenshots for reference. Since I was able to use S32Flashtool to flash fip.s32-qspi successfully, and the board booted, I suspect there might be an issue with the IVT configuration of the LED project. Could you help me troubleshoot this? Thanks in advance for your support. XD Re: S32G3 RDB3 flash RGB_LED_M7 project to QSPI Hi @alejandro_e : It works now, thank you for your support! Thanks, XD Re: S32G3 RDB3 flash RGB_LED_M7 project to QSPI Hello @XD , For what I can see you are missing the QSPI parameters, you can solve that by selecting the "Configure QSPI parameters" checkbox on the left side of the IVT view, and select the file mx25_sim133ddr.bin. you should be able to find it in your installation directory, for example "C:\NXP\S32DS.3.5\eclipse\mcu_data\processors\S32G399A\PlatformSDK_S32XX_4_0_0\quadspi\default_boot_images\mx25_sim133ddr.bin" Let me know if this information solved your problem.

NT3H2111 energy harvesting Hello, I am evaluating the NT3H2111 as a replacement for an ST25DV. However, it is not clear from the datasheet how the energy harvesting behaves. This is important since our application does require the ability to temporarily enable the energy harvesting. Can the energy harvesting function be disabled? Is the VOUT pin High-Z when there is no field and/or the energy harvesting function is disabled? What is the current leakage when external voltage is applied to the VOUT pin? Thanks for your help! Alexis Re: NT3H2111 energy harvesting Hello earth75,  NT3H2111 does not have the posibility to "disable" the energy harvesting. In different words, if there is an RF voltage on the LA/LB pins, you will always see the rectified voltage on VOUT (of cource, it depends on an used load).  About the current leakage, it should be in the range of 10-15 uA.  BR Tomas  Re: NT3H2111 energy harvesting Hello @earth75  If you do not want to use the energy harvesting function, keep the VOUT pin floating should be OK. Re: NT3H2111 energy harvesting Hi @KaiLi  Thanks I have read the Application note already. It describes in good details what the behavior of VOUT is during harvesting and the relationship between field strength and output power. However I'm interested in the behavior in the absence of a field : what happens to Vout when a voltage is externally applied to the pin, for example by a battery? Does it sink current? Also, is it possible to disable energy harvesting so that VOUT stars high-Z at all times? Regards, Alexis Re: NT3H2111 energy harvesting Hello @earth75  I would suggest you take a look at the following documentation, which should help you understand energy harvesting feature. https://www.nxp.com.cn/docs/en/application-note/AN11578.pdf

Changing ADC S32K342 to read from pin instead of internal bandgap I am trying to edit the Adc_Sar_Bctu_Ip_example_S32K344 example to read from an input pin, in this case Pin78 on the 100 pin package which corresponds to S9, rather than the internal bandgap. Is changing the ADC Physical Channel name to S9 and the define to match the correct channel number? When I try to run it it gets stuck in the endofchainnotif with data having the maxed out 14 bit value despite not having any power connected to the pin Is there an easier/barebones way to do this? Re: Changing ADC S32K342 to read from pin instead of internal bandgap While I still dont get the data value to appear in variables on the right the issue was found to be a hardware one and now the adc functions properly. Re: Changing ADC S32K342 to read from pin instead of internal bandgap I tried to copy this and it still does not show on the variables/ data goes maximum 14 bit value. I attached the project to maybe help. My board is just an s32k342 with the bare minimum requirements to power on the board. Also for some reason in the 342 SDK VS_0 is named Board_peripherals according to a different post which is why that is different to the 344 version. also the  Re: Changing ADC S32K342 to read from pin instead of internal bandgap Hi, I tried this example on S32K344_EVB, do little code modification to do SW trigger still, connect POT output to S9 channel and see conversion normally changing as per input value. BR, Petr Re: Changing ADC S32K342 to read from pin instead of internal bandgap It never shows me a conversion, in variables all I have are these optimized out values, am I looking in the wrong place? Regardless of whether I give S9 voltage or not the data only shows 16838 if i hover it Re: Changing ADC S32K342 to read from pin instead of internal bandgap Hi, changes you did would be enough. Even not connected external signal you will get some value converted. Put some voltage and check if you got correct conversion. You can omit while loop in notification callback, it is there just for example purpose. Do your stuff with converted value. BR, Petr

S32K1xx LPUART IntCtrl_IP callback function Implement Hello NXP Team, I'm modifying the UART example from S32K1 AUTOSAR R21-11 RTD 2.0.0 P04 D2404 Example Project and want to add a UART RX interrupt callback function. Currently, I'm using IntCtrl_IP to add the callback function, but it's not working. Here is my LPUART0_ISR function void LPUART0_ISR() {     const char* pBuffer = "LPUART0_ISR\r\n";     volatile Lpuart_Uart_Ip_StatusType lpuartStatus = LPUART_UART_IP_STATUS_ERROR;     uint32 T_timeout = 0xFFFFFF;     uint32 remainingBytes;       Lpuart_Uart_Ip_AsyncSend(UART_LPUART_INTERNAL_CHANNEL, pBuffer, strlen(pBuffer));     /* Check for no on-going transmission */     do     {         lpuartStatus = Lpuart_Uart_Ip_GetTransmitStatus(UART_LPUART_INTERNAL_CHANNEL, &remainingBytes);     } while (LPUART_UART_IP_STATUS_BUSY == lpuartStatus && 0 < T_timeout--); } Or is there any sample code I can refer to? Thank you! Re: S32K1xx LPUART IntCtrl_IP callback function Implement Hi, do you use own board or EVB? On S32K118EVB you should use different pins then the one selected. BR, Petr Re: S32K1xx LPUART IntCtrl_IP callback function Implement I tried implementing the RX interrupt on both UART0 and UART1, but I couldn't receive the RX_FULL event for either of them. Additionally, I encountered a LPUART_UART_IP_EVENT_ERROR on UART1. Could you please help me review my code to check if there's anything incorrectly configured? I would really appreciate your assistance. Re: S32K1xx LPUART IntCtrl_IP callback function Implement Hi, the LPUART_UART_IP0_IRQHandler is assigned nowhere so there is no reason to be called. 1) the Lpuart_Uart_Ip_EventType enum of the Events which can trigger UART callback is defined in lpuart_uart_ip_types.h.  Teh callback with LPUART_UART_IP_EVENT_RX_FULL event is called when defined number of bytes (specified in AsyncReceive function) was received. 2) the LPUART_UART_IP_0_IRQHandler is driver ISR routine assigned for module interrupt. When byte is received/send this handler is called, byte serviced and user callback is called from there if defined event is achieved. 3) you can check in debugger if driver interrupt is get, means LPUART_UART_IP_0_IRQHandler called. if yes then LPUART_UART_IP_EVENT_RX_FULL would be called as well after defined number of bytes is received. BR, Petr Re: S32K1xx LPUART IntCtrl_IP callback function Implement Hi PetrS Thanks for your reply I'm testing the UART callback function by enabling UART loopback mode. I can receive the UART_Callback event, but the LPUART_UART_IP0_IRQHandler function is not being executed. I have some questions regarding this setup: 1. Where can I set the LPUART_UART_IP_EVENT_RX_FULL value? 2. If the UART event is triggered, what is the purpose of the LPUART_UART_IP0_IRQHandler function? 3.If UART loopback mode is not enabled and I use another UART TX to send data to the S32K118 RX, I am unable to receive the LPUART_UART_IP_EVENT_RX_FULL event. here is my testing function void sendstring(char* string) { Lpuart_Uart_Ip_AsyncSend(UART_LPUART_INTERNAL_CHANNEL, string, strlen(string)); } void UART_Callback(const uint8 HwInstance, const Lpuart_Uart_Ip_EventType Event, void *UserData) { if(HwInstance == UART_LPUART_INTERNAL_CHANNEL) { switch(Event){ case LPUART_UART_IP_EVENT_RX_FULL: sendstring("LPUART_UART_IP_EVENT_RX_FULL\r\n"); ISR_UART = 1; break; case LPUART_UART_IP_EVENT_TX_EMPTY: sendstring("LPUART_UART_IP_EVENT_TX_EMPTY\r\n"); break; case LPUART_UART_IP_EVENT_END_TRANSFER: //sendstring("LPUART_UART_IP_EVENT_END_TRANSFER\r\n"); break; case LPUART_UART_IP_EVENT_ERROR: sendstring("LPUART_UART_IP_EVENT_ERROR\r\n"); break; //case LPUART_UART_IP_EVENT_IDLE_STATE: //break; default: break; } } } void LPUART_UART_IP0_IRQHandler() { sendstring("LPUART_UART_IP0_IRQHandler\r\n"); } I would greatly appreciate any advice you can provide. Thank you! Re: S32K1xx LPUART IntCtrl_IP callback function Implement Hi, if you want to use driver's interrupt routine and call own callback from it then just configure respective handler in IntCtrl component (here lpuart 6 is shown, use your instance) and add your callback function in Lpuart component Then in your code you add callback and do your need according available events void Uart_Callback(const uint8 HwInstance, const Lpuart_Uart_Ip_EventType Event, void *UserData) { if(HwInstance == UART_INSTANCE) { switch(Event){ case LPUART_UART_IP_EVENT_RX_FULL: break; case LPUART_UART_IP_EVENT_TX_EMPTY: break; case LPUART_UART_IP_EVENT_END_TRANSFER: break; case LPUART_UART_IP_EVENT_ERROR: break; case LPUART_UART_IP_EVENT_IDLE_STATE: break; default: break; } } } BR, Petr

MC33665ATS4シルクスクリーンの違い 顧客のIQCエンジニアは、MC33665ATS4として最新のチップシルクスクリーンを受け取りましたが、これは最後に素材のシルクスクリーンがMC33665ATS4AEされたときと一致しません、AEがパッケージングの接尾辞であることを顧客に説明し、エンジニアは特定の違い特定のドキュメントの説明を必要とし、それをどのように取得しますか?ありがとうございます！

MC33665ATS4 silk screen differences The customer's IQC engineer received the latest chip silk screen as MC33665ATS4, which is inconsistent with the last time the material silk screen was MC33665ATS4AE, explain to the customer that AE is a packaging suffix, the engineer needs a specific difference specific document description, how to get it? Thank you! Re: MC33665ATS4 silk screen differences Hello, You can reach out to the manufacturer's technical support or check their official documentation, such as datasheets or release notes. They should be able to provide you with the necessary information to clarify the differences between the two packaging styles.

S32DS 3.0 Install error when i try to activate the software, it report the error above, who can help resolve this issue? Re: S32DS 3.0 Install error The issue is solved after restarting my notebook, thanks very much for your prompt response Re: S32DS 3.0 Install error Hi @leolv. To help diagnose this, it would be useful to review the installation logs from the base tool.  You can find the installation log in the following directory: C:\NXP\S32DS.3.6.0\_S32 Design Studio for S32 Platform 3.6.0_installation\Logs\S32_Design_Studio_for_S32_Platform_3.6.0_Install_MM_DD_YYYY (date)_HH_MM_SS(time).log Please note that the path may vary depending on your Design Studio Version and your installation directory. I will be waiting for your response. - RomanVR.

MC33665ATS4丝印差异 客户的IQC工程师收到最新的芯片丝印为MC33665ATS4，与上次物料丝印为MC33665ATS4AE不一致，向客户解释AE是封装后缀，工程师需要具体差异具体的文档说明，如何获取？谢谢你！

BTCU LIST Configuration I am facing an issue understanding the list of the BTCU. Currently, I can retrieve values in the DMA buffer, but they are not uniform. The values appear cyclic, making it difficult to map ADC values to specific indices. Additionally, the values vary, though some match the expected ADC values. This issue primarily occurs when using two different ADC instances. In this example, I am using ADC1 and ADC0: ADC1: S21_ChanNum45 and S8_ChanNum32 ADC0: S10_ChanNum34 Question: I understand that the "Last Channel" is used to indicate the next list if a different trigger is present. I want to confirm whether this applies only to a different trigger or also to the same trigger occurring in the next cycle. Q2. Regarding the values, they are not consistent, as I mentioned earlier. Can you explain how this works and how I can achieve stable and consistent values? As you can see, even without changing the voltage, the values sometimes rotate and appear in a different order Q3) I have encountered this issue of misinterpreting the BTCU list in multiple examples. For instance, I tested this example: [https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-PIT-BTCU-ADC-DMA-DS3-4-RTD100/ta-p/1435324], which includes a BTCU list. I noticed that the same channel appears twice, but I don’t understand the reason for this or how it maps to the BctuDmaFifo1. Could you please explain? Q4) Additionally, could you explain the significance of the 'Watermark Value' Q5) A more detailed explanation of the BTCU list would be very helpful. In terms of configuration, I believe I have set it up correctly, but the values do not appear at the expected indexes and do not match the BTCU list. @PetrS Re: BTCU LIST Configuration Thanks a lot for this! I was missing that detail. It's working fine now—I updated the peripherals and code as per your recommendation. I hadn’t realized that the BCTU list[ADC0,ADC1,ADC0,ADC1] sequence maps directly to the ADC sequence. Re: BTCU LIST Configuration Hi, if 2 ADCs are triggered by BCTU (ADC0 and ADC1 in your case as target mask is 3) then a list should contain even number of items, ADCs are sampled parallelly as below   You should add another item for ADC1 conversion and mark it as last channel. Moreover set watermark to 3. BR, Petr Re: BTCU LIST Configuration Re: BTCU LIST Configuration Can you consider only the below settings and provide comments based on that? I have set up the ADC to obtain the following results: Result[0] → ADC1, channel S21 Result[1] → ADC0, channel S10 Result[2] → ADC1, channel S8 However, is not appearing as expected. I have reviewed the reference manual as you suggested. . I had some basic understanding issue regarding the same.  Regarding point 6 (the last point), does this mean I cannot sample ADC1 channels S8 and S21 simultaneously? Will the value update in the next trigger of BctuWatermarkNotification? Could this be the reason why the result is not updating as I expected? I would appreciate it if you could clarify this behavior. If there are any corrections needed, please let me know. In my actual system, I have multiple ADCs, so I want to ensure I understand the behavior correctly with this basic example. Rest of the configuration I think is okay. Re: BTCU LIST Configuration Hi, it looks pretty the same, sorry. Also why you show list with 3 item at first then with 6 items. What is your need in fact? Then, no picture shows BCTU trigger setting, is it for single ADC or more? Rather share your simplified project or explain more. BR, Petr Re: BTCU LIST Configuration Re: BTCU LIST Configuration I have attached a higher-resolution image along with a .zip file containing my configuration, which is focused solely on this functionality. Re: BTCU LIST Configuration Hi, pictures are very blurred, hard to read anything. But lets try... 1) the CL operation is clearly described in chapters 64.3.2.1-3 of the RM, regarding NEXT and LAST option. If multiple ADCs are triggered then list items are taken in pairs (triplets), see more in chapter  64.3.4 2-3) cannot comment here, share complete BCTU setting in visible form. 4) FIFO Watermark specifies the FIFO watermark levels. If the number of active FIFO entries exceeds the watermark level, a DMA or interrupt request can be generated. Usually set based on BCTU list entries, if for example contains 6 items, watermark is set to 5. Means once 6 results are stored in FIFO interrupt is called and you can read those 6 results in callback. In case of DMA, the DMA reads the RXFIFO and fill user buffer and callback is called again. 5) refer e.g to https://community.nxp.com/t5/S32K/How-BCTU-LIST-items-works/m-p/1570114#M19447 Or share your config/code in readable form, or simplified project. BR, Petr 

After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. We are facing hard fault exception after PMIC, I2c and Dio Integration in Bootloader, included Mcu clock ref also.  Following are the screenshots of the hard fault: So far we found that ModeConfigPtr is not updating the correct address and we updated it manually during debug. Even after that we see it is going hard fault as seen below: Configuration parameters: Re: After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. Hello @Anup97,  As I mentioned before, we do not recommend including the PMIC driver into the bootloader, therefore we don't have examples or guide on how to do it. I can recommend you checking the Bootloader User Manual available in the GoldVIP package that you can find in the AUTO-SW-PACKAGE-MANAGER  you can find this document after installing the package in the documentation folder. If you are not able to download the package please contact your FAE/DFAE/NXP representative so they can guide you on how to enable it. In this document you can will see information on how to customize the bootloader.  Re: After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. We are able to load the bootloader image and from bootloader initialization it is going to exception. As shared in below screenshots: Do you have any reference, where Pmic is integrated in the bootloader ? Re: After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. Hello @Anup97,  Being that it is a custom HW I may not be able to give you full support. With that said, I do not recommend putting this modules in the bootloader, since the expected behavior is that the bootloader does the minimum just to boot the needed cores and then give control to said cores. Also the bootROM has a timeout to load the Bootloader image, if the image is too big it will cause the board to reset, as you can see in the reference manual [page 1348, S32G3 Reference Manual, Rev. 4, 02/2024]: Can you check if this timeout is being respected? Another thing I can recommend is checking the clock an power configurations of the problematic modules. I2C uses either DMA or interrupts to manage the flow of information, this modules might not be completely configured when the bootloader is traying to send/receive messages.  I am assuming that if you are using this modules in your application then the hardware can be discarded as a problem. In this case, mi general recommendation is to create the smallest and simplest bootloader so it can be loaded and executed in the fastest way possible, so that the M7 application can refresh the PMIC watchdog before the PMIC timeout. Let me know if this information was useful. Re: After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. Hello @alejandro_e , RTD version is 4.0.2 Custom HW Tresos version 29.2.0 The modules were already available in the EB Tresos plugins, I've imported the modules by selecting the module configuration settings. Please refer below:  We are already using these modules in our autosar application, we're trying to replicate in bootloader for triggering the watchdog refresh. Re: After PMIC integration in bootloader, it is going to Hard Fault exception in S32G3. Hello @Anup97, To be able to help you I will need some details about your setup: What is the RTD version you are using? Are you using the RDB3 or a custom HW? What is the Tresos version you are using? Can you describe more about how you added the modules you mentioned? or if you modified them? Is this the first time you use the PMIC, I2c and Dio modules? or have you used the example for each of them in the past? Thanks in advance for the information

LinuxでのUARTとしてのFlexIO 親愛なる皆様へ i.MX93のFlexIOについて説明が必要で、私の理解が正しいかどうかを確認したいと思います。 私たちの意図は、FlexIOをUARTとして使用して、Linuxを実行しているA55コアに追加のUARTを取得することでした。 最初のステップである devicetree での IOMUX の設定は、非常に簡単です。しかし、それでもドライバーが必要になります。しかし、まだあるのでしょうか? linux-imx リポジトリにも、imx-flexio ベース ドライバーと i2c ドライバーしかありません。 また、Linux用のそのようなflexio uartドライバーを開発することはあまり意味がありません、なぜならソフトウェアでやるべきことがまだ多すぎるからですか? リファレンスマニュアルには「FLEXIOはパリティビットの自動挿入には対応していません」と記載されています。 i.MX Linuxのリリースノートには、(flexio-i2cに関連して)次のように書かれています。「FlexIOには正確なタイミング要件があります。非リアルタイム ROS で FlexIO を使用すると、タイミングの問題が発生する可能性があります。非リアルタイムROSでの使用はお勧めしません。 FlexIOのものはM33コアとMCUの世界向けであるというのは正しいですか? それとも、LinuxでFlexIOを使用してフル機能のUARTを取得する方法はありますか? よろしく アンドレアス Re:Linuxの下でのUARTとしてのFlexIO 万が一の場合に備えて、誰かが同じことを疑問に思い、上記よりも詳細な答えを探しています。 AN14110は多くのヒントを与えてくれます 4 まとめ FlexIOは、さまざまなオペレーティングシステムでI2Cマスターとしてエミュレートできます。ただし、Linux環境でFlexIO I2Cを直接使用することはお勧めしません。Linux環境で読み取りまたは書き込み操作が正しく実行されることを確認するために、いくつかのチェックメカニズムを適用する必要があります。LinuxはRTOSではないため、割り込みの遅延や割り込みの応答時間を保証することはできません。Linuxは大きな割り込みレイテンシを生成する可能性がありますが、FlexIO IPは小さな割り込みレイテンシしか許容できません。 ZephyrなどのBareMetalまたはRTOS環境では、FlexIOは期待どおりに正常に動作します。

FlexIO as UART under Linux Dear all, I need some clarification on FlexIO on i.MX93 and would like to see if my understanding is correct. Our intention was to use FlexIO as a UART to get an extra UART on the A55 cores running Linux. The first step, setting up the IOMUX in the devicetree, would be quite simple. But then you would still need a driver. But is there one yet? Even in the linux-imx repo there is only an imx-flexio base driver and some i2c driver. Also, it would not make much sense to develop such a flexio uart driver for Linux, because there is still too much UART stuff to be done in software? The reference manual says "FLEXIO does not support automatic insertion of parity bits". The i.MX Linux release notes say (in connection with flexio-i2c): "FlexIO has precise timing requirements. Using FlexIO on non real-time ROS may cause timing problems. It is not recommended for use on non real-time ROS". Am I right that the FlexIO stuff is more for the M33 core and MCU world? Or is there a way to get a full-featured UART using FlexIO on Linux? Regards, Andreas Re: FlexIO as UART under Linux Just in case anyone is wondering the same thing and is looking for a more detailed answer than the one above. AN14110 gives many hints 4 Conclusion FlexIO can be emulated as the I2C master in different operating systems. However, it is not recommended to use FlexIO I2C in a Linux environment directly. Some check mechanisms should be applied to make sure the read or write operation is executed correctly in the Linux environment. Linux is not an RTOS, which means it cannot guarantee the interrupt latency or interrupt responding time. Linux may generate big interrupt latency while FlexIO IP can only tolerate small interrupt latency. In a BareMetal or RTOS environment, such as Zephyr, FlexIO can work normally as expected. Re: FlexIO as UART under Linux we suggest customer to use FlexIO as uart with M core, not under linux, the application below is useful for you https://www.nxp.com.cn/docs/en/application-note/AN12772.pdf

Linux 下 FlexIO 作为 UART 各位， 我需要对 i.MX93 上的 FlexIO 进行一些说明，并想看看我的理解是否正确。 我们的目的是使用 FlexIO 作为 UART，以在运行 Linux 的 A55 内核上获得额外的 UART。 第一步，在设备树中设置 IOMUX，非常简单。但你仍然需要一个司机。但现在已经有一个了吗？ 即使在 linux-imx repo 中也只有一个 imx-flexio 基础驱动程序和一些 i2c 驱动程序。 此外，为 Linux 开发这样的 flexio uart 驱动程序也没有多大意义，因为软件中还有太多 UART 工作要做？ 参考手册说“FLEXIO不支持自动插入奇偶校验位”。 i.MX Linux 发行说明指出（与 flexio-i2c 相关）：“FlexIO 具有精确的时间要求。在非实时 ROS 上使用 FlexIO 可能会导致时间问题。不建议在非实时 ROS 上使用”。 我是否正确地认为 FlexIO 更适合 M33 核心和 MCU 世界？ 或者有没有办法在 Linux 上使用 FlexIO 获得功能齐全的 UART？ 问候， 安德烈亚斯 回复：Linux 下 FlexIO 作为 UART 以防万一有人想知道同样的事情并正在寻找比上述更详细的答案。 AN14110 给出了许多提示 4 结论 FlexIO 可以在不同的操作系统中模拟为 I2C 主设备。但是，不建议在 Linux 环境中直接使用 FlexIO I2C。应该应用一些检查机制来确保在 Linux 环境中正确执行读取或写入操作。Linux不是RTOS，这意味着它无法保证中断延迟或中断响应时间。Linux 可能会产生较大的中断延迟，而 FlexIO IP 只能容忍较小的中断延迟。 在 BareMetal 或 RTOS 环境中，例如 Zephyr，FlexIO 可以按预期正常工作。

Freemaster 记录器数据不正确的问题 freemaster 之前一直用的是 2.0 版本，后来更新到 3.0 版本，Recorder 数据就不正确了

Does i.MX8M and plus series CPU support IEEE1588 V2? Does i.MX8M and plus series CPU support IEEE1588 V2? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Does i.MX8M and plus series CPU support IEEE1588 V2? Thanks for your quickly reply! Re: Does i.MX8M and plus series CPU support IEEE1588 V2? Hi cyesman: The i.MX 8M family can support IEEE 1588V2, the reference manual says IEEE 1588 message formats can encapsulated with the newer 1588v2 directly in Ethernet frames (layer 2.) You can refer to i.MX Linux Reference Manual  for the implementation. Section 4.2 ENET IEEE-1588   Please also note that iMX8M family support 1588V2 2-step , but not support 1-step. see below link for more details Can the i.MX8M (or 8M Plus) support 1588v2 1-Step? - NXP Community Regards Daniel

Online Activation Failed I tried install S23DS v3.4 with the license but it always failed like bottom picture. In my opinion its reason why is Reinstallation I have downloaded version 3.6 and activated it before. Re: Online Activation Failed Hi 1. The activation codes for S32DS v3.4 and v3.6 are different, please do not mix them. 2. You should find the activation code for S32 Design Studio version v.3.4 in the License List. The activation code for S32 Design Studio for S32 Platform v.3.4 with support for S32K3 devices cannot be used to install S32DS v3.4. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Online Activation Failed This is the license which is related with my problem. I capture this picture in my license list.

Problems with incorrect freemaster Recorder data freemaster had been using version 2.0 before, and later updated to version 3.0, the Recorder data became incorrect Re: Problems with incorrect freemaster Recorder data Hello, by using NXP FreeMASTER with microcontrollers from other vendor you are violating FreeMASTER license conditions. You have agreed with the conditions when downloading and then also when installing the FreeMASTER. You can only use FreeMASTER with NXP MCUs. Re: Problems with incorrect freemaster Recorder data Hello, I am using Freemaster version 3.2.4.3 Using STM32F103 MCU Uart communication used on MCU end The data in Figure 3 on the left appears to be incorrect and is using version 3.0, while the data in Figure 2 on the right is normal and is using version 2.0 Re: Problems with incorrect freemaster Recorder data Hello, we would need more information about the issue like: Exact version of the FreeMASTER tool (the latest is 3.2.4, see Help/About) What is the target MCU? What communication and driver software is used at the MCU side? (the latest can be found in various SDK packages or at GitHub) What do you mean by incorrect data? Thank you, Michal

Question about LLCE clock in S32G Hi NXP， I am using hardware as S32G274rdb2 and have implemented bootloader to drive 3 M cores + A core according to AN13750 with the following versions of each module: LLCE:1.0.8, RTD:4.0.2, Linux_BSP:BSP42 (kernel:5.15.158) I initialized LLCE in the M0 core and configured the llce_pe clock to 40M (FXOSC_CLK) and configured the baud rate of LLCE_can to 250k, but the LLCE_can output clock that I captured through the oscilloscope is incorrect, what could be the reason? Using clk dump in u-boot to get llce_can_pe clock as 0,as follows: 0                     0   |-- llce_can_pe 200000000   0   |-- llce_sys 80000000     0   |-- llce_per thanks， Re: Question about LLCE clock in S32G hi，youke Thank you for sharing your experience, and I am glad to help you, welcome to ask new ticket when you have other question. BR Joey Re: Question about LLCE clock in S32G Hi joey， I found that in tf-a, I did not modify the clock source in the device tree. After modifying it, the LLCE clock is correct. Thank you for your support; thanks， Re: Question about LLCE clock in S32G Hi joey， I found through testing that I configured the clock source for McuCGm0ClockMux7 in the bootloader to be FXOSC_CLK 40M. After booting to the M0 core, LLCE.can output correctly; If the output frequency of M0 core LLCEcan changes after the Linux startup of A core is completed, it is found through calculation that CAN-PE-CLK should be changed to 48M; I have already commented out all llce clocks in TF-A (see attachment for TF-A modifications). Do you still need to modify u-boot or kernel? How to modify? thanks Re: Question about LLCE clock in S32G hi,youke Have you configured the PLL as shown in the following picture? If you have done, and the tf-a did not start successfully after turning on the PLL clock in McuLockSettings Disable PLL, I thank it is not suitable for you. You can try unchecking the MCU control in Mux7. In addition,  you can try turning off the clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader, It's a suggested way for you. BR Joey Re: Question about LLCE clock in S32G Hi joey， 1. I have followed your instructions and configured the CANP_PE-CLK of M7-0 core to 80M, and configured the MCU ->McuLockSettingDnfig.0 CANP_PE-CLK of bootloader to 80M, The CANP_PE-CLK in McuLockSettings Disable PLL is not configured because I found that tf-a did not start successfully after turning on the PLL clock in McuLockSettings Disable PLL; After this configuration, my llce clock output still doesn't work; 2. I tried to shut down the operation of tf-a, but now the bootloader only starts M7-0/1/2 cores. However, the clock output of LLCE.can in M7-0 is still incorrect. Do you have any other troubleshooting ideas? thanks， Re: Question about LLCE clock in S32G hi,youke Thank you for your reply. There should be an incompatibility for the llce_can_pe between the M-core and A-core, you can turn off the clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader. In addition, in order to find the problem, you can try to configure CAN_PE_CLK as 40MHz in TF-A/u-boot, or set M core CAN_PE_CLK as 80Mhz as shown in the following picture. BR Joey Re: Question about LLCE clock in S32G Hi joey, 1.   I am currently using bootloader to pull up multi-core, and the initial program for M-core is IPCF. I have ported the LLCE code; 2.  I have tried to test the LLCE project of M core separately and it is available. 3.  I saw that the bootloader's sysdal module's powerUp ->SystemPowerUpConfiguration-0->DeinitList has the initialization of Mcu_initClock McuLockSetDisable PLL. I configured McuLockSetDisable PLL for Mcu ->McuLockSettingConfi and modified McuCGm0ClockMux7 as follows 4.  I followed the command in the bootloader you provided and used clk dump. I can see that llce_can_pe is 80000000. After entering the system, I tested that llce_can did not output, and the log showed that it was stuck in the Llce_fFirmware_Load function 5.  I am considering using bootloader to initialize all clocks for llce, and turning off clock operations for llce in tf-a, u-boot, and kernel, using the values configured in bootloader. Is this approach correct? thanks， Re: Question about LLCE clock in S32G Hi,youke Thank you for contacting us. Do you have a test  that only start M Core to capture the LLCE_can output clock? Please make sure you correctly configure the mux7 of MC_CGM _0 in MCU clock setting.  In addition, you can try to enable all LLCE clocks by referring to the attached picture. Hope it can help you. BR Joey

誤ったfreemasterレコーダーデータの問題 freemaster は以前バージョン 2.0 を使用していましたが、後にバージョン 3.0 に更新したため、Recorder のデータが正しくなくなりました