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Trouble implementing ios app using Taplinx SDK Hi, i'm trying to follow UG10045.pdf - Starting development with TapLinx iOS SDK. Below is excerpt from that guide: 3.4 Implementing the delegate method for APDU communication To communicate with the TapLinx iOS Library and the Tag (or Card), a delegate method which is created inside the MIFAREApduHandler must be implemented in your class. Below is the delegate method. However i do not understand where i should implement that TapLinxApduHandlerProtocol, on what class? Where/how should i pass my class to something in Taplinx SDK to indicate where i implemented that hander? Is there a ios sample app like for Android? It would be very helpful. In case there is no such app, could someone share a code sample with full sdk initialization on ios? Re: Trouble implementing ios app using Taplinx SDK Hello @DamianD  Since your problem involves the level of code debugging, we do not have such a test environment as yours, so your problem needs to be debugged by you, say sorry for that. Re: Trouble implementing ios app using Taplinx SDK hi @KaiLi  - unfortunately there is only swiftsourceinfo file inside Project folder and it is of no use to me. When i add libTapLinxLibrary.a to xcode app project (and set up search paths) during compilation i get error: /Users/xxx/Projects/xcodeproj/facilityapp/SampleTaplinxApp/SampleTaplinxApp/ContentView.swift:9:8 Compiled module was created by a different version of the compiler '5.10.0.13'; rebuild 'TapLinxLibrary' and try again: /Users/xxx/Projects/xcodeproj/facilityapp/SampleTaplinxApp/TapLinxLibrary2/TapLinxLibrary.swiftmodule/arm64-apple-ios.swiftmodule\ Could you hint me at what to do? Re: Trouble implementing ios app using Taplinx SDK thanks, i will give it a try and let you know Re: Trouble implementing ios app using Taplinx SDK Hello @DamianD  Unfortunately, there is not the dedicated sample for ios, but I think there should be something in SDK could refer to, like sdk_TapLinx_Library_iOS\TapLinxv1.0.1\TapLinxiOSSDK\TapLinxiOSSDK\TapLinxLibrary\TapLinxLibrary.swiftmodule\Project. Please try it.
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使用 Taplinx SDK 实现 iOS 应用时遇到问题 你好,我正在尝试遵循 UG10045.pdf - 使用 TapLinx iOS SDK 开始开发。以下是该指南的摘录: 3.4 实现APDU通信的委托方法 为了与 TapLinx iOS 库和标签(或卡)进行通信,需要在内部创建一个委托方法 您的类中必须实现 MIFAREpduHandler。下面是委托方法。 但是我不明白我应该在哪里实现 TapLinxApduHandlerProtocol,在哪个类上?我应该在哪里/如何将我的类传递给 Taplinx SDK 中的某个东西来指示我在哪里实现了该处理程序?是否有类似 Android 的 iOS 示例应用程序?这将会非常有帮助。如果没有这样的应用程序,有人可以分享一个在 ios 上具有完整 sdk 初始化的代码示例吗? 回复:使用 Taplinx SDK 实现 iOS 应用时遇到问题 你好@DamianD 由于您的问题涉及到代码调试层面,我们没有您这样的测试环境,所以您的问题需要您自行调试,对此我们深感抱歉。 回复:使用 Taplinx SDK 实现 iOS 应用时遇到问题 嗨@KaiLi - 不幸的是,项目文件夹中只有 swiftsourceinfo 文件,它对我来说没用。当我在编译期间将 libTapLinxLibrary.a 添加到 xcode 应用程序项目(并设置搜索路径)时出现错误: /用户/xxx/项目/xcodeproj/facilityapp/SampleTaplinxApp/SampleTaplinxApp/ContentView.swift:9:8编译模块是由不同版本的编译器“5.10.0.13”创建的;重建“TapLinxLibrary”并重试:/Users/xxx/Projects/xcodeproj/facilityapp/SampleTaplinxApp/TapLinxLibrary2/TapLinxLibrary.swiftmodule/arm64-apple-ios.swiftmodule\ 你能提示我该怎么做吗? 回复:使用 Taplinx SDK 实现 iOS 应用时遇到问题 谢谢,我会尝试一下并告诉你 回复:使用 Taplinx SDK 实现 iOS 应用时遇到问题 你好@DamianD 不幸的是,没有专门针对 iOS 的示例,但我认为 SDK 中应该有一些可以参考的东西,比如 sdk_TapLinx_Library_iOS\TapLinxv1.0.1\TapLinxiOSSDK\TapLinxiOSSDK\TapLinxLibrary\TapLinxLibrary.swiftmodule\项目。 请尝试一下。
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S32G2 IPC communication Dear members of NXP community, I have just started working on NXP S32G2 IPC framework. I am following app note AN13750: "Enabling Multicore Application on S32G2 using S32G2 Platform Software Integration" and I had a few questions: First off, if I understand the flow correctly from the document 1. Build Linux image with IPC and boot the A53 core using SD card. 2. Build the IPC image for M7 using design studio and use the bootloader to load the M7 into its SRAM. The bootloader is provided by the EB Tresos. 3. Start IP-communication from A53 with M7. Under the assumption that above understanding is correct, 1. Can I directly run the M7 application from design studio with a debugger. 2. Let the linux image boot from SD card on A53. 3. Start IPC communication with M7 from A53 linux. Is this possible? I do not want to deal with the EB bootloader as of now, unless, my understanding of the whole process is incorrect and this bootloader is crucial to the IPC functioning. Any comments/suggestions are welcome and appreciated. P.S. : I want to only use 1 M7 core instead of the 3 cores used in the app note. Best, Vishnu   Re: S32G2 IPC communication @chenyin_h thanks for all your help. I'm going to close this thread and open a new one for RAM related questions. Best, Vishnu  Re: S32G2 IPC communication Thanks @chenyin_h . I now see that the RAM utilisation is around 4 GB. And the swap space allocated is 0. Is there a way to increase the swap memory?  Best, Vishnu  Re: S32G2 IPC communication Hello, @Vishnu3  Thanks for your reply. BSP images that the A53 used are mainly work with DDR, DDR is initialized and then used at very early stage before U-Boot is running. BR Chenyin Re: S32G2 IPC communication Hello @chenyin_h , Thank you for the response, I managed to get the IPCF example running from U-boot. The normal blink binary is also working however that puts the the kernel into panic when it is booting, I will look into that later. So I have one last question, when the A53 image is executing, what is the RAM accessible to it? Does it only have access to the 8 MB SRAM or it has DRAM access as well? Please let me know. Best, Vishnu Re: S32G2 IPC communication Hello, @Vishnu3  Sorry that I do not see other formal document related to original topic(running IPCF via U-Boot). It is not recommended directly running the LED binary following the way that from the txt file you mentioned, the description.txt only provide method of using IPCF.bin directly from U-Boot, it is not targeted for other kinds of M core binaries. BR Chenyin Re: S32G2 IPC communication A quick question, I followed the desciption.txt file. But as a starter I did not load the IPCF project bin, instead I created a simple LED blink project and loaded it from Uboot but it is not working. Following are the steps I used: 1. Created a NXP DS project that blinks a blue LED on the S32G2. Tested with debugger, generated the bin file. NOTE: This bin was generated by the NXP and NOT from the IVT. I hope that is okay. Please confirm. 2. I placed this bin file in the boot section of the sd card which contains the A53 image. 3. Inserted the SD card and interrupted the auto boot so that I get access to the Uboot terminal. 4. Following commands were given as per "description.txt" modified as per the blinky project SRAM address => dcache off => fatload mmc 0:1 0x80000000 Siul2_Dio_Ip_Example_S32G274A_M7.bin [this returned with reading the bin file] => cp.b 0x80000000 0x34000000 0x100000 => startm7 0x34500400 [interrupt vector address as per map file of blinky project] [this returns saying that M7 core 0 has started at the address 0x34500400] RESULT: but the LED does not blink on the board Best, Vishnu Re: S32G2 IPC communication Edit: "Description.txt" Re: S32G2 IPC communication @chenyin_h  is there no other document apart from "document.txt" that tells how to load M7 from Uboot. I mean like an application note.  Best, Vishnu Re: S32G2 IPC communication Hello, @Vishnu3  Thanks for the reply. Sure, if any other issues found, you may also create other new posts, we are happy to support. B R Chenyin Re: S32G2 IPC communication @chenyin_h  thank you for the reply, I am trying the sequence you mentioned, will update in a couple of days. Best, Vishnu Re: S32G2 IPC communication Hello, @Vishnu3  Thanks for your post. If you only want to try the IPCF, and do not want to deal with the bootloader, it is still possible: 1. You may firstly build the IPCF_Example_S32G274A_M7_0 from the IPCF packages, once finished, a M7_0 application would be prepared. 2. Then directly boot the board with BSP(A53), stopped to the console of U-Boot. 3. Under U-Boot, following the instructions that shown from description.txt which could also be found under the IPCF_Example_S32G274A_M7_0. Then the IPCF communication example could run correctly between both A & M core. Hope it will help. BR Chenyin
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Visible+IR in black and white mode Hello,  I am using IMX8M plus for my application development, I have an 2MP RGB sensor with dual band pass filter lens (Visible+NIR 940nm), it outputs 12bit RAW RGB. Using IMX8M plus ISP, I need to fuse both visible and infrared (IR) data and convert into a single black and white (grayscale) image which can enhance imaging capabilities. Is this supported in the IMX8Mplus ISP? how can I achieve this, which API should I use it? Regards, i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Visible+IR in black and white mode Thanks, let me reach out to the local representative for the support on the tooling. Re: Visible+IR in black and white mode I don't have tuning tool so I didn't use tuning server before, since you need to request this tool, you can test after you get this tools, as my understanding, after you build the ISP sdk, you would get the library files, then you can use the tuning server by these library files Re: Visible+IR in black and white mode Yes, the tunning tool is required and I can request the local representative. but, Is that for tunning server I need to request for, I need to convert this onchip an not offline (tunning client)? Re: Visible+IR in black and white mode you should use tuning tool to support this,  for tuning tool,  you need contact local representative to get it  Re: Visible+IR in black and white mode I went through the reference document, basically there are two ways to tune to grayscale Image, tunning client is straight forward process with the documentation,  I would be more interested to use tunning server i.e, to run directly on IMX8M plus , Is tunning client required as well? or tunning server alone is sufficient, then with this 3 commands, can I convert into grayscaleImage? root@cn-szh02-ns-pr002:~/all# systemctl stop weston* root@cn-szh02-ns-pr002:~/all# chmod 777 tuningext root@cn-szh02-ns-pr002:~/all# ./tuningext& Re: Visible+IR in black and white mode I attached the AN for your reference, you can ty to use the tools to tune the ISP to check if it has the feature you need Re: Visible+IR in black and white mode I understand this is not tested and guaranteed, but is there an API available or any alternate solution available to convert into an grayscale Image, I can test this. Re: Visible+IR in black and white mode this is my another case, I confirmed that we couldn't guarantee this because we don't test this yet Solved: MX8MP ISP with IR wavelengths - NXP Community
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Taplinx SDKを使用したiOSアプリの実装の問題 こんにちは、私はUG10045.pdfをフォローしようとしています-TapLinx iOSSDKで開発を開始します。以下は、そのガイドからの抜粋です。 3.4 APDU通信のデリゲートメソッドの実装 TapLinx iOSライブラリとタグ(またはカード)と通信するには、内部に作成されるデリゲートメソッド MIFAREApduHandler は、クラスに実装する必要があります。以下はデリゲートメソッドです。 しかし、私はそのTapLinxApduHandlerProtocolをどこに実装すべきか、どのクラスに理解していませんか?Taplinx SDKのどこにクラスを渡して、そのハンダーをどこに実装したかを示す必要がありますか?AndroidのようなiOSのサンプルアプリはありますか?とても助かります。そのようなアプリがない場合、誰かがiOSで完全なsdk初期化を含むコードサンプルを共有できますか? Re:Taplinx SDKを使用したiOSアプリの実装の問題 こんにちは@DamianD  あなたの問題はコードのデバッグのレベルに関係しているため、私たちはあなたのようなテスト環境を持っていませんので、あなたの問題はあなたがデバッグする必要があります。 Re:Taplinx SDKを使用したiOSアプリの実装の問題 こんにちは@KaiLi-残念ながら、プロジェクトフォルダ内にはswiftsourceinfoファイルしかなく、私には役に立ちません。コンパイル中にlibTapLinxLibrary.aをxcodeアプリプロジェクトに追加する(および検索パスを設定する)と、次のエラーが発生します。 /Users/xxx/Projects/xcodeproj/facilityapp/SampleTaplinxApp/SampleTaplinxApp/ContentView.swift:9:8コンパイルされたモジュールは、コンパイラ '5.10.0.13' の異なるバージョンによって作成されました。'TapLinxLibrary' を再構築して、再試行してください: /Users/xxx/Projects/xcodeproj/facilityapp/SampleTaplinxApp/TapLinxLibrary2/TapLinxLibrary.swiftmodule/arm64-apple-ios.swiftmodule\ どうすればいいのか教えていただけますか? Re:Taplinx SDKを使用したiOSアプリの実装の問題 ありがとう、私はそれを試してみて、あなたに知らせます Re:Taplinx SDKを使用したiOSアプリの実装の問題 こんにちは@DamianD  残念ながら、ios専用のサンプルはありませんが、SDKには参照できるものがあるはずだと思います。 sdk_TapLinx_Library_iOS\TapLinxv1.0.1\TapLinxiOSSDK\TapLinxiOSSDK\TapLinxLibrary\TapLinxLibrary.swiftmodule\Projectです。 ぜひお試しください。
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UART configuration and operation for LPC55S16 Hi, I am using the LPC55S16 evaluation board. In our design, there is a UART that needs to be configured for half-duplex operation. It should normally function in RX mode, but when receiving data, it should switch to TX mode to send a response back. Later, at some point, we need to convert the UART to full-duplex operation. Is this achievable? If so, how can it be done? Regards, Winston Re: UART configuration and operation for LPC55S16 Hi, Follow up question, when  the UART works in half duplex mode, actually I need to set it as one-wire UART - the TX and RX are in the same line. When the UART works in full duplex mode, the TX and RX are separate lines. Is there a solution for this kind of settings? Regards, Winston Re: UART configuration and operation for LPC55S16 HI @yangao  Yes, you can configure the UART on the LPC55S16 for both half-duplex and full-duplex operation. Configure UART initially for receiving (RX) USART_GetDefaultConfig(&config); config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; config.enableTx = false; config.enableRx = true; USART_Init(DEMO_USART, &config, DEMO_USART_CLK_FREQ); Configure UART for full-duplex (TX and RX enabled) USART_GetDefaultConfig(&config); config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; config.enableTx = true; config.enableRx = true; USART_Init(DEMO_USART, &config, DEMO_USART_CLK_FREQ); BR Hang
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[MPC5777c] SDADC with using DMA Hello. I'm trying to SDADC with using DMA for resolver Sin & Cos Signals. So now I'm reffering to eTPURDCCUG.pdf with example codes (Example_MPC5777C-SDADC_eTPU_triggered_v0_0-GHS714 & Example_MPC5777C_DSPI_Master_TXRX_DMA_S32DSPower21) eTPURDCCUG.pdf suggets three DMA channels are used – two channels to transfer the ADC data of Sine and Cosine signals, and one channel to transfer the HSRs. I wanna use SDA[0], SDA[1] for Sin signal and Cos signal. Sin signal - SDA0 Cos signal - SDA1 Now I'm using eQADC with DMA, below the source code is summary of DMA init for eQADC.  ---- No 1. summary of DMA init for eQADC --- DMA_A.TCD[0].SADDR.R = (vuint32_t) &A_CQUEUEX0; //  Start Address DMA_A.TCD[0].DADDR.R =  CFIFO_A0_PUSH;    //  Destination address   DMA_A.TCD[1].SADDR.R = RFIFO_A0_POP;      //  Start Address // DMA_A.TCD[1].DADDR.R = (vuint32_t) &A_RQUEUEX0;//  Destination address   DMA_A.TCD[2].SADDR.R = (vuint32_t) &A_CQUEUEX1; //  Start Address DMA_A.TCD[2].DADDR.R =  CFIFO_A1_PUSH;    //  Destination address   DMA_A.TCD[3].SADDR.R = RFIFO_A1_POP;      //  Start Address // DMA_A.TCD[3].DADDR.R = (vuint32_t) &A_RQUEUEX1;//  Destination address   DMA_B.TCD[0].SADDR.R = (vuint32_t) &B_CQUEUEX0; //  Start Address DMA_B.TCD[0].DADDR.R =  CFIFO_B0_PUSH;    //  Destination address   DMA_B.TCD[1].SADDR.R = RFIFO_B0_POP;      //  Start Address // DMA_B.TCD[1].DADDR.R = (vuint32_t) &B_RQUEUEX0;//  Destination address   DMA_B.TCD[2].SADDR.R = (U32)&B_CQUEUEX1; //  Start Address DMA_B.TCD[2].DADDR.R = CFIFO_B1_PUSH;    //  Destination address   DMA_B.TCD[3].SADDR.R = RFIFO_B1_POP;      //  Start Address //eQADC DMA_B.TCD[3].DADDR.R = (U32)&B_RQUEUEX1;//  Destination address ---- End of summary ----   ----- No 2. Construction of DMA init for eQADC ----- DMA_A.TCD[0].SADDR.R = (vuint32_t) &A_CQUEUEX0; //  Start Address DMA_A.TCD[0].DADDR.R =  CFIFO_A0_PUSH;    //  Destination address DMA_A.TCD[0].ATTR.B.SMOD = 0x00; //  Source address modulo DMA_A.TCD[0].ATTR.B.DMOD = 0x00; //  Destination address modulo DMA_A.TCD[0].ATTR.B.DSIZE = 0x02; //  Destination transfer size : 32 Bits DMA_A.TCD[0].ATTR.B.SSIZE = 0x02; //  Source transfer size : 32 Bits DMA_A.TCD[0].SOFF.R = 0x04; //  Signed source address offset DMA_A.TCD[0].NBYTES.MLNO.R = 0x00000004; //  Inner "minor" byte count DMA_A.TCD[0].SLAST.R = -16; //  last Signed source address adjust DMA_A.TCD[0].DOFF.R = (vint16_t)0x0;    //  Signed destination address offset DMA_A.TCD[0].DLASTSGA.R = (vint32_t)0x0; //  Signed destination address adjust DMA_A.TCD[0].BITER.ELINKYES.B.ELINK = 0x00; //  Disable Channel Linking  Minor Loop Channel Linking Disabled DMA_A.TCD[0].BITER.ELINKYES.B.BITER = 0x0004; //  Beginning "major" iteration count - Minor Loop Channel Linking Disabled DMA_A.TCD[0].CITER.ELINKYES.B.ELINK = 0x00;    //  Disable Channel Linking  Minor Loop Channel Linking Disabled DMA_A.TCD[0].CITER.ELINKYES.B.CITER = 0x0004; //  Current "major" iteration count - Minor Loop Channel Linking Disabled DMA_A.TCD[0].CSR.B.BWC = 0x00; //  Bandwidth control :  No DMA Stalls DMA_A.TCD[0].CSR.B.MAJORLINKCH = 0x00; //  Major Channel number DMA_A.TCD[0].CSR.B.MAJORELINK = 0x0; //  Major Channel Link : Disabled DMA_A.TCD[0].CSR.B.DONE = 0x00; //  Channel Done DMA_A.TCD[0].CSR.B.ACTIVE = 0x00; //  Channel ACtive DMA_A.TCD[0].CSR.B.ESG = 0x0; DMA_A.TCD[0].CSR.B.DREQ = 0x0; DMA_A.TCD[0].CSR.B.INTHALF = 0x0; DMA_A.TCD[0].CSR.B.INTMAJOR = 0x0; DMA_A.TCD[0].CSR.B.START = 0; ----- End of construction of DMA init for eQADC-----   ------ No.3 Construction  of SDADC_init from Example code ----- void SDADC2_Init(void) { /* for comments see SDADC1_Init */ SIU.SDCLKCFG.R = 0x0000003F; SDADC_2.MCR.B.EN = 1; /* TRIGSEL = 0101b = 5 = eTPU_A23 */ SDADC_2.MCR.R = 0x00001593; SDADC_2.CSR.R = 0x0; SDADC_2.OSDR.R = 0xFF; SDADC_2.FCR.R = 0x107; SDADC_2.RSER.R = 0x00000001; } ------ End of construction SDADC_init  from Example code ------     *Question 1. how do I apply SDADC with using DMA for Sin - SDA[0], Cos - SDA[1], HSR ? (Based on above eQADC code)   2. Can I perform DMA initialization for SDADC using the same structure as the DMA source code configuration for eQADC as in No.2 above? (If not, Please let me know how to configurate)   3.To initialize SDADC using DMA, Is it correct to configure SDADC initialization in the same way as example code 3 above? (If not, Please let me know how to configurate)   Thank you for always helping me.   MPC5777C  Re: [MPC5777c] SDADC with using DMA I see. This table is described quite straightforward. Use recommended values. For SDADC following channels is supposed to be used (eDMA_B): For HSR, you may use any channel. Re: [MPC5777c] SDADC with using DMA Thank you for your answer. I'm a beginner level so I couldn't understand much of your explained without exmaples... Can you show me how should I configure SDADC with using DMA? I want to configure DMA configuration as shown in the table below. I want to use SDA0 and SDA1 channel for Sine ADC FIFO DMA channel and Cosine ADC FIFO DMA channel, but I'm already using TCD[0] and TCD[1] for eQADC. If I want to use SDA0 and SDA1 channel for DMA Channel, How should I do? Re: [MPC5777c] SDADC with using DMA According sketch in shows using differential inputs i.e. SIN by one pair of inputs, COS by another pair. In comparison to eQADC - SDADC does not use any commands as you have in the TCD above. You will only need DMA transfers for results' draining. Some general words to SDADC: SDADC is targeted to high-precision, moderate input bandwidth AC signal processing (knock detection/in pressure cylinder control). Once enabled the SDADC keeps running. There is no “Single conversion mode”. This requires converted data to be continually drained by DMA or ISR. The digital nature of the SDADC means that there is a propagation delay as the data is clocked through the internal digital filters. This has to be taken into account at startup or at any channel mux change. This latency means that the SDADC is not well suited to some applications including motor control. When used in an AC sampling application it is likely that each SDADC will have to be dedicated to a particular input rather than switching the input channel. SDADC offers higher conversion accuracy (16-bit result). SDADC is always combined with other type of ADC, on this device it is eQADC offering advanced triggering and channel multiplexing capability (on other MPC57xx device SDADC is supplemented by SAR ADC).
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S32G2 IPC通信 NXPコミュニティの親愛なるメンバーの皆様、 私はちょうどNXP S32G2 IPCフレームワークに取り組み始めました。私は次のアプリケーションノートAN13750ています:「S32G2でのマルチコアアプリケーションの有効化 using S32G2 Platform Software Integration」と題し、いくつかの疑問を抱きました。 まず、ドキュメントからの流れを正しく理解しているかどうか 1. IPCを使用してLinuxイメージをビルドし、SDカードを使用してA53コアを起動します。 2. Design Studio を使用して M7 の IPC イメージをビルドし、ブートローダーを使用して M7 を SRAM に読み込みます。ブートローダーはEB Tresosによって提供されます。 3. A53からM7でIP通信を開始します。 上記の理解が正しいことを前提として、 1. デバッガを使用して、デザインスタジオからM7アプリケーションを直接実行できますか。 2. LinuxイメージをA53のSDカードから起動させます。 3. A53 linuxからM7とのIPC通信を開始します。 これは可能ですか?私は今のところEBブートローダーを扱いたくありませんが、プロセス全体についての私の理解が間違っていて、このブートローダーがIPCの機能にとって重要である場合を除きます。どんなコメント/提案も大歓迎です。 PS:アプリケーションノートで使用されている3つのコアではなく、1つのM7コアのみを使用したいです。 最良 ヴィシュヌ Re:S32G2 IPC通信 編集:「Description.txt」
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ReadObject can't read binary file in sessionless access PnT nano How to I allow my ReadObject command to output a binary file while in sessionless access? I am just receiving 0's when checking for content, instead of the actual content. Maybe I have to set policies differently when writing the binary file? I thought default policies enable all access. SE050 Re: ReadObject can't read binary file in sessionless access PnT nano Hi @Jansch , Please kindly refer to https://github.com/NXPPlugNTrust/nano-package/blob/ccd5782c1acc855b4bee7be9de6a1d6c9416e7e0/examples/se05x_qi_auth/sa_qi_transmitter_auth/sa_qi_transmitter_helpers.c#L158 for details. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: ReadObject can't read binary file in sessionless access PnT nano Thank you very much for your answer Kan! Is there an example on how to do this with the nano mw aswell, which doesn't have the SSS API? Best wishes Jansch Re: ReadObject can't read binary file in sessionless access PnT nano Hi @Jansch , The demo in simw-top\demos\se05x\se05x_GetCertificate shows how to use SSS APIs to get a certificate in the SE, you may use it as a reference. Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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IMX8DQ ENET consumption of shared resources Hello, I am currently working on the ENET module. I would like to know if it consumes any shared resources during the MAC receive process other than the "Write FIFO data and frame state" step ? Best regards i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: IMX8DQ ENET consumption of shared resources Hello Joseph, Thank you for your prompt reply! I just wanted to make sure. Kind regards, Kevin N Re: IMX8DQ ENET consumption of shared resources Hi, Thank you for your interest in NXP Semiconductor products, It does not. The MAC receive process is: • Check frame framing • Remove frame preamble and frame SFD field • Discard frame based on frame destination address field • Terminate pause frames • Check frame length • Remove payload padding if it exists • Calculate and verify CRC-32 • Write received frames in the core receive FIFO All of it is performed in ENET module itself. Regards
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İ.MX8 Dual Camera Under Single MIPI CSI Hi all, I want to get stream from two of my cameras in single MIPI CSI. Currently I have the setup below: I did find some useful information on the below forum post: bring up dual Camera under single mipi csi  however, those modifications didn't work for me, but it was a good head start. I change the device tree like below: fragment@9 { target = <&irqsteer_csi0>; __overlay__ { status = "okay"; }; }; fragment@10 { target = <&irqsteer_csi1>; __overlay__ { status = "okay"; }; }; fragment@11 { target = <&mipi_csi_0>; __overlay__ { #address-cells = <1>; #size-cells = <0>; status = "okay"; /* Camera 0 MIPI CSI-2 (CSIS0) */ port@0 { reg = <0>; mipi_csi0_ep_0: endpoint { remote-endpoint = <&as0149_serdes_ep_0>; data-lanes = <1 2>; csis-hs-settle = <10>; }; }; port@2 { reg = <2>; mipi_csi0_ep_1: endpoint { remote-endpoint = <&as0149_serdes_ep_1>; data-lanes = <1 2>; csis-hs-settle = <10>; }; }; }; }; fragment@12 { target = <&isi_0>; __overlay__ { status = "okay"; cap_device { status = "okay"; }; m2m_device { status = "okay"; }; }; }; fragment@12 { target = <&isi_1>; __overlay__ { status = "okay"; cap_device { status = "okay"; }; m2m_device { status = "okay"; }; }; }; fragment@13 { target = <&mipi_csi_1>; __overlay__ { #address-cells = <1>; #size-cells = <0>; status = "okay"; /* Camera 2 MIPI CSI-2 (CSIS2) */ port@1 { reg = <1>; mipi_csi1_ep_0: endpoint { remote-endpoint = <&as0149_serdes_ep_2>; data-lanes = <1 2>; }; }; port@3 { reg = <3>; mipi_csi1_ep_1: endpoint { remote-endpoint = <&as0149_serdes_ep_3>; data-lanes = <1 2>; }; }; /* Camera 3 MIPI CSI-2 (CSIS3) */ }; }; fragment@14 { target = <&isi_4>; __overlay__ { status = "okay"; cap_device { status = "okay"; }; m2m_device { status = "okay"; }; }; }; fragment@14 { target = <&isi_5>; __overlay__ { status = "okay"; cap_device { status = "okay"; }; m2m_device { status = "okay"; }; }; }; };   and here is the changes I made on the `imx8-mipi-csi2-sam.c` and `imx8-media-dev.c`.  diff --git a/drivers/staging/media/imx/imx8-media-dev.c b/drivers/staging/media/imx/imx8-media-dev.c index 0d0355844eab..c18a1b15265f 100644 --- a/drivers/staging/media/imx/imx8-media-dev.c +++ b/drivers/staging/media/imx/imx8-media-dev.c @@ -35,8 +35,8 @@ #define ISI_OF_NODE_NAME "isi" #define MIPI_CSI2_OF_NODE_NAME "csi" -#define MXC_MAX_SENSORS 3 -#define MXC_MIPI_CSI2_MAX_DEVS 2 +#define MXC_MAX_SENSORS 4 +#define MXC_MIPI_CSI2_MAX_DEVS 4 #define MXC_NAME_LENS 32 @@ -516,6 +516,7 @@ static int mxc_md_create_links(struct mxc_md *mxc_md) source->name, sink->name); } else if (mxc_md->mipi_csi2[sensor->id].sd) { mipi_csi2 = &mxc_md->mipi_csi2[sensor->id]; + v4l2_info(&mxc_md->v4l2_dev, "sensor->id is (%d)\n", sensor->id);//joan source = &sensor->sd->entity; sink = find_entity_by_name(mxc_md, mipi_csi2->sd_name); @@ -523,7 +524,9 @@ static int mxc_md_create_links(struct mxc_md *mxc_md) sink_pad = source_pad; mipi_vc = (mipi_csi2->vchannel) ? 4 : 1; + v4l2_info(&mxc_md->v4l2_dev, "mipi_vc is (%d)\n", mipi_vc); for (j = 0; j < mipi_vc; j++) { + v4l2_info(&mxc_md->v4l2_dev, "j is (%d)\n", j); ret = media_create_pad_link(source, source_pad + j, sink, @@ -958,8 +961,8 @@ static int mxc_md_register_platform_entities(struct mxc_md *mxc_md, static int register_sensor_entities(struct mxc_md *mxc_md) { struct device_node *parent = mxc_md->pdev->dev.of_node; - struct device_node *node, *ep, *rem; - struct v4l2_fwnode_endpoint endpoint; + struct device_node *node, *ep, *ep1, *rem, *rem1; + struct v4l2_fwnode_endpoint endpoint, endpoint1; struct i2c_client *client; struct v4l2_async_subdev *asd; int index = 0; @@ -967,9 +970,12 @@ static int register_sensor_entities(struct mxc_md *mxc_md) mxc_md->num_sensors = 0; + v4l2_info(&mxc_md->v4l2_dev, "port full name is %s\n", mxc_md->pdev->dev.of_node->name);//joan + /* Attach sensors linked to MIPI CSI2 / paralle csi / HDMI Rx */ for_each_available_child_of_node(parent, node) { struct device_node *port; + struct device_node *port1; if (!of_node_cmp(node->name, HDMI_RX_OF_NODE_NAME)) { mxc_md->sensor[index].fwnode = of_fwnode_handle(node); @@ -990,16 +996,25 @@ static int register_sensor_entities(struct mxc_md *mxc_md) continue; /* csi2 node have only port */ - port = of_get_next_child(node, NULL); + //port = of_get_next_child(node, NULL);//joan + port1 = of_get_next_child(node, NULL);//joan + port = of_get_next_child(node, port1);//joan + v4l2_info(&mxc_md->v4l2_dev, "port full name is %s\n", port->full_name);//joan + v4l2_info(&mxc_md->v4l2_dev, "port name is %s\n", port->name);//joan if (!port) continue; /* port can have only endpoint */ ep = of_get_next_child(port, NULL); + ep1 = of_get_next_child(port1, NULL); + v4l2_info(&mxc_md->v4l2_dev, "ep full name is %s and ep name is %s\n", ep->full_name, ep->name);//joan + if (!ep) return -EINVAL; memset(&endpoint, 0, sizeof(endpoint)); + memset(&endpoint1, 0, sizeof(endpoint1)); + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep1), &endpoint1); ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &endpoint); if (WARN_ON(endpoint.base.port >= MXC_MAX_SENSORS || ret)) { v4l2_err(&mxc_md->v4l2_dev, @@ -1007,14 +1022,21 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return -EINVAL; } + if (endpoint1.base.port ==2)//joan + endpoint1.base.port=0; //joan + if (endpoint1.base.port ==3)//joan + endpoint1.base.port=1; //joan mxc_md->sensor[index].id = endpoint.base.port; + mxc_md->sensor[index+1].id = endpoint1.base.port; if (!of_node_cmp(node->name, MIPI_CSI2_OF_NODE_NAME)) mxc_md->sensor[index].mipi_mode = true; /* remote port---sensor node */ + rem1 = of_graph_get_remote_port_parent(ep1); rem = of_graph_get_remote_port_parent(ep); of_node_put(ep); + of_node_put(ep1); if (!rem) { v4l2_info(&mxc_md->v4l2_dev, "Remote device at %s not found\n", @@ -1025,6 +1047,7 @@ static int register_sensor_entities(struct mxc_md *mxc_md) /* * Need to wait sensor driver probed for the first time */ + client = of_find_i2c_device_by_node(rem1); client = of_find_i2c_device_by_node(rem); if (!client) { v4l2_info(&mxc_md->v4l2_dev, @@ -1033,7 +1056,12 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return -EPROBE_DEFER; } + mxc_md->sensor[index+1].fwnode = of_fwnode_handle(rem1); mxc_md->sensor[index].fwnode = of_fwnode_handle(rem); + asd = v4l2_async_notifier_add_fwnode_subdev( + &mxc_md->subdev_notifier, + mxc_md->sensor[index+1].fwnode, + struct v4l2_async_subdev); asd = v4l2_async_notifier_add_fwnode_subdev( &mxc_md->subdev_notifier, mxc_md->sensor[index].fwnode, @@ -1043,9 +1071,9 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return PTR_ERR(asd); } - mxc_md->num_sensors++; + mxc_md->num_sensors += 2; - index++; + index += 2; } return 0; @@ -1118,8 +1146,8 @@ static int mxc_md_probe(struct platform_device *pdev) mxc_md_clean_unlink_channels(mxc_md); } else { /* no sensors connected */ - mxc_md_unregister_all(mxc_md); - v4l2_async_notifier_unregister(&mxc_md->subdev_notifier); + //mxc_md_unregister_all(mxc_md); + //v4l2_async_notifier_unregister(&mxc_md->subdev_notifier); } } } @@ -1168,7 +1196,19 @@ static struct platform_driver mxc_md_driver = { .remove = mxc_md_remove, }; -module_platform_driver(mxc_md_driver); + +static int __init mxc_md_driver_init(void) +{ + return platform_driver_register(&mxc_md_driver); +} + +static void __exit mxc_md_driver_exit(void) +{ + platform_driver_unregister(&mxc_md_driver); +} + +late_initcall(mxc_md_driver_init); +module_exit(mxc_md_driver_exit); MODULE_AUTHOR("Freescale Semiconductor, Inc."); MODULE_DESCRIPTION("MXC Media Device driver"); diff --git a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c index 1d12365520a6..c94dd8ee721d 100644 --- a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c +++ b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c @@ -46,7 +46,7 @@ #define CSIS_DRIVER_NAME "mxc-mipi-csi2-sam" #define CSIS_SUBDEV_NAME "mxc-mipi-csi2" -#define CSIS_MAX_ENTITIES 2 +#define CSIS_MAX_ENTITIES 4 #define CSIS0_MAX_LANES 4 #define CSIS1_MAX_LANES 2 @@ -1486,6 +1486,7 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, struct csi_state *state) { struct device_node *node = pdev->dev.of_node; + struct device_node *node1; state->index = of_alias_get_id(node, "csi"); @@ -1495,7 +1496,9 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, if (of_property_read_u32(node, "bus-width", &state->max_num_lanes)) return -EINVAL; - node = of_graph_get_next_endpoint(node, NULL); + //node = of_graph_get_next_endpoint(node, NULL); + node1 = of_graph_get_next_endpoint(node, NULL); + node = of_graph_get_next_endpoint(node, node1); if (!node) { dev_err(&pdev->dev, "No port node\n"); return -EINVAL; @@ -1505,10 +1508,14 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, of_property_read_u32(node, "csis-hs-settle", &state->hs_settle); of_property_read_u32(node, "csis-clk-settle", &state->clk_settle); of_property_read_u32(node, "data-lanes", &state->num_lanes); + of_property_read_u32(node1, "csis-hs-settle", &state->hs_settle); + of_property_read_u32(node1, "csis-clk-settle", &state->clk_settle); + of_property_read_u32(node1, "data-lanes", &state->num_lanes); state->wclk_ext = of_property_read_bool(node, "csis-wclk"); of_node_put(node); + of_node_put(node1); return 0; } with the above changes I manage to get this log from the dmesg: [ 13.882103] mxc-mipi-csi2 58227000.csi: lanes: 2, name: mxc-mipi-csi2.0 [ 13.910417] mxc-mipi-csi2 58247000.csi: lanes: 2, name: mxc-mipi-csi2.1 [ 13.925936] mxc-isi 58110000.isi: mxc_isi.1 registered successfully [ 13.933616] mxc-isi 58150000.isi: mxc_isi.5 registered successfully [ 13.945677] mx8-img-md: Registered mxc_isi.1.capture as /dev/video2 [ 13.952694] mx8-img-md: Registered mxc_isi.5.capture as /dev/video3 [ 13.959160] mx8-img-md: port full name is camera [ 13.963813] mx8-img-md: port full name is port@0 [ 13.968440] mx8-img-md: port name is port [ 13.972455] mx8-img-md: ep full name is endpoint and ep name is endpoint [ 13.979270] mx8-img-md: port full name is port@1 [ 13.983896] mx8-img-md: port name is port [ 13.987913] mx8-img-md: ep full name is endpoint and ep name is endpoint [ 13.994738] mx8-img-md: Registered sensor subdevice: as0149 3-005f (1) [ 14.002070] mx8-img-md: Registered sensor subdevice: as0149 3-005e (2) [ 14.009413] mx8-img-md: created link [mxc_isi.1] => [mxc_isi.1.capture] [ 14.016050] mx8-img-md: created link [mxc-mipi-csi2.0] => [mxc_isi.1] [ 14.022527] mx8-img-md: created link [mxc_isi.5] => [mxc_isi.5.capture] [ 14.029150] mx8-img-md: created link [mxc-mipi-csi2.1] => [mxc_isi.5] [ 14.035616] mx8-img-md: sensor->id is (1) [ 14.039634] mx8-img-md: mipi_vc is (1) [ 14.043386] mx8-img-md: j is (0) [ 14.046632] mx8-img-md: created link [as0149 3-005f] => [mxc-mipi-csi2.1] [ 14.054212] mx8-img-md: sensor->id is (1) [ 14.058238] mx8-img-md: mipi_vc is (1) [ 14.061997] mx8-img-md: j is (0) [ 14.065228] mx8-img-md: created link [as0149 3-005e] => [mxc-mipi-csi2.1] [ 14.072817] mxc-md bus@58000000:camera: mxc_md_create_links [ 14.078833] mxc-md bus@58000000:camera: mxc_md_do_clean get remote pad fail [ 14.085829] mxc_md_clean_unlink_channels: clean channel fail(0) however as you can see I have a remote pad fail error, and also below error: [ 18.034390] mxc-mipi-csi2.0: is_entity_link_setup, No remote pad found! I can see that it links on the media-ctl: root@sm2s-imx8:~/test-suite/camera# media-ctl -p -d 1 Media controller API version 5.15.71 Media device information ------------------------ driver mxc-md model FSL Capture Media Device serial bus info hw revision 0x0 driver version 5.15.71 Device topology - entity 1: mxc_isi.1 (16 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 pad0: Sink pad1: Sink <- "mxc-mipi-csi2.0":5 [ENABLED] pad2: Sink pad3: Sink pad4: Sink pad5: Sink pad6: Sink pad7: Sink pad8: Sink pad9: Sink pad10: Sink pad11: Sink pad12: Source -> "mxc_isi.1.capture":0 [ENABLED] pad13: Source pad14: Source pad15: Sink - entity 18: mxc_isi.1.capture (1 pad, 1 link) type Node subtype V4L flags 0 device node name /dev/video2 pad0: Sink <- "mxc_isi.1":12 [ENABLED] - entity 22: mxc_isi.5 (16 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 pad0: Sink pad1: Sink pad2: Sink pad3: Sink pad4: Sink pad5: Sink <- "mxc-mipi-csi2.1":5 [ENABLED] pad6: Sink pad7: Sink pad8: Sink pad9: Sink pad10: Sink pad11: Sink pad12: Source -> "mxc_isi.5.capture":0 [ENABLED] pad13: Source pad14: Source pad15: Sink - entity 39: mxc_isi.5.capture (1 pad, 1 link) type Node subtype V4L flags 0 device node name /dev/video3 pad0: Sink <- "mxc_isi.5":12 [ENABLED] - entity 43: mxc-mipi-csi2.0 (8 pads, 1 link) type Node subtype V4L flags 0 device node name /dev/v4l-subdev0 pad0: Sink pad1: Sink pad2: Sink pad3: Sink pad4: Source pad5: Source -> "mxc_isi.1":1 [ENABLED] pad6: Source pad7: Source - entity 52: mxc-mipi-csi2.1 (8 pads, 3 links) type Node subtype V4L flags 0 device node name /dev/v4l-subdev1 pad0: Sink <- "as0149 3-005f":0 [ENABLED,IMMUTABLE] <- "as0149 3-005e":0 [ENABLED,IMMUTABLE] pad1: Sink pad2: Sink pad3: Sink pad4: Source pad5: Source -> "mxc_isi.5":5 [ENABLED] pad6: Source pad7: Source - entity 61: as0149 3-005f (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 pad0: Source -> "mxc-mipi-csi2.1":0 [ENABLED,IMMUTABLE] - entity 63: as0149 3-005e (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 pad0: Source -> "mxc-mipi-csi2.1":0 [ENABLED,IMMUTABLE] however when I try to stream I get the following error: [ 1271.639925] subdev->entity.num_pads = 16 [ 1271.639952] subdev->entity.num_pads = 8 [ 1271.644613] mxc-mipi-csi2.0: is_entity_link_setup, No remote pad found! [ 1271.655623] subdev->entity.num_pads = 16 [ 1271.655638] subdev->entity.num_pads = 8 [ 1271.659931] subdev->entity.num_pads = 16 [ 1271.685547] subdev->entity.num_pads = 16 [ 1271.689520] subdev->entity.num_pads = 8 [ 1271.693488] mxc-mipi-csi2.0: is_entity_link_setup, No remote pad found! [ 1271.706157] subdev->entity.num_pads = 16 [ 1271.706178] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.717394] subdev->entity.num_pads = 16 [ 1271.717408] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.728498] subdev->entity.num_pads = 16 [ 1271.728509] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.739767] subdev->entity.num_pads = 16 [ 1271.739788] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.754653] subdev->entity.num_pads = 16 [ 1271.754669] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.768329] subdev->entity.num_pads = 16 [ 1271.768344] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.779549] subdev->entity.num_pads = 16 [ 1271.779561] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.790708] subdev->entity.num_pads = 16 [ 1271.790727] mxc-mipi-csi2.0: mipi_csi2_enum_framesizes, No remote pad found! [ 1271.803980] subdev->entity.num_pads = 16 [ 1271.803996] mxc-mipi-csi2.0: mipi_csi2_g_frame_interval, No remote pad found! [ 1271.837543] subdev->entity.num_pads = 16 [ 1271.837568] mxc-mipi-csi2.0: mipi_csi2_s_power, No remote pad found! [ 1271.847946] mxc_isi.1: Call subdev s_power fail! maybe if I solve the padding error I might able to get a stream ? hopefully :). Can you help me on this ? I kind of stuck at this.  Thanks! i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: İ.MX8 Dual Camera Under Single MIPI CSI Hi all, Below you can find how you can create virtual channels in i.mx8 board. I manage to create 4 virtual channels and get a stream from all 4 of them: diff --git a/drivers/staging/media/imx/imx8-media-dev.c b/drivers/staging/media/imx/imx8-media-dev.c index 0d0355844..4d86eadc0 100644 --- a/drivers/staging/media/imx/imx8-media-dev.c +++ b/drivers/staging/media/imx/imx8-media-dev.c @@ -35,8 +35,8 @@ #define ISI_OF_NODE_NAME "isi" #define MIPI_CSI2_OF_NODE_NAME "csi" -#define MXC_MAX_SENSORS 3 -#define MXC_MIPI_CSI2_MAX_DEVS 2 +#define MXC_MAX_SENSORS 4 +#define MXC_MIPI_CSI2_MAX_DEVS 4 #define MXC_NAME_LENS 32 @@ -515,7 +517,11 @@ static int mxc_md_create_links(struct mxc_md *mxc_md) "created link [%s] => [%s]\n", source->name, sink->name); } else if (mxc_md->mipi_csi2[sensor->id].sd) { - mipi_csi2 = &mxc_md->mipi_csi2[sensor->id]; + if(mxc_md->mipi_csi2[i].sd == 0) + mipi_csi2 = &mxc_md->mipi_csi2[1]; + else + mipi_csi2 = &mxc_md->mipi_csi2[0]; + v4l2_info(&mxc_md->v4l2_dev, "sensor->id is (%d)\n", sensor->id); source = &sensor->sd->entity; sink = find_entity_by_name(mxc_md, mipi_csi2->sd_name); @@ -523,7 +529,12 @@ static int mxc_md_create_links(struct mxc_md *mxc_md) sink_pad = source_pad; mipi_vc = (mipi_csi2->vchannel) ? 4 : 1; + v4l2_info(&mxc_md->v4l2_dev, "mipi_vc is (%d)\n", mipi_vc); for (j = 0; j < mipi_vc; j++) { + v4l2_info(&mxc_md->v4l2_dev, "j is (%d), sink pad is (%d), source_pad is (%d)\n", j, sink_pad, source_pad); + if(sensor->id == 1) + sink_pad++; + ret = media_create_pad_link(source, source_pad + j, sink, @@ -958,8 +969,8 @@ static int mxc_md_register_platform_entities(struct mxc_md *mxc_md, static int register_sensor_entities(struct mxc_md *mxc_md) { struct device_node *parent = mxc_md->pdev->dev.of_node; - struct device_node *node, *ep, *rem; - struct v4l2_fwnode_endpoint endpoint; + struct device_node *node, *ep, *ep1, *rem, *rem1; + struct v4l2_fwnode_endpoint endpoint, endpoint1; struct i2c_client *client; struct v4l2_async_subdev *asd; int index = 0; @@ -967,9 +978,12 @@ static int register_sensor_entities(struct mxc_md *mxc_md) mxc_md->num_sensors = 0; + v4l2_info(&mxc_md->v4l2_dev, "port full name is %s\n", mxc_md->pdev->dev.of_node->name); + /* Attach sensors linked to MIPI CSI2 / paralle csi / HDMI Rx */ for_each_available_child_of_node(parent, node) { struct device_node *port; + struct device_node *port1; if (!of_node_cmp(node->name, HDMI_RX_OF_NODE_NAME)) { mxc_md->sensor[index].fwnode = of_fwnode_handle(node); @@ -990,16 +1004,25 @@ static int register_sensor_entities(struct mxc_md *mxc_md) continue; /* csi2 node have only port */ - port = of_get_next_child(node, NULL); + //port = of_get_next_child(node, NULL); + port1 = of_get_next_child(node, NULL); + port = of_get_next_child(node, port1); + v4l2_info(&mxc_md->v4l2_dev, "port full name is %s\n", port->full_name); + v4l2_info(&mxc_md->v4l2_dev, "port name is %s\n", port->name); if (!port) continue; /* port can have only endpoint */ ep = of_get_next_child(port, NULL); + ep1 = of_get_next_child(port1, NULL); + v4l2_info(&mxc_md->v4l2_dev, "ep full name is %s and ep name is %s\n", ep->full_name, ep->name); + if (!ep) return -EINVAL; memset(&endpoint, 0, sizeof(endpoint)); + memset(&endpoint1, 0, sizeof(endpoint1)); + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep1), &endpoint1); ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &endpoint); if (WARN_ON(endpoint.base.port >= MXC_MAX_SENSORS || ret)) { v4l2_err(&mxc_md->v4l2_dev, @@ -1007,14 +1030,21 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return -EINVAL; } + if (endpoint1.base.port ==2) + endpoint1.base.port=1; mxc_md->sensor[index].id = endpoint.base.port; + mxc_md->sensor[index+1].id = endpoint1.base.port; if (!of_node_cmp(node->name, MIPI_CSI2_OF_NODE_NAME)) mxc_md->sensor[index].mipi_mode = true; /* remote port---sensor node */ + rem1 = of_graph_get_remote_port_parent(ep1); rem = of_graph_get_remote_port_parent(ep); of_node_put(ep); + of_node_put(ep1); if (!rem) { v4l2_info(&mxc_md->v4l2_dev, "Remote device at %s not found\n", @@ -1025,6 +1055,7 @@ static int register_sensor_entities(struct mxc_md *mxc_md) /* * Need to wait sensor driver probed for the first time */ + client = of_find_i2c_device_by_node(rem1); client = of_find_i2c_device_by_node(rem); if (!client) { v4l2_info(&mxc_md->v4l2_dev, @@ -1033,7 +1064,12 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return -EPROBE_DEFER; } + mxc_md->sensor[index+1].fwnode = of_fwnode_handle(rem1); mxc_md->sensor[index].fwnode = of_fwnode_handle(rem); + asd = v4l2_async_notifier_add_fwnode_subdev( + &mxc_md->subdev_notifier, + mxc_md->sensor[index+1].fwnode, + struct v4l2_async_subdev); asd = v4l2_async_notifier_add_fwnode_subdev( &mxc_md->subdev_notifier, mxc_md->sensor[index].fwnode, @@ -1043,9 +1079,9 @@ static int register_sensor_entities(struct mxc_md *mxc_md) return PTR_ERR(asd); } - mxc_md->num_sensors++; + mxc_md->num_sensors += 2; - index++; + index += 2; } return 0; diff --git a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c index 1d1236552..d2ba5c890 100644 --- a/drivers/staging/media/imx/imx8-mipi-csi2-sam.c +++ b/drivers/staging/media/imx/imx8-mipi-csi2-sam.c @@ -46,7 +46,7 @@ #define CSIS_DRIVER_NAME "mxc-mipi-csi2-sam" #define CSIS_SUBDEV_NAME "mxc-mipi-csi2" -#define CSIS_MAX_ENTITIES 2 +#define CSIS_MAX_ENTITIES 4 #define CSIS0_MAX_LANES 4 #define CSIS1_MAX_LANES 2 @@ -1486,6 +1486,7 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, struct csi_state *state) { struct device_node *node = pdev->dev.of_node; + struct device_node *node1; state->index = of_alias_get_id(node, "csi"); @@ -1495,7 +1496,9 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, if (of_property_read_u32(node, "bus-width", &state->max_num_lanes)) return -EINVAL; - node = of_graph_get_next_endpoint(node, NULL); + //node = of_graph_get_next_endpoint(node, NULL); + node1 = of_graph_get_next_endpoint(node, NULL); + node = of_graph_get_next_endpoint(node, node1); if (!node) { dev_err(&pdev->dev, "No port node\n"); return -EINVAL; its very messy way to do such thing but for now, it works without an issue.  The above code basically parses device tree and connects two cameras into csi2.0 and other two to csi2.1. And since we have isi subdevices you can get a stream from all 4 of them. Hopefully this will help someone in future.   Re: İ.MX8 Dual Camera Under Single MIPI CSI Hello @B target=_blankio_TICFSL, I check out the latest BSP, if I understood it correctly, the approach is basically didn't changed. I can get some output from video3 and video4, which is both connected to csi2.0. [ 14.313983] mx8-img-md: num_sensors is (4) [ 14.318097] mx8-img-md: sensor is (as0149 2-005f), sd (69904512) [ 14.324920] mx8-img-md: sensor->id is (0) [ 14.328947] mx8-img-md: mipi_vc is (1) [ 14.332708] mx8-img-md: j is (0) [ 14.335973] mx8-img-md: created link [as0149 2-005f] => [mxc-mipi-csi2.0] [ 14.343561] mx8-img-md: sensor is (as0149 2-005e), sd (70127744) [ 14.350392] mx8-img-md: sensor->id is (1) [ 14.354419] mx8-img-md: mipi_vc is (1) [ 14.358179] mx8-img-md: j is (0) [ 14.361413] mx8-img-md: created link [as0149 2-005e] => [mxc-mipi-csi2.0] [ 14.369019] mx8-img-md: sensor is ((efault)), sd (0) [ 14.374009] mx8-img-md: sensor is ((efault)), sd (0) [ 14.378987] mxc-md bus@58000000:camera: mxc_md_create_links but the output is green, and at the top of the screen there are statics. Like below: How can I possibly solve this ? Also from media-ctl -p -d 1: - entity 85: mxc-mipi-csi2.0 (8 pads, 4 links) type Node subtype V4L flags 0 device node name /dev/v4l-subdev0 pad0: Sink <- "as0149 2-005f":0 [ENABLED,IMMUTABLE] <- "as0149 2-005e":0 [ENABLED,IMMUTABLE] pad1: Sink pad2: Sink pad3: Sink pad4: Source -> "mxc_isi.0":0 [ENABLED] pad5: Source -> "mxc_isi.1":1 [ENABLED] pad6: Source pad7: Source I see both of my cameras connected to port0, which basically means when I try to stream from video3 or video4 both of my cameras tries to go into stream. May be this is the problem why I'm getting the green screen output from the MIPI CSI ? I appreciate any help I can get on this.  Thanks. Re: İ.MX8 Dual Camera Under Single MIPI CSI Hi, My kernel version is 5.15.71_2.2.0, the one you linked is Linux 6.6.36_2.1.0. Is it possible to compare the changes and apply it on my own and work it that way ? Thanks. Re: İ.MX8 Dual Camera Under Single MIPI CSI Hi, https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX Regards Re: İ.MX8 Dual Camera Under Single MIPI CSI Hello Bio_TICFSL, Yes I connect my camera into mipi_csi_1. Where can I find the `latest BSP` ?  thanks Re: İ.MX8 Dual Camera Under Single MIPI CSI Hello, Have you connected the MIPI port? since it looks like you are not attached nothing on it, please try the latest BSP it include support for dual camera, but check your hardware camera firts. Regards
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Drive Strength Enable DSE vs DSE1 in MCX A Hello, I have some doubts about drive strength configuration in MCX A micros: What is the difference between DSE and DSE1 in PCRn register? Where is it DSE1 integrated in the I/O pin diagram structure drawing? I’m not able to clearly understand the difference… Thanks! MCXA Re: Drive Strength Enable DSE vs DSE1 in MCX A I'm glad I could help you. Any new issues, welcome to create the new thread. Re: Drive Strength Enable DSE vs DSE1 in MCX A Thanks Celeste! Re: Drive Strength Enable DSE vs DSE1 in MCX A Hello @JosG , Thanks for contacting NXP Tech Support. For more information about DSE, you can find it in the Data Sheet. It is mentioned that "PE, PS, SRE, ODE and DSE are supported in the Pin Control register of all types of IO. 5VTol and HD pads support two DSE bits in the Pin Control register of the pin." In the PCRn register, DSE and DSE1 are the names of these two bits. Not all PCRn registers have two DSE bits; some only have one. The details can be found in the Reference Manual. Based on this, the I/O pin diagram structure is easy to understand. The DSE indicated on it includes both DSE and DSE1. You can also find some useful information in the Data Sheet. For example, as mentioned on page 23, as shown in the following figure: For a detailed introduction to PCRn[DSE], you can refer to the figure below. I hope the above information is useful to you. Best Regards, Celeste
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CAN Bus messages missing during Flash write operation Hi, I have a bare metal OS system working for a while. I noticed recently that sometimes canbus messages are lost when I run a FLASH Write operation. It happens only in case of high traffic.  - Canbus communication is configured as non-blocking. - I don't detect MCAN Errors. I check in callback function for : kStatus_MCAN_RxFifo0Full & kStatus_MCAN_RxFifo0Lost I checked for non blocking flash but no such function exists. Apparently there is no interruption associated to flash operations, meaning that I cannot prioritize can over flash operations. Any ideas or suggestions? Currently my only solution would be to make sure that I write to Flash when there is not a lot of canbus traffic. LPC55xx Re: CAN Bus messages missing during Flash write operation Hi Xiangjun, we're now considering to port the code to SRAM in order to try one of the solutions that you suggested. That way we could still be able to use interruptions during the flashing of the data. Would you please answer a couple of questions? - As I understand I need to copy to ram the interruptions table, the interruption function with ALL the dependencies, functions and code used in the interruption function. Can you confirm this? - The APIs for flashing the memory are blocking, so during the flashing only the interruption functions will be executed. Is it so? Thank you! Re: CAN Bus messages missing during Flash write operation Hello Xiangjun, your explanation makes all the sense. Thank you very much. Probably the easiest is to avoid using interruptions with canbus as I understand that the function MCAN_TransferReceiveBlocking allows.  Re: CAN Bus messages missing during Flash write operation Hi, I suppose that you use LPC55xx family, which has only one flash block, if you erase/program sector or page of the same block where you save code and execute, you will have issue. while the flash block is erased/programed by calling IAP function, you can not access the block, so you have to disable interrupt, but you use CAN non-blocking mechanism, which uses interrupt mechanism, it will leads to error. If you want to erase/program flash and hope you can use interrupt mechanism, you have to copy the interrupt table to SRAM and copy the ISR to SRAM from flash, because core fetches interrupt table from RAM and execute code from RAM, it is okay, although you erase/program flash page or sector Hope it can help you BR Xiangjun Rong
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ReadObject 无法在无会话访问 PnT nano 中读取二进制文件 如何允许我的 ReadObject 命令在无会话访问时输出二进制文件?我在检查内容时只收到 0,而不是实际内容。也许我在编写二进制文件时必须设置不同的策略?我以为默认策略允许所有访问。 SE050 回复:ReadObject 无法在无会话访问 PnT nano 中读取二进制文件 非常感谢 Kan 的回答! 有没有一个例子说明如何使用没有 SSS API 的 nano mw 来执行此操作? 最好的祝愿 扬施
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DPMAC Issue on LX2160A with 16 SFP Ethernet Ports Dear NXP Team, We are experiencing an issue when trying to use all 16 DPMACs (DPMAC3-18) simultaneously in Linux on our custom board: Details: CPU: LX2160A Board: Custom board with 16 1000BaseX SFP Ethernet ports (DPMAC3-18) SerDes1 Protocol: 4 (8x 1G Ethernet) SerDes2 Protocol: 9 (8x 1G Ethernet) SerDes3 Protocol: 3 (2x PCIe) Software: Bootloaders and Linux firmware are based on "LSDK-21.08" branches MC Firmware: v10.39.0 One of the ports (DPMAC18) is not working correctly: ingress and egress data are not flowing, and both RX/TX "frame discards" MIB counters are increasing. Here are the relevant NIC statistics from ethtool: # ethtool -S eth1 | grep -v ": 0" NIC statistics: [hw] tx discarded frames: 34 [hw] tx confirmed frames: 34 [hw] tx dequeued bytes: 1804 [hw] tx dequeued frames: 34 [drv] tx conf frames: 34 [drv] tx conf bytes: 1804 [drv] tx sg frames: 34 [drv] tx sg bytes: 1804 [drv] tx converted sg frames: 34 [drv] tx converted sg bytes: 1804 [drv] cdan: 34 [qbman] buffer count: 10248 [mac] rx 64 bytes: 33 [mac] rx frame discards: 2 [mac] rx bytes: 1984 [mac] rx b-cast: 31 [mac] rx all frames: 33 [mac] rx frames ok: 31 There are no errors in dmesg or the MC log (/dev/dpaa2_mc_console), but we do observe the following warnings in the MC log: [W, PLATFORM] UART print failed, all debug data will be printed to buffer. Running MC app, waiting for events ... [W] [PFS ] val=0x0000002f got=0x00000001 Port FIFO size not configured, please reduce FIFO allocated on recycle ports [W] [PFS ] val=0x0000002f got=0x00000001 Port FIFO size not configured, please reduce FIFO allocated on recycle ports We have followed the "Network Subsystem Troubleshooting on DPAA2" guide from this document, and tried the following steps: 1) We checked all 16 ports in u-boot, and they are working properly: u-boot> setenv ethact DPMAC3@sgmii ; ping 10.0.0.2 Using DPMAC3@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC4@sgmii ; ping 10.0.0.2 Using DPMAC4@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC5@sgmii ; ping 10.0.0.2 Using DPMAC5@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC6@sgmii ; ping 10.0.0.2 Using DPMAC6@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC7@sgmii ; ping 10.0.0.2 Using DPMAC7@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC8@sgmii ; ping 10.0.0.2 Using DPMAC8@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC9@sgmii ; ping 10.0.0.2 Using DPMAC9@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC10@sgmii ; ping 10.0.0.2 Using DPMAC10@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC11@sgmii ; ping 10.0.0.2 Using DPMAC11@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC12@sgmii ; ping 10.0.0.2 Using DPMAC12@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC13@sgmii ; ping 10.0.0.2 Using DPMAC13@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC14@sgmii ; ping 10.0.0.2 Using DPMAC14@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC15@sgmii ; ping 10.0.0.2 Using DPMAC15@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC16@sgmii ; ping 10.0.0.2 Using DPMAC16@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC17@sgmii ; ping 10.0.0.2 Using DPMAC17@sgmii device host 10.0.0.2 is alive u-boot> setenv ethact DPMAC18@sgmii ; ping 10.0.0.2 Using DPMAC18@sgmii device host 10.0.0.2 is alive 2) We tried to start Linux firmware with minimal DPL configuration (that contains only 40 DPMCPs) and configure DPL in run-time with "restool" and "ls-addni" utilities, the result is still the same, one port is not working properly, though we found out that the problem is not related to one specific port: port with DPMAC that was initialized last with restool dpmac create --mac-id=X is the one that is not working. For example: if we initialize DPMAC3 last, a port with this DPMAC will not work, and a port with DPMAC18 will work without any problems. We also found out that two warnings in the MC log appear only after 16-th DPMAC is initialized: MC log after booting with minimal DPL configuration: [W, PLATFORM] UART print failed, all debug data will be printed to buffer. Running MC app, waiting for events ... MC log after 15 ports (DPMAC3-17) were configured with commands ex restool dpmac create --mac-id=X, ex restool dprc assign dprc.1 --object=dpmac.X --plugged=1, ex ls-addni -nq=8 -t=1 dpmac.X: [W, PLATFORM] UART print failed, all debug data will be printed to buffer. Running MC app, waiting for events ...​ MC log after 16-th port is configured with same commands: root@TinyLinux:~# cat /dev/dpaa2_mc_console [W, PLATFORM] UART print failed, all debug data will be printed to buffer. Running MC app, waiting for events ... root@TinyLinux:~# restool dpmac create --mac-id=18 root@TinyLinux:~# restool dprc assign dprc.1 --object=dpmac.18 --plugged=1 root@TinyLinux:~# root@TinyLinux:~# root@TinyLinux:~# ls-addni -nq=8 -t=1 dpmac.18 root@TinyLinux:~# cat /dev/dpaa2_mc_console [W, PLATFORM] UART print failed, all debug data will be printed to buffer. Running MC app, waiting for events ... [W] [PFS ] val=0x0000002f got=0x00000001 Port FIFO size not configured, please reduce FIFO allocated on recycle ports [W] [PFS ] val=0x0000002f got=0x00000001 Port FIFO size not configured, please reduce FIFO allocated on recycle ports​ 3) We checked out the logs from ifconfig, restool dpni, restool dpmac commands about non-working port as guide suggested: root@TinyLinux:~# sudo ping 10.0.0.2 -I eth1 -c 5 PING 10.0.0.2 (10.0.0.2): 56 data bytes --- 10.0.0.2 ping statistics --- 5 packets transmitted, 0 packets received, 100% packet loss root@TinyLinux:~# ifconfig eth1 eth1: flags=4163 mtu 1500 ether ae:27:42:ac:48:16 txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 14 bytes 908 (908.0 B) TX errors 14 dropped 0 overruns 0 carrier 0 collisions 0 root@TinyLinux:~# restool dpmac info dpmac.18 dpmac version: 4.10 dpmac object id/portal id: 18 plugged state: plugged endpoint state: 1 endpoint: dpni.0, link is up DPMAC link type: DPMAC_LINK_TYPE_BACKPLANE DPMAC ethernet interface: DPMAC_ETH_IF_SGMII MAC address: ae:27:42:ac:48:16 maximum supported rate 1000 Mbps Counters: rx all frames: 2 rx frames ok: 2 rx frame errors: 0 rx frame discards: 0 rx u-cast: 0 rx b-cast: 2 rx m-cast: 0 rx 64 bytes: 0 rx 65-127 bytes: 0 rx 128-255 bytes: 1 rx 256-511 bytes: 1 rx 512-1023 bytes: 0 rx 1024-1518 bytes: 0 rx 1519-max bytes: 0 rx frags: 0 rx jabber: 0 rx align errors: 0 rx oversized: 0 rx pause: 0 rx bytes: 531 tx frames ok: 0 tx u-cast: 0 tx m-cast: 0 tx b-cast: 0 tx frame errors: 0 tx undersized: 0 tx b-pause: 0 tx bytes: 0 root@TinyLinux:~# restool dpni info dpni.0 dpni version: 8.5 dpni id: 0 plugged state: plugged endpoint state: 1 endpoint: dpmac.18, link is up link status: 1 - up mac address: ae:27:42:ac:48:16 max frame length: 10240 dpni_attr.options value is: 0 num_queues: 8 num_cgs: 1 num_rx_tcs: 1 num_tx_tcs: 1 mac_entries: 16 vlan_entries: 0 qos_entries: 0 fs_entries: 64 qos_key_size: 0 fs_key_size: 56 ingress_all_frames: 0 ingress_all_bytes: 0 ingress_multicast_frames: 0 ingress_multicast_bytes: 0 ingress_broadcast_frames: 0 ingress_broadcast_bytes: 0 egress_all_frames: 0 egress_all_bytes: 0 egress_multicast_frames: 0 egress_multicast_bytes: 0 egress_broadcast_frames: 0 egress_broadcast_bytes: 0 ingress_filtered_frames: 0 ingress_discarded_frames: 0 ingress_nobuffer_discards: 0 egress_discarded_frames: 14 egress_confirmed_frames: 14 ceetm_dequeue_bytes: 908 ceetm_dequeue_frames: 14 ceetm_reject_bytes: 0 ceetm_reject_frames: 0 cgr_reject_frames: 0 cgr_reject_bytes: 0 policer_cnt_red: 0 policer_cnt_yellow: 0 policer_cnt_green: 0 policer_cnt_re_red: 0 policer_cnt_re_yellow: 0 tx_pending_frames_cnt: 0 We have attached a detailed MC log (captured using ls-debug --log=on --console=on --level=2) for your review. Could you please assist us in identifying and resolving the issue? Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports dear o_m_v in order to have a better grasp about the FIFO size and frames please review the Chapter 3, “Frame Descriptor and Frame Description.” also please review the Table 7-5. Frame Descriptor Fields. you can review the DPAA driver to understood the FIFO allocation https://github.com/nxp-imx/linux-imx/tree/29549c7073bf72cfb2c4614d37de45ec36b60475/drivers/net/ethernet/freescale/dpaa2 Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports Thank you for your previous response regarding our FIFO calculations. We have reviewed the section "7.6 WRIOP Ports" in the LX2160ADPAA2RM document, as advised. However, we are still unclear on a few points. Could you please elaborate on what specific aspects we should consider from this section regarding our egress FIFO calculations? Specifically, we would like to understand how the WRIOP port configuration and frame descriptors affect the available FIFO memory for Ethernet ports (PPID 1-18). We would appreciate any additional details or examples to clarify how FIFO allocation differs between CTLU and WRIOP, or any adjustments we should make based on WRIOP's requirements. Thank you for your assistance. Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports dear o_m_v, the FIFO size you related is for the CTLU ""Classifier and Table Lookup Unit"". please review, in the LX2160ADPAA2RM, the "7.6 WRIOP Ports" subject and the related to frame descriptors. Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports We have reviewed the LX2160ADPAA2RM.pdf document and identified 264 KB (0x42000 bytes) available for ingress FIFO, as well as 264 KB available for egress FIFO. Additionally, we noted the existence of two internal "recycle" ports (PPID 19-20) and an additional internal 1G "management command" port (PPID 0). Our egress calculations are as follows: Starting with 0x42000 bytes for egress FIFO: PPID 0 ("management command" port) will require: 0x100 * (0x2F + 0x1) = 0x3000 bytes. PPID 19-20 ("recycle" ports) will require: 1G: 2 * 0x100 * (0x2F + 0x1) = 0x6000 bytes; 10G: 2 * 0x100 * (0x3F + 0x1) = 0x8000 bytes; 50G: 2 * 0x100 * (0x7F + 0x1) = 0x10000 bytes. Thus, the remaining egress FIFO available for normal Ethernet ports (PPID 1-18) would be: 1G recycle: 0x42000 - 0x3000 - 0x6000 = 0x39000 bytes; 10G recycle: 0x42000 - 0x3000 - 0x8000 = 0x37000 bytes; 50G recycle: 0x42000 - 0x3000 - 0x10000 = 0x2F000 bytes. Could you please confirm that our FIFO calculations are correct? Thank you for your assistance. Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports you can find it at the LX2160ADPAA2 reference manual, use the below link and go ahead to the "Documentation" section. https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports Thank you for sharing the application note to help resolve the issue. In the document, it states: "The total sum of ports' FIFOs must not exceed the total FIFO size available. The FIFO size is device specific. Check Device specific features." Could you please clarify where we can find the Total FIFO size information specifically for our LX2160A processor? Thank you! Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports dear @o_m_v , please use the next application note to resolve the issue  https://www.nxp.com/docs/en/application-note/AN13684.pdf  Re: DPMAC Issue on LX2160A with 16 SFP Ethernet Ports I need more info from your side in order to investigate the issue, please review my message on your email
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Increasing flash size I'm using a RT1176 in a custom board with SDRAM and a IS25WP128-JBLE QSPI external flash. We are doing a HMI, and the flash size is getting small for including images in flash, so we changed the flash to IS25WP256D-JLLE. When the code is less than 50% of the flash size, all is working fine, but when we start using the "new sectors" we get a hard fault in data_init. I changed the board flash size in board.h and a line in board.c #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); // MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); #endif /*! @brief The board flash size */ #define BOARD_FLASH_SIZE (0x2000000U) Also changed the size in MCU settings: Maybe the cfx driver is not valid? I need to do more steps? Thank you very much Re: Increasing flash size It's working now. I had to change the lookupTable at evkmimxrt1170_flexspi_nor_config.c, using the commands given in the new memory datasheet. Thank you! Re: Increasing flash size Hello EdwinHz, I tried the example code, and changing the flash size it seems to work in the upper part of the FLASH: I changed lookupTable in evkmimxrt1170_flexspi_nor_config.c with the customLUT provided, but it's not working yet. Maybe it's important to remark that my program is working fine until the mid region of the flash. When the % used of the memory surpases the 50%, it fails. I was thinking about the instructions for managing 4-byte address, but it's not included in customLUT, and the example seems to work without that: Re: Increasing flash size Hi @daniJVV, Please follow the recommendations mentioned by my colleague in the following community post: Re: iMX RT1062 with IS25WP365D-JLLE issue - NXP Community He mentions some remarks that are worth taking into account. Also, try the example code that he mentions and let me know what are the results as well. BR, Edwin.
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x86_64 driver for iw611 Hello, I got a eval kit with a 2DL module from murata using the iw611 chip laying around and I would like to test it out using my laptop. I read UM11675 and it dosnt say anything about a driver for non ARM. Is there none available? When I did a quick search it looked like it had been at some point (e.g. https://community.nxp.com/t5/Wireless-Connectivity-Knowledge/How-to-compile-IW416-linux-driver-for-x86-amp-ubuntu-16-04/ta-p/1282541) best regards Re: x86_64 driver for iw611 Hello, perfect I will try that! Thanks. Re: x86_64 driver for iw611 Hi, @malj  Thanks for creating case to us. Are you using Ubuntu PC based on Linux? I think for X86 platform, you can directly compile our Wi-Fi driver with below command: make KERNELDIR="Your kernel location" build And for your information, usually on Ubuntu, the default Linux kernel directory is below: /usr/src/linux-headers-xxxx I give you an example of compile command as below: make KERNELDIR=/usr/src/linux-headers-5.4.0-192-generic build Please do not forget to modify the ARCH from arm64 to x86 in Makefile before build the Wi-Fi source code. You can try on your side, and let me know whether is successful on your side. If there are any errors or still need our help, please do not hesitate to let me know. Best regards, Christine.
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ReadObject はセッションレス アクセス PnT nano でバイナリ ファイルを読み取れません セッションレスアクセス中にReadObjectコマンドがバイナリファイルを出力できるようにするにはどうすればよいですか?実際のコンテンツではなく、コンテンツを確認するときに0を受け取るだけです。たぶん、バイナリファイルを書き込むときにポリシーを異なる方法で設定する必要がありますか?デフォルトのポリシーですべてのアクセスが有効になると思いました。 SE050 Re:ReadObjectは、セッションレスアクセスPnT nanoでバイナリファイルを読み取ることができません カンさん、ご回答いただき、誠にありがとうございます! SSS APIがないnano mwでもこれを行う方法の例はありますか? 頑張ってください ヤンシュ
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The S32DS license for ARM 2018R1 is expiring soon Hello, my license of S32 Design Studio for ARM Version 2018.R1 expiration soon Could you please extend it ? Thanks.  My activation Code: 0D34-286B-9EE6-E692 Thanks a lot Re: The S32DS license for ARM 2018R1 is expiring soon It's ok, thank you very much Re: The S32DS license for ARM 2018R1 is expiring soon Hi,  your S32DS License has been extended. Please activate S32DS again with your old code. 
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S32DS S32K1xx_flash.ld Startup_code. s I am using the S32DS S32K144 chip and I would like to use my own S32K1xx_flash.ld file and Startup_code. s file instead of being automatically generated by the system. Every time I clean up the project, these files will be deleted, which is inconvenient. Is there any way to do this. Yesterday I found out that the ld file seems to have been modified here, but Startup.Code. s still doesn't know what to do Re: S32DS S32K1xx_flash.ld Startup_code. s Hi,  sorry for delay. Clean the project don't delete any source code. Source code can be replaced for example if you generate code for SDK.  You can add your own startup code into src folder and exclude Project_Settings/Startup folder from build:  Re: S32DS S32K1xx_flash.ld Startup_code. s Hi,  sorry for delay. Clean the project don't delete any source code. Source code can be replaced for example if you generate code for SDK.  You can add your own startup code into src folder and exclude Project_Settings/Startup folder from build: 
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