S32K comparator tolerance/offset we are having some test on the comparator of S32K116: we apply an input voltage(238mV) to INN (or INP), use bandgap as reference, then we increase VOSEL from 0 to 255 and monitor when the comparator output changed. Somehow, we see different tolerance/offset on MCU2 when the connection of input voltage and bandgap is swapped. (Details shown in Test1 and Test2) 1) Is this some kind of known feature like VAIO or something else? 2) For this tolerance/offset, is it stable and can we eliminate this by calibration? (like record the trigger VOSEL at the target voltage) Test1: Input Voltage on V-, Bandgap on V+, Low Speed Mode Test2: Input Voltage on V+, Bandgap on V-, Low Speed Mode Re: S32K comparator tolerance/offset 1) Input Pin CMP0_IN is always set to channel 0. (PIN26, PTA0) Yes, input voltage still being input through the same CMP0_IN Pin26, PTA0. 2) Bandgap The feature I want to figure out is not the difference between two MCU. It is this different tolerance/offset from the same MCU when INN and INP is swapped. I think the bandgap should not change during this swapped. (The data of MCU1 here is just use as reference) 3) VDD/VDDA: The two MCU are using same +3.3V network (LDO within 1.25% tolerance). I am fully understanding there will be difference between MCUs bandgap, but, again, it is the difference during swapped I am checking. 4) test method The test data above is not increasing input voltage, it is using fixed input voltage, and increasing VOSEL. (For decreasing VOSEL, i have not test yet, will check this later.) As for increasing/decreasing input voltage with fixed VOSEL, there is similar -9mV. 5) Hysteresis I do have test data for hysteresis in low-speed mode: Test data here is fixing input voltage and increase VOSEL: 6) MCU photos you can refer to attached photo "MCU1.PNG" and "MCU2.PNG" Solder mask is FS32K11-6LFMFM-ON96V-S12YM16 Re: S32K comparator tolerance/offset Hi Sid_Zhou,
Which CMP0_IN pin are you connecting the input voltage to?
When swapping INN and INP, is the input voltage still being input through the same CMP0_IN pin?
Also, the BandGap voltage range is between 0.97-1.03V. Have you considered temporarily ruling out issues caused by different BandGap voltages on the two MCUs? For example, could you use a different CMP0_IN pin to input a more accurate external voltage reference?
Have you checked whether the VDD/VDDA voltages of the two S32K1s are the same?
Were OFFSET=1 and HYSTCTR=0 confirmed during debugging?
I noticed you increased the input voltage and recorded VOSEL. Have you tested decreasing the input voltage and recording VOSEL? Also, check if the Analog comparator hysteresis is affected, although I see you configured HYSTCTR=0.
Take two S32K116 photos and tell me the MCU mask.
Best Regards, Robin
Re: S32K comparator tolerance/offset Thank you for your detailed explanation. I now understand that you are concerned about the VAIO (Analog Input Offset Voltage) parameter in the S32K1 Datasheet.
Internally, I saw the AE team's explanation: The AIO offset is the offset of the comparator itself. the offset between INP and INN. The INL error includes the DNL error since it is an integral over the DNL. The error is then |V_AIO| + |INL|
Based on my understanding, directly using two analog voltages from an external signal source to input INP and INN respectively to test VAIO should be more intuitive than using bandgap voltage divider.
Regarding your question: for the same MCU, VAIO is not a random value that changes arbitrarily from moment to moment , but it can drift with operating conditions, especially temperature. The VAIO value in the datasheet should be understood as a guaranteed/worst-case limit over the full temperature range. When designing the threshold, do not treat VAIO as negligible or as a fixed calibrated-out value . Keep margin based on the full-temperature worst-case |VAIO| , plus the DAC/INL error.
I also checked your previous discussion on this: S32K116 comparator tolerance. It seems that CMP's accuracy doesn't meet your needs. Have you considered the feature described in section "44.5.5 Automatic compare function" of S32K1XXRM Rev14.2? "Table 41. 12-bit ADC characteristics (2.7 V to 3 V)" in S32K1 DataSheet Rev15 shows a maximum TUE of ±8 LSB. This appears to be more accurate than CMP. Re: S32K comparator tolerance/offset Thanks for your detailed explanation. I noted that the ADC may have better accuracy in our application. But somehow, we have requirements for using CMP as safety monitor from high level architecture and i am not sure if this can be changed to ADC.
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