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meter 我想在组件里面找到meter控件,怎么没有啊
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S32K328 HSE-B: Recommended Architecture for A/B Swap using Mem_43_INFLS (without Vector FOTA) Hello NXP Team, We are currently in the design and implementation phase of adding OTA A/B swap support to an existing application running on S32K328. This is an initial implementation where we are extending the existing software with OTA capability rather than integrating a complete FOTA framework. Current Environment MCU: S32K328 (8 MB P-Flash) AUTOSAR Stack: Vector MICROSAR RTD: S32K3_RTD_6_0_0_QLP04_D2508_ASR_REL_4_7_REV_0000_20250822 Binary transfer interface: UART Image activation service: HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK HSE A/B swap is enabled via RTD configuration The OTA binary is received over UART by a custom OTA CDD. Our current Vector configuration contains MemAccM only for NvM/Fee (D-Flash). There is no MemAccM configuration for programming the application P-Flash, and we are not using Vector OTA/FOTA. Therefore, we are considering using Mem_43_INFLS from the OTA CDD to erase and program the inactive application flash directly. We would appreciate guidance on the following points. 1. Recommended approach Is Mem_43_INFLS the recommended low-level driver for managing OTA image programming in an A/B swap setup when not using Vector’s OTA/FOTA package? Or should MemAccM be extended to cover P‑Flash programming even for custom OTA implementations? 2. Inactive flash block addressing After enabling HSE A/B swap: Is the inactive application P‑Flash block always accessed via fixed physical addresses defined in the memory layout? Or does HSE provide any logical mapping or abstraction for the passive block? 3. Preconditions for activation What are the mandatory preconditions for successful execution of HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK? For example: Image header format Metadata requirements Alignment constraints Authentication / signature requirements Flash state or attributes 4. Flash controller concurrency Does the C40 flash controller on S32K328 support concurrent operations between D‑Flash (Fee/NvM) and P‑Flash (inactive block)? If not, what is the recommended synchronization strategy: Application-level scheduling RTD driver arbitration MemAccM usage 5. Recommended architecture Is the following architecture aligned with NXP recommendations? UART ↓ Custom OTA CDD ↓ Mem_43_INFLS (erase/write inactive P‑Flash) ↓ Image verification ↓ HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK ↓ System reset ↓ HSE/BAF activates the passive block We are specifically looking for guidance on whether this lightweight approach is appropriate and compliant with HSE requirements. If there are any application notes, RTD examples, or reference implementations for custom OTA with HSE A/B swap, we would greatly appreciate your guidance. Thank you for your support. Best regards, Venkatesh KV #s32k328 Re: S32K328 HSE-B: Recommended Architecture for A/B Swap using Mem_43_INFLS (without Vector FOTA) Hi @venkatesh-kv  1. A custom OTA implementation can use Mem_43_INFLS directly to erase and program the passive partition. Whether MemAccM should be extended is an architectural decision and mainly depends on whether a common flash access and arbitration layer is desired within the application. 2. The passive application image is normally programmed using its physical P-Flash address range. HSE does not provide a dedicated logical addressing abstraction for the passive block. The application/bootloader is responsible for writing the new image to the inactive partition, after which HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK can be used to make that partition active on the next reset. 3. If secure boot is used, the signatures should be updated accordingly (depending on secure boot mode and other settings), so new application can be successfully authenticated and executed after next reset. Older version of HSE firmware required super user rights to execute service HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK. This has been downgraded to normal user rights in firmware versions 0.2.55.0 and newer. 4. Only one flash operation can run at a time. The implementation of flash access arbitration is left to the application architecture. In general, it is recommended to avoid concurrent flash operations from multiple software components and ensure that flash accesses are properly synchronized to prevent conflicts between OTA programming activities and any other flash users in the system. There’s no synchronization support between Fee/NvM and Mem_43_INFLS. 5. Yes, that’s correct flow. If fact, the only requirement is that there should be valid application in passive partition before the swap and signatures (or secure boot configuration in general) should be updated accordingly. We have basic OTA demo “SW32K3_OTADEMO_0.8.0_D2203” for S32K344 - it shows how to write new application to passive block and then request AB SWAP (this is a feature of HSE firmware). RTD 1.0.0 is used in this demo. Next more advanced demo is “S32K396 OTA Demo version 0.4.0” which shows how to update firmware via ethernet. This one uses RTD 3.0.0 P07. Both demos can be found in S32K3 Reference Software: https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-REFSW-D Click on the link and then search for “Automotive SW - S32K3 - OTA Demo”. These are the only versions we have, it’s only reference software, it’s up to users to migrate it to other derivatives or to newer RTD packages if needed. And we have following OTA trainings: https://www.nxp.com/design/design-center/training/TIP-CONNECTS2021-AUT428 https://www.nxp.com/design/design-center/training/TIP-NXP-AUT-T3955A Both can be found in Training section on S32K3 page: https://www.nxp.com/products/S32K3 Also you can take a look at “S32K3XX HSE and OTA Advance Training [TR744101]” which can be downloaded from Documentation -> Secure files: https://www.nxp.com/products/S32K3 Regards, Lukas
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MEXの設定はWindowsやLinuxとは異なるコードを生成します 同じXEMファイルでも、システムによって生成されるコードが異なる。 Windowsファイルはコード正常生成ですが、Linuxシステムは異常な生成をします 前提条件:RTDおよびSDKバージョンインストールと同じです 5.jpg Re: mex config generate code different from windows and linux こんにちは、 @Littenさん 現在、RTDはWindowsプラットフォームでのみサポートされており、Linuxでは公式にはサポートされていません。たとえLinuxにインストールできても、開発や統合の過程で追加の問題に直面する可能性があります。 主な理由の一つは、Linuxが大文字大文字を区別するオペレーティングシステムであることです。この状況の詳細は スレッド「S32DSのLpi2c_Ip_MasterConfigとLpi2c_Ip_SlaveState構造体生成の問題」で議論されています。S32K344。 BR、VaneB
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KinetisとLPC用のデバッグインターフェースのおすすめはありますか? 私は主にKinetisシリーズで開発をしており、近い将来LPCのパーツもいくつか手がけるかもしれません。P&E Microのデバッグインターフェースが引き出しいっぱいにあり、よく使っているCyclone ACPも含まれています。 時々、600ドルのCycloneから20ドルのLPC-Link2に切り替えることがあります。なぜなら、CycloneはMCUXpressoに多くの奇妙な問題があるからです。正直なところ、LPC-Link2は私の必要な機能のほとんどを満たしてくれるのですが、少し動作が遅いのが難点です。 Seggerインターフェースを検討しるべきでしょうか?MCUXpresso(そしてできればCodeWarrior 11でも)で十分にサポートされ、クラッシュや走行中のターゲットを止められない信頼性が高く、そこそこ高速なインターフェースを誰かおすすめできませんか?トレースサポートがあれば助かります。 よろしくお願いします! Re: Debug interface recommendations for Kinetis and LPC? こんにちは、 @zeref さん。 これは繰り返し投稿です。KinetisとLPCのデバッグインターフェース推奨に関する私の返信を参照してください。 BR セレステ
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请求为 MCXW72 Matter 锁示例提供受控访问的 Aliro 中间件 尊敬的NXP技术支持: 我是鲁汶大学/COSIC应用密码学专业的博士后研究员。我正在进行一项关于 CSA Aliro 1.0 Reader SDK 的学术实施安全性和互操作性研究。 我下载了: MCUXpresso SDK 26.06.00 for MCX-W72-EVK; 相应的 MCUXpresso 配置工具包; mcuxsdk-examples-matter-release-v1.4.2 ; NXP Matter lock-app-aliro 示例。 Matter 示例需要以下受控中间件: > /middleware/aliro/aliro_sdk.cmake 但是,Aliro 中间件并未包含在 MCXW72 SDK Builder 包或 Matter 示例存档中。 能否提供与 MCUXpresso SDK 26.06.00 和 Matter Aliro 锁示例兼容的完整 Aliro 中间件包? 该材料将仅用于经授权的学术分析,并将根据任何适用的许可或保密协议进行处理。 亲切的问候, 萨永·杜塔古普塔 博士后研究员 鲁汶大学 COSIC   安全(Edgelock | 安全启动 | OTP) Re: Request for controlled-access Aliro middleware for MCXW72 Matter lock example 你好@Sayon 希望你一切都好。 非常抱歉,Aliro 解决方案尚未发布,而且很遗憾,中间件也不可用。 对于给您带来的不便,我深表歉意。 问候, 爱德华多。
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Does i.MX6UL provide any mechanism (timer/register) to delay or control ZMK zeroization after tamper Does the i.MX6UL provide any hardware mechanism (register, timer, counter, or configuration) to prevent or postpone automatic ZMK zeroization after a valid external tamper event? If such a mechanism exists, could you please point me to the relevant register(s), timer, or configuration described in the Security Reference Manual? Platform: i.MX6UL  Bootloader: U-Boot 2016.03 OS: Linux + OP-TEE Reference used: Security Reference Manual for the i.MX 6UltraLite Applications Processor, Rev. 0, 04/2016 @nxp 
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i.MX8M Plus DDR4-3200 EVK 设计文件和 DDR4 布局指南 你好 , 我们希望采用 i.MX8M Plus+DDR4 设计我们的产品。 NXP能否向我们提供i.MX8M Plus+DDR4-3200的设计文件(sch和.brd)以及DDR4布局指南文档? Re: i.MX8M Plus DDR4-3200 EVK Design file and DDR4 layout guide 我正在尝试同样的方法。 供参考。基于 i.MX 8M Plus 的 AI 机器人平台 “ I-MX8MPLUS-ALROBOT-FORM”是DDR4参考设计。 您需要联系恩智浦半导体才能获得这些资源。 Re: i.MX8M Plus DDR4-3200 EVK Design file and DDR4 layout guide @seungyeon我已经通过邮件和附件发送给你了,请查收。
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Request for controlled-access Aliro middleware for MCXW72 Matter lock example Dear NXP Support, I am a postdoctoral researcher in applied cryptography at KU Leuven/COSIC. I am conducting an academic implementation-security and interoperability study of CSA Aliro 1.0 Reader SDKs. I downloaded: MCUXpresso SDK 26.06.00 for MCX-W72-EVK; the corresponding MCUXpresso Config Tools package; mcuxsdk-examples-matter-release-v1.4.2; the NXP Matter lock-app-aliro example. The Matter example expects the following controlled middleware: >  /middleware/aliro/aliro_sdk.cmake However, the Aliro middleware is not present in the MCXW72 SDK Builder package or in the Matter example archive. Could you please provide access to the complete Aliro middleware package compatible with MCUXpresso SDK 26.06.00 and the Matter Aliro lock example? The material will be used solely for authorised academic analysis and will be handled according to any applicable licence or NDA. Kind regards, Sayon Duttagupta Postdoctoral Researcher COSIC, KU Leuven   Security(Edgelock | secure boot | OTP) Re: Request for controlled-access Aliro middleware for MCXW72 Matter lock example Hello @Sayon Hope you are doing well. My apologies, Aliro solution has not been released and, unfortunately, middleware is not available. I truly apologize for the inconvenience. Regards, Eduardo.
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メートル 部品の中からメーター制御装置を探しているのですが、見つかりません。
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i.MX6ULは、改ざん後のZMKのゼロ化を遅延または制御するためのメカニズム(タイマー/レジスタ)を提供しますか? i.MX6ULは、有効な外部改ざんイベント後に自動ZMKゼロ化を防止または延期するためのハードウェア機構(レジスタ、タイマー、カウンター、または設定)を提供していますか?もしそのような仕組みが存在するなら、セキュリティリファレンスマニュアルに記載されている該当レジスタ、タイマー、または設定をご紹介いただけますか? プラットフォーム: i.MX6UL  ブートローダー: U-Boot 2016.03 OS: Linux + OP-TEE 参考文献: i.MX 6UltraLiteアプリケーションプロセッサのセキュリティリファレンスマニュアル、Rev. 0、2016年4月 @nxp 
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MCXW72 Matterロックの例として、Aliroミドルウェアの制御アクセスリクエスト NXPサポートの皆様、 私はルーヴェン・カトリック大学/COSICで応用暗号学の博士研究員をしています。私はCSA Aliro 1.0 Reader SDKの学術実装、セキュリティ、相互運用性に関する研究を行っています。 ダウンロードしました: MCUXpresso SDK 26.06.00 for MCX-W72-EVK; 対応するMCUXpresso設定ツールパッケージ、 mcuxsdk-examples-マター-release-v1.4.2; NXPのMatterのlock-app-aliroの例です。 マターの例では、以下の制御ミドルウェアが求められます: > /middleware/aliro/aliro_sdk.cmake しかし、AliroミドルウェアはMCXW72 SDK Builderパッケージやマターの例アーカイブには含まれていません。 MCUXpresso SDK 26.06.00およびMatter Aliroロックの例に対応したAliroミドルウェアパッケージの完全なアクセスを教えていただけますか? 当該資料は、許可された学術分析のみに使用され、適用されるライセンスまたは秘密保持契約に従って取り扱われます。 敬具、 サヨン・ダッタグプタ ポスドク研究員 COSIC、ルーヴェン・カトリック大学   セキュリティ(EdgeLock | セキュアブート | OTP) Re: Request for controlled-access Aliro middleware for MCXW72 Matter lock example こんにちは、 @Sayon さん。 あなたの調子が良いといいのですが。 申し訳ございませんが、Aliroソリューションはまだリリースされておらず、残念ながらミドルウェアもご利用いただけません。 ご迷惑をおかけして誠に申し訳ございません。 よろしくお願いいたします。 エドゥアルド。
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Kinetis 和 LPC 的调试接口有什么建议? 我目前主要从事 Kinetis 系列芯片的开发工作,未来可能还会开发一些 LPC 芯片。我抽屉里装满了 P&E Micro 的调试接口,其中最常用的是 Cyclone ACP。 我有时会发现自己从 600 美元的 Cyclone 换成了 20 美元的 LPC-Link2,因为 Cyclone 与 MCUXpresso 存在很多奇怪的问题。说实话,LPC-Link2 基本能满足我的需求,只是速度有点慢。 我应该考虑使用Segger接口吗?请问有人可以推荐一款可靠、速度适中、在 MCUXpresso(最好也能在 CodeWarrior 11)中支持良好的接口吗?这款接口不会经常导致程序崩溃,也不会无法停止正在运行的目标。如果能支持追踪功能就更好了。 谢谢您! Re: Debug interface recommendations for Kinetis and LPC? 你好@zeref , 这是重复发帖,请参考我在“Kinetis 和 LPC 的调试接口建议?”中的回复。 BR 塞莱斯特
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i.MX8M Plus DDR4-3200 EVK設計ファイルおよびDDR4レイアウトガイド こんにちは 、 私たちはi.MX8M Plus+DDR4で製品を設計したいと考えています。 NXPはi.MX8M Pluse+DDR4-3200およびDDR4レイアウトのデザインファイル(schと.brd)を私たちに提供できますか? Re: i.MX8M Plus DDR4-3200 EVK Design file and DDR4 layout guide 私も同じアプローチで取り組んでいます。 参考までに。i.MX 8M Plusを基盤としたAIロボットプラットフォーム 「I-MX8MPLUS-ALROBOT-FORM」はDDR4リファレンスデザインです。 アクセスするにはNXPに連絡する必要があります。 Re: i.MX8M Plus DDR4-3200 EVK Design file and DDR4 layout guide @seungyeon既にメールで添付してお送りしましたので、ご確認ください。
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mex config generate code different from windows and linux The same XEM file generates different code on different systems. Windows  file generate code normal but linux system generate abnormal precondition:the same as RTD and SDK version install 5.jpg Re: mex config generate code different from windows and linux Hi @Litten  Currently, RTDs are supported only on the Windows platform and are not officially supported on Linux. Even if you are able to install them on Linux, you may encounter additional issues during development and integration. One of the main reasons is that Linux is a case-sensitive operating system,  details about this situation have been discussed in the thread Problems with Lpi2c_Ip_MasterConfig and Lpi2c_Ip_SlaveState struct generation on S32DS for S32K344. BR, VaneB
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mex 配置生成的代码与 Windows 和 Linux 不同 同一个XEM文件在不同的系统中会生成不同的代码。 Windows系统生成的文件代码正常,但Linux系统生成的文件代码异常。 前提条件:与 RTD 和 SDK 版本安装相同 5.jpg Re: mex config generate code different from windows and linux 嗨@Litten 目前,RTD 仅在 Windows 平台上受支持,Linux 平台尚未获得官方支持。即使您能够在 Linux 上安装它们,在开发和集成过程中也可能会遇到其他问题。 主要原因之一是 Linux 是一个区分大小写的操作系统,有关此情况的详细信息已在 S32DS 上针对 S32K344 的 Lpi2c_Ip_MasterConfig 和 Lpi2c_Ip_SlaveState 结构体生成问题线程中进行了讨论。 BR,VaneB
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meter I'm trying to find the meter control within the components, but I can't find it.
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S32K328 HSE-B: Mem_43_INFLSを使用したA/Bスワップの推奨アーキテクチャ(Vector FOTAなし) NXPチームの皆様、こんにちは。 現在、S32K328上で動作する既存のアプリケーションにOTA A/Bスワップのサポートを追加する設計・実装段階にあります。 これは、完全なFOTAフレームワークを統合するのではなく、既存のソフトウェアをOTA機能で拡張する初期実装です。 現在の環境 MCU:S32K328(8MB Pフラッシュ) AUTOSARスタック:ベクターMICROSAR RTD: S32K3_RTD_6_0_0_QLP04_D2508_ASR_REL_4_7_REV_0000_20250822 バイナリ転送インターフェース:UART 画像アクティベーションサービス: HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK HSE A/B スワップは RTD 設定により有効化されます OTAバイナリは、カスタムOTA CDDによってUART経由で受信されます。 現在のVector構成には、NvM/Fee(D-Flash)専用のMemAccMが含まれています。P-FlashアプリケーションをプログラミングするためのMemAccM設定はなく、Vector OTA/FOTAも使用していません。 そのため、OTA CDDのMem_43_INFLSを使って非アクティブなアプリケーションのフラッシュを直接消去・プログラムすることを検討しています。 以下の点についてご指導いただければ幸いです。 1. 推奨されるアプローチ VectorのOTA/FOTAパッケージを使わない場合、A/Bスワップ環境でOTA画像プログラミングを管理するための推奨される低レベルのドライバーはMem_43_INFLSでしょうか? あるいは、MemAccMは、カスタムOTA実装の場合も含め、P-Flashプログラミングに対応するように拡張されるべきでしょうか? 2. 非アクティブなフラッシュブロックのアドレス指定 HSE A/Bスワップを有効にした後: 非アクティブなアプリケーションP-Flashブロックは常にメモリレイアウトで定義された固定物理アドレスを通じてアクセスされるのでしょうか? あるいは、HSEはパッシブブロックに対して何らかの論理マッピングや抽象化を提供しているのでしょうか? 3. 有効化の前提条件 HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK を正常に実行するための必須の前提条件は何ですか? 例: 画像ヘッダー形式 メタデータの要件 整列制約 認証/署名要件 フラッシュ状態または属性 4. フラッシュコントローラの並行処理 S32K328のC40フラッシュコントローラーはDフラッシュ(Fee/NvM)とPフラッシュ(非アクティブブロック)間の同時操作をサポートしていますか? そうでない場合、推奨される同期戦略は何ですか? アプリケーションレベルのスケジューリング RTDドライバ仲裁 MemAccM の使用状況 5. 推奨される建築様式 以下のアーキテクチャはNXPの推奨事項に準拠していますか? UART ↓ カスタムOTA CDD ↓ Mem_43_INFLS(非アクティブなPフラッシュの消去/書き込み) ↓ 画像認証 ↓ HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK ↓ システムリセット ↓ HSE/BAF がパッシブブロックをアクティブ化します 私たちは特に、この軽量化アプローチが適切であり、HSE(環境・安全・衛生)要件に準拠しているかどうかについて、ご助言を求めています。 HSE A/Bスワップ対応のカスタムOTAに関するアプリケーションノート、RTD例、または参考実装があれば、ぜひご指導いただけるとありがたいです。 再開まで今しばらくお待ちください。 よろしくお願いします、 ヴェンカテシュ KV #s32k328 Re: S32K328 HSE-B: Recommended Architecture for A/B Swap using Mem_43_INFLS (without Vector FOTA) こんにちは、 @venkatesh-kv 1.カスタムOTA実装では、パッシブパーティションを消去・プログラムするために直接このMem_43_INFLSを使うことができます。 MemAccMを拡張すべきかどうかはアーキテクチャ上の決定であり、主にアプリケーション内で共通のフラッシュアクセスおよび仲裁レイヤーが望まれるかどうかに依存します。 2. パッシブアプリケーション画像は通常、物理的なP-フラッシュアドレス範囲でプログラムされます。HSEは、パッシブブロック専用の論理アドレス指定抽象化を提供していません。アプリケーション/ブートローダーは新しいイメージを非アクティブなパーティションに書き込む責任があり、その後HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCKを使って次のリセット時にそのパーティションをアクティブにすることができます。 3. セキュアブートを使用する場合、シグネチャは(セキュアブートモードやその他の設定に応じて)更新され、次のリセット後に新しいアプリケーションが正常に認証・実行されるようにすべきです。 旧バージョンのHSEファームウェアでは、サービスHSE_SRV_ID_ACTIVATE_PASSIVE_BLOCKを実行するためにスーパーユーザー権が必要でした。これはファームウェアバージョン0.2.55.0以降では通常のユーザー権限にダウングレードされています。 4. 一度に1つのフラッシュ操作のみが実行可能。フラッシュアクセス仲裁の実装はアプリケーションアーキテクチャに委ねられています。 一般的に、複数のソフトウェアコンポーネントからの同時フラッシュ操作を避け、OTAプログラミング活動とシステム内の他のフラッシュユーザー間の競合を防ぐために、フラッシュアクセスが適切に同期されていることを確認することが推奨されます。 Fee/NvMとMem_43_INFLSの間に同期サポートはありません。 5. はい、その流れで合っています。実際には、交換前に有効なアプリケーションがパッシブパーティションに存在し、署名(またはセキュアブート設定全般)が適切に更新される必要があるという唯一の要件です。 S32K344には基本的なOTAデモ「SW32K3_OTADEMO_0.8.0_D2203」があります。これは新しいアプリケーションをパッシブブロックに書き込み、その後AB SWAPを要求する方法を示しています(これはHSEファームウェアの機能です)。このデモではRTD 1.0.0を使用しています。 次のより高度なデモは「S32K396 OTA Demo version 0.4.0」で、イーサネット経由でファームウェアを更新する方法を示しています。こちらはRTD 3.0.0を使用しています。P07。 両方のデモはS32K3リファレンスソフトウェアで見ることができます: https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-REFSW-D リンクをクリックして「Automotive SW - S32K3 - OTA Demo」で検索してください。 これが唯一のバージョンで、あくまで参考ソフトウェアです。必要に応じて他の派生版や新しいRTDパッケージに移行するのはユーザーが自由に行っています。 そして、以下のOTAトレーニングがあります: https://www.nxp.com/design/design-center/training/TIP-CONNECTS2021-AUT428 https://www.nxp.com/design/design-center/training/TIP-NXP-AUT-T3955A 両者はS32K3のトレーニングセクションでご覧いただけます: https://www.nxp.com/products/S32K3 また、「S32K3XX HSE and OTA Advance トレーニング [TR744101]」もご覧いただけます。これはドキュメント -> Secure files: https://www.nxp.com/products/S32K3 よろしくお願いいたします。 ルーカス
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Architectural Overview for the Dual-Motor EV Control System 1 Introduction After introducing the Dual-Motor EV Traction platform and the Software & Hardware environment behind it, this article moves one step closer to the running application. It looks inside the Motor Control System and explains how the Simulink model is structured to control two PMSM motors using the NXP S32K396 MCU as the target hardware. The goal is to provide a clear architectural view of the application before diving into simulation, validation, or deployment details. We will follow the main signal paths, from vehicle-level CAN commands and inverter feedback to FOC execution, PWM generation, ADC measurement, and communication back to the vehicle network. The focus remains intentionally architectural. Instead of covering controller tuning, peripheral configuration, or low-level implementation, this article highlights the building blocks that make the dual-motor application understandable as a complete embedded control system. This article is organized around five architectural views: the application overview, the system interfaces, the CAN communication path, the Simulink model structure, and the peripheral-to-data-flow mapping. Together, these views explain how the dual-motor application receives commands, measures feedback, executes control, drives the inverters, and reports diagnostic information back to the vehicle network.   2 Table of Contents • Introduction • Application Overview • System Inputs and Outputs • Vehicle-Level Communication • Simulink Application Architecture • Peripheral Mapping • Data Flow • Conclusion • References   3 Application Overview The Motor Control System is implemented on the NXP S32K396 microcontroller and runs as a single-core embedded application. The ECU controls two PMSMs, each connected to its own three-phase inverter stage. From a control perspective, the application contains two Field-Oriented Control implementations. Each FOC instance is responsible for one motor and executes independently, based on its own sensing path, control states, and output generation. Both control loops are scheduled from independent interrupt sources and are triggered every 100 microseconds. This execution period supports the fast current-control layer required by traction inverter applications, while the single-core implementation requires both motor-control paths to complete within the available timing budget.   simulink_overview.png Figure 3-1. Overall Simulink Application At vehicle level, the Motor Control System behaves as a actuating end node. It receives enable and speed commands from the Central Node over CAN and sends back monitoring and diagnostic information at a slower periodic rate. The Motor Control System exchanges CAN data with the vehicle network through the South Zone Controller. 3.1. Control Strategy At the heart of the application is the Field-Oriented Control algorithm, which provides the control structure required to drive each PMSM efficiently and independently. In this architecture, FOC transforms the three-phase motor behavior into a control problem handled in a rotating reference frame, where torque-producing and flux-producing current components are regulated separately. The control strategy is built around speed control. The requested speed comes from the vehicle-level command interface, while the estimated rotor speed is provided by the sensorless observer. The speed controller compares these values and generates the current reference needed to reach the commanded operating point. For each motor, the FOC structure combines an outer speed loop with inner current-control loops. The current PI controllers regulate the direct-axis and quadrature-axis currents in the rotating reference frame, allowing the application to control the electrical behavior of the motor in a deterministic and decoupled way. Sensorless operation is achieved using an Extended EMF Observer. This observer estimates the rotor position and speed from the measured electrical quantities, removing the need for a physical position sensor in the control loop. The estimated position is then used by the Park and inverse Park transformations that connect the stationary and rotating reference frames. The feedback path is based on phase-current reconstruction using the dual-shunt measurement method. The reconstructed phase currents are processed through the Clarke and Park transformations, while the DC bus voltage feedback is used to keep the control and modulation stages aware of the available inverter supply. The two FOC implementations follow the same control structure, but each one operates on its own motor-specific inputs, states, and outputs. This separation allows Motor 1 and Motor 2 to be controlled independently, even though both algorithms execute on the same S32K396 device. Because the control loops are executed every 100 microseconds, the FOC layer must remain compact and deterministic. The model architecture therefore separates the fast control path from slower communication and monitoring tasks, ensuring that current regulation and PWM update remain the highest-priority activities in the application.   mcb_foc.png Figure 3-2. Sensorless Field-Oriented Control diagram 4 System Inputs and Outputs The application interface can be viewed through two categories of signals. The first category contains vehicle-level commands exchanged over CAN. These signals define how the traction application is started, stopped, and commanded from the rest of the vehicle. The second category contains real-time electrical feedback and actuation signals exchanged with the inverter hardware.   in_out_app.png Figure 4-1. Split the Simulink model to Inputs, Outputs and Application layers 4.1. Inputs The main vehicle-level inputs are received from the Central Node over CAN through the South Zone Controller. The command message contains the CCS_EnableMotors signal, used to engage or disengage the motors, and the CCS_SetSpeed signal, used to provide the desired speed reference for the control application.   can_unpack.png Figure 4-2. CAN Message Unpack block for receiving the command signals   These CAN inputs are not part of the fast current-control loop, but they directly influence its behavior. Once decoded, the enable command defines whether the control logic is allowed to drive the inverters, while the speed reference becomes the target followed by the outer speed controller. The hardware feedback inputs are acquired from the inverter stages through ADC measurements. For each motor, two phase currents are measured using the dual-shunt method, while the third phase current is reconstructed in software using Kirchhoff’s Current Law. The DC bus voltage is measured for each inverter so the control, modulation, and monitoring logic remain aware of the available supply voltage.   adc_block.png Figure 4-3. Gathering analog quantities via ADC Block   4.2. Outputs The primary real-time outputs are the PWM commands used to actuate the inverter phases for both motors. The FOC algorithm computes the voltage commands required by each PMSM, and these commands are translated into duty cycles for the three-phase inverter. Because each inverter leg requires a high-side and a low-side control signal, the application ultimately drives six PWM signals per motor. These signals are generated from the MCU timing path and routed to the gate-driver stage that controls the external power switches.   pwm.png Figure 4-4. PWM Actuation Subsystem   In addition to the PWM outputs, the application sends CAN data to the South Zone Controller every 0.1 seconds. These messages are intended for diagnostics, monitoring, and vehicle-level observability. The transmitted CAN data includes the estimated speed of each motor, the fault status reported by each control channel, the measured DC bus voltage for each inverter, the current operating state of each motor-control instance and many more. The following table highlights the output data sent over CAN bus:   Name Description Unit MC_BusVoltageM1 DC Bus Voltage measured by inverter for Motor 1 V MC_BusVoltageM2 DC Bus Voltage measured by inverter for Motor 2 V MC_FaultStatusM1 Fault status reported by Motor 1 true/false MC_FaultStatusM2 Fault status reported by Motor 2 true/false MC_PhACurrentM1 Phase A current – Motor 1 A MC_PhACurrentM2 Phase A current – Motor 2 A MC_PhBCurrentM1 Phase B current – Motor 1 A MC_PhBCurrentM2 Phase B current – Motor 2 A MC_PhCCurrentM1 Phase C current – Motor 1 A MC_PhCCurrentM2 Phase C current – Motor 2 A MC_SpeedEstM1 Motor 1 estimated speed rpm MC_SpeedEstM2 Motor 2 estimated speed rpm MC_SpeedRefM1 Motor 1 desired speed rpm MC_SpeedRefM2 Motor 2 desired speed rpm MCS_StateM1 Motor 1 state. It can be Stand By, Running, Fault - MCS_StateM2 Motor 2 state. It can be Stand By, Running, Fault - MCS_PhAVoltageM1 Phase A Voltage – Motor 1 V MCS_PhAVoltageM2 Phase A Voltage – Motor 2 V MCS_PhBVoltageM1 Phase B Voltage – Motor 1 V MCS_PhBVoltageM2 Phase B Voltage – Motor 2 V MCS_PhCVoltageM1 Phase C Voltage – Motor 1 V MCS_PhCVoltageM2 Phase C Voltage – Motor 2 V   can_pack.png Figure 3-5. Example for CAN Pack Message 5 Vehicle-Level Communication The Motor Control System is part of a distributed EV control architecture. It does not operate as an isolated controller. Instead, it receives high-level commands from the vehicle network and reports measured and estimated values back to the rest of the system. The communication path is organized around the CAN interface between the Central Node, the South Zone Controller, and the Motor Control System Node. Commands such as motor enable and desired speed are received through this path, while feedback messages such as estimated speed, DC bus voltage, phase-current information, and fault status are sent back through the same zonal communication route. CAN receive handling is interrupt-driven. When a command frame is received, the application decodes the enable and speed request signals and updates the internal command variables used by the Simulink control model. This keeps the command interface responsive without placing CAN processing inside the 100 microsecond FOC interrupt.   can_rx_isr.png Figure 4-1. CAN Receive Interrupt block   CAN transmit handling is periodic. A PIT interrupt schedules outgoing monitoring messages every 0.1 seconds. This separates network reporting from the real-time control path and ensures that diagnostics transmission does not disturb the deterministic execution of the motor-control interrupts.   can_tx_isr.png Figure 4-2. Periodic Interrupt for transmitting CAN messages   The CAN database defines the mapping between application variables and network messages. For example, the enable and speed command are grouped in dedicated message, while fault information, estimated speed, DC bus voltage, and phase-current feedback are exposed through dedicated monitoring messages. More information about the CAN database created for organizing the CAN messages and signals will be presented in a dedicated article. 6 Simulink Application Architecture The Simulink model is organized around a dual-control structure. Each motor channel contains the algorithmic blocks required to transform measured currents, estimate rotor position and speed, regulate the control loops, and generate voltage commands for PWM modulation. Although both channels implement the same FOC strategy, they are treated as separate execution paths. This separation makes it easier to scale from a single-motor setup to a dual-motor configuration and to validate each channel independently before running both motors together. 6.1. Real-Time Control Layer The real-time control layer is executed inside the BCTU-triggered interrupt flow. The BCTU is synchronized with the PWM timing generated by eMIOS, so the ADC conversions are requested at the correct moment within the switching period. Once the required current measurements are available, the interrupt allows the control algorithm to run using a coherent feedback set.   foc_simulink.png Figure 5-1. FOC Implementation   Inside this layer, the application reconstructs the three-phase current set, executes the Clarke and Park transformations, estimates rotor position and speed through the Extended EMF Observer, runs the speed and current PI controllers, and generates the voltage commands required by the modulation stage. The voltage commands are then translated into PWM duty cycles. eMIOS provides the base PWM generation, while the LCU forms the complementary high-side and low-side signals needed by the inverter legs. LCU also adds the necessary dead-time in complementary PWM signals to avoid the DC source damage. TRGMUX routes the required trigger signals between these peripherals, maintaining alignment between actuation and measurement.   fast_loop_simulink.png Figure 5-2. Fast Loop Subsystem   The same execution concept is applied to the second motor channel. The two FOC instances run on the same S32K396 core, so the application depends on the MCU processing capability and on a carefully scheduled interrupt structure to complete both control paths within the available timing budget. 6.2. Communication and Monitoring Layer The communication and monitoring layer connects the fast control application with the vehicle network. It receives the enable and speed commands from CAN, prepares diagnostic information, and schedules outgoing status messages. This layer runs at a lower rate than the FOC loops. It is intended for command exchange, observability, and integration with the Central Node through the South Zone Controller. 6.3. Hardware Abstraction and Peripheral Layer The hardware abstraction and peripheral layer connects the generated Simulink application to the physical resources of the S32K396 MCU. Its purpose is to keep the control algorithm separated from the low-level hardware access, while still allowing the model to read measurements, update PWM outputs, handle interrupts, and exchange data over communication interfaces. In practice, this layer contains the target-specific blocks used for ADC acquisition, PWM generation, and CAN communication. These blocks provide the interface between the algorithmic part of the model and the peripherals configured on the MCU. This layer also makes the model easier to understand and maintain. The FOC subsystems can remain focused on control behavior, while the peripheral layer handles how signals enter and leave the MCU. As a result, the same architectural structure can be reused when moving between simulation, generated code, and target execution. The NXP Model-Based Design Toolbox provides the Simulink blocks that expose these S32K396 peripherals at model level. This allows engineers to configure and connect hardware-facing functions directly in Simulink, while the generated embedded code uses the corresponding target drivers and configuration. 7 Peripheral Mapping The peripheral mapping is centered on the synchronization between measurement, control execution, actuation, gate-driver communication, and vehicle-level CAN communication. Each peripheral has a specific role in this chain, and together they allow the generated Simulink application to interact deterministically with the inverter hardware. SAR-ADC is used to measure the analog quantities required by the control algorithm. These measurements include the phase-current feedback acquired from the inverter stages and the DC bus voltage used by the modulation and monitoring logic. BCTU (Body Cross Triggering Unit) performs the triggering of the ADC conversions. Instead of sampling the analog signals at an arbitrary moment, BCTU waits for the synchronization event coming from the PWM timing path and then starts the SARADC conversions at the correct point in the switching period. eMIOS (Enhanced Multiple Input Output System) generates the three phase PWM signals for each motor channel. These PWM signals represent the base timing generated from the duty cycles computed by the FOC algorithm. LCU (Logic Control Unit) takes the three PWM signals generated by eMIOS and creates the six PWM outputs required by the inverter. For each motor phase, it generates the complementary high-side and low-side control signals with dead-time insertion used to drive the corresponding inverter leg. TRGMUX provides the internal routing between peripherals. It connects the three PWM outputs from eMIOS to the LCU inputs and also routes the synchronization signal between eMIOS and BCTU. This routing keeps the actuation path and the measurement path aligned. LPSPI is used as the communication layer between the S32K396 controller and the MC33937 gate driver. Through this interface, the application can configure and exchange diagnostic information with the gate-driver device, complementing the direct PWM actuation path. FlexCAN provides the CAN communication controller used by the Motor Control System. It enables reception of command messages from the South Zone Controller and transmission of monitoring and diagnostic data back to the vehicle network. In this mapping, the fast motor-control path is formed by eMIOS, TRGMUX, BCTU, SARADC, and LCU, while LPSPI supports gate-driver interaction and FlexCAN supports vehicle-level communication. This separation helps keep the time-critical control loop independent from slower configuration, diagnostics, and network tasks.   peripherals.png Figure 6-1. Peripherals Mapping Overview   PIT (Periodic Interrupt Timer) peripheral is used for slower periodic activity, such as CAN diagnostics transmission every 0.1 seconds. CAN receive interrupts are used for incoming command messages from the South Zone Controller. 8 Data Flow The data flow starts at the vehicle network and at the analog feedback interface. CAN provides the high-level operating commands, while the inverter sensing path provides the real-time electrical feedback required by the FOC loops. When a CAN command is received, the enable and speed references are decoded and stored as application-level command variables. These signals are then consumed by the motor-control logic during the next control execution. In parallel, synchronized ADC conversions provide the latest phase-current and DC bus voltage values. The control algorithm reconstructs the motor currents, estimates rotor position and speed, transforms the feedback into the rotating reference frame, and computes the required voltage commands. The voltage commands are converted into PWM duty cycles and applied to the inverter actuation path. The resulting gate-drive signals control the external power stage, which drives the PMSM phases. At a slower rate, selected internal variables are packed into CAN monitoring frames. These values allow the South Zone Controller and Central Node to observe the Motor Control System state without interfering with the fast control-loop execution. 9 Conclusion This article described the architectural overview of the Dual-Motor EV Control System application. It presented the main Simulink model structure, the system inputs and outputs, the vehicle-level CAN communication path, the peripheral mapping, and the data flow between command reception, sensing, control, actuation, and monitoring. The architecture is built around two independent FOC control paths running on the S32K396 in a single-core configuration. Each motor channel receives synchronized analog feedback, executes its control algorithm every 100 microseconds, and generates the PWM outputs required by its inverter stage. By combining Model-Based design with target-specific peripheral integration, the application provides a scalable foundation for validating dual-motor traction behavior in simulation and on real hardware. The next article can build on this architecture by focusing on Model-in-the-Loop development and controller validation before deployment. 10 References Developing a Dual-Motor EV Control System with Model-Based Design Toolbox Software & Hardware Enablement for the Dual-Motor EV Control System Sensorless FOC with Motor Control Blockset Extended EMF Observer – Motor Control Blockset NXP Model-Based Design Toolbox for S32K3 NXP S32K396 microcontroller documentation AN14481: MCSPTR2AK396 3-phase PMSM Motor Control Kit with S32K396 Application Note
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LPC-Link2のシリアル番号の一貫性について 複数のLPC-Link2チップのシリアル番号が同一である場合、それらのシリアル番号を変更する方法を教えていただきたいです。よろしくお願いいたします。 Re: 关于lpc-link2 SN码一致 こんにちは@chenwe97 このシリアル番号は変更できません。 複数のLPC-LINK2デバイスを同時に接続する場合は、CMSIS-DAPファームウェアにアップデートすることをお勧めします。これにより、各デバッガに固有のID番号が割り当てられます。 BR アリス
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关于lpc-link2 SN码一致 想请问下几块lpc-link2  SN码一致的情况下,怎么更改,谢谢。 Re: 关于lpc-link2 SN码一致 Hi @chenwei97  这个SN 码没办法修改。 如果您是为了同时连接多个LPC-LINK2,建议更新成CMSIS-DAP固件。这样每个调试器会有唯一的ID号。 BR Alice
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