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S32K328 HSE-B: Recommended Architecture for A/B Swap using Mem_43_INFLS (without Vector FOTA)

Hello NXP Team,

We are currently in the design and implementation phase of adding OTA A/B swap support to an existing application running on S32K328.

This is an initial implementation where we are extending the existing software with OTA capability rather than integrating a complete FOTA framework.

Current Environment

MCU: S32K328 (8 MB P-Flash)
AUTOSAR Stack: Vector MICROSAR
RTD: S32K3_RTD_6_0_0_QLP04_D2508_ASR_REL_4_7_REV_0000_20250822
Binary transfer interface: UART
Image activation service: HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK
HSE A/B swap is enabled via RTD configuration

The OTA binary is received over UART by a custom OTA CDD.

Our current Vector configuration contains MemAccM only for NvM/Fee (D-Flash). There is no MemAccM configuration for programming the application P-Flash, and we are not using Vector OTA/FOTA.

Therefore, we are considering using Mem_43_INFLS from the OTA CDD to erase and program the inactive application flash directly.

We would appreciate guidance on the following points.

1. Recommended approach

Is Mem_43_INFLS the recommended low-level driver for managing OTA image programming in an A/B swap setup when not using Vector’s OTA/FOTA package?

Or should MemAccM be extended to cover P‑Flash programming even for custom OTA implementations?

2. Inactive flash block addressing

After enabling HSE A/B swap:

Is the inactive application P‑Flash block always accessed via fixed physical addresses defined in the memory layout?
Or does HSE provide any logical mapping or abstraction for the passive block?

3. Preconditions for activation

What are the mandatory preconditions for successful execution of HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK?

For example:

Image header format
Metadata requirements
Alignment constraints
Authentication / signature requirements
Flash state or attributes

4. Flash controller concurrency

Does the C40 flash controller on S32K328 support concurrent operations between D‑Flash (Fee/NvM) and P‑Flash (inactive block)?

If not, what is the recommended synchronization strategy:

Application-level scheduling
RTD driver arbitration
MemAccM usage

5. Recommended architecture

Is the following architecture aligned with NXP recommendations?

UART
↓
Custom OTA CDD
↓
Mem_43_INFLS (erase/write inactive P‑Flash)
↓
Image verification
↓
HSE_SRV_ID_ACTIVATE_PASSIVE_BLOCK
↓
System reset
↓
HSE/BAF activates the passive block

We are specifically looking for guidance on whether this lightweight approach is appropriate and compliant with HSE requirements.

If there are any application notes, RTD examples, or reference implementations for custom OTA with HSE A/B swap, we would greatly appreciate your guidance.

Thank you for your support.

Best regards,
Venkatesh KV

#s32k328