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AFT05MS004NT1 型号的 ADS Keysight ADS 型号 AFT05MS004NT1 和 RF Power ADS DK 不适用于 ADS 2027。 它返回此错误。 模拟消息 hpeesofsim 在解析网表时检测到警告。 模型“FSL_AFT05MS004N_FET2.FET2M1”(定义于文件“C:/ADS_USER/PDK and Supplier Libraries/AFT05MS004N_Level1_Rev0_DK//circuit/models/fsl_AFT05MS004N_pkg_netlists.net”第 31 行附近):“FSLRFPK_FET2”是未定义的原始设备。 hpeesofsim 在网表展平过程中检测到错误。 `FSL_AFT05MS004N_FET2.FSL1` 是未定义模型 `FET2M1` 的一个实例。 状态/摘要 hpeesofsim (*) 650.shp 2026年7月29日,MINT 版本 5 (64 位 Windows 构建于:2026 年 7 月 29 日星期三 11:10:28 +0000) ***** 模拟开始于 2026 年 9 月 16 日星期三 15:58:10 运行于主机“XXXX” 在目录“C:\ADS_USER\AFT05MS004NT1_Project\AFT05MS004NT1_wrk\data”中 进程 ID:19040 -------------------- 模拟因错误而终止。 -------------------- 这款晶体管目前仍可通过代理商购买。 射频 Re: ADS Model of AFT05MS004NT1 你好,穆罕默德 我不会说它已经完全放弃了;就目前而言,我会把它描述为暂停开发——如果需求持续高涨,这种情况将来可能会改变,尽管目前还没有发布新版本或更新的计划。 对于可能由此导致的不便,我们深感抱歉。 Re: ADS Model of AFT05MS004NT1 感谢您的快速回复。 你说恩智浦退出了射频业务,但如下所示,市场对射频产品有着巨大的需求。 无论如何,谢谢。我会改变我的做法。 Screenshot_16-9-2026_1682_www.mouser.fr.jpegScreenshot_16-9-2026_1682_www.mouser.fr.jpeg Re: ADS Model of AFT05MS004NT1 你好 tbursali 再会! 现有模型尚未在 2027 版本中进行测试。 目前,最新使用并验证功能正常的版本是 2025 套件。 因此,我建议您访问我们的官方网站,重新下载并安装那里推荐的模型套件,以及 AFT05MS004N 的模型设计。 https://www.nxp.com/products/radio-frequency-rf/rf-high-power-models/models-for-ads-keysight-advanced-design-system:RF_HIGH_POWER_MODELS_KEYSIGHT NXP 已决定缩减其射频部门的规模,导致该领域的许多同事离开了公司;因此,目前没有发布进一步更新或新产品的计划。 对于可能由此导致的不便,我们深感抱歉。 希望这些信息对您有所帮助,如果您还需要其他帮助,请告诉我。 祝你今天过得愉快,一切顺利。
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NXP S32k118 I2Cエミュレーション こんにちは、 私は、I2Cマルチプレクサを使用せずに、S32K118(Q48)マスターから10個の同一アドレスのI2Cスレーブを同時に駆動する方法を評価しています。 私の計画は、ハードウェアタイマーでクロックを生成し、DMA転送を組み合わせて同じポート上の10本のGPIOピンを同時に更新することで、10本の並列I2Cバスをエミュレートすることです。 S32K118のDMAやタイマー**ペリフェラル**が、このような方法でポート全体のGPIO更新をトリガーできるかどうか、確認を手伝ってもらえますか?このアーキテクチャに関して注意すべきハードウェアの制限やエッジケースはありますか? よろしくお願いいたします。 Re: NXP S32k118 I2C emulation こんにちは、 @Luke_John さん。 はい、このアーキテクチャは基本的にサポートしています。 S32K1xxシリーズリファレンスマニュアル、Rev. 14を参照: 第13.3.1項 GPIOレジスタの説明 ご覧の通り、すべてのGPIOポートは32ビットレジスタからアクセス可能です。 セクション 17 4.1「GPIOポートを使用して波形を駆動またはサンプリングする」DMAを構成してデータを1つ以上のGPIOポートに転送することにより、オンチップメモリに格納された表形式データを使用して複雑な波形を作成することが可能です。逆に、DMAを使用して1つまたは複数のGPIOポートからデータを定期的に転送することで、複雑な波形をサンプリングし、その結果を表形式でオンチップメモリに保存することが可能です。 DMAトランスファーはDMAMUXやTRGMUXのタイマーでトリガーできます。 シームレスなDMA転送を実現するには、クロスバーをラウンドロビンアービトレーション(MCM_CPCR[CBRR]を「1」に設定)にプログラムする必要があります。 よろしくお願いいたします。 ダニエル
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LPUART1 TX FIFO Failed Hi all, I'm working with an S32K311 and a custom bare-metal driver for two LPUART instances configured identically (115200 8N1, TX/RX FIFO enabled, same init sequence). LPUART0 works perfectly with both TX and RX FIFOs enabled. LPUART1 does not: TX: a single write to DATA (or a single push while FIFO[TXFE]=1) results in the same byte being physically transmitted 3 times on the TX pin. This is not garbage/noise — it's the exact byte I wrote, repeated 3 times back-to-back. Verified with an oscilloscope/logic analyzer on the TX pin (GPIO71). RX: reception does not behave correctly while the RX FIFO is enabled on this instance either (no usable data comes back), unlike LPUART0. What I've already ruled out / verified: Baud rate / clock is correct: I do not see corrupted or misaligned characters, only the correct byte value duplicated 3 times, which points away from an oversampling/BAUD (OSR/SBR) miscalculation. Clock gating is enabled for both instances: the MC_ME peripheral clock request is enabled for LPUART0 and LPUART1 in the same way (same partition, sequential request IDs), and LPUART0 with the identical code path works fine. Workarounds found by trial and error: Disabling the TX FIFO (FIFO[TXFE]=0) on LPUART1 fixes the transmit issue (single frame per write, using STAT[TDRE] instead of WATER[TXCOUNT] for flow control). Leaving the RX FIFO enabled (FIFO[RXFE]=1) is required for RX to work on LPUART1 at all. So the only configuration that works on LPUART1 is: TX FIFO disabled, RX FIFO enabled — which is the opposite of LPUART0 (where both FIFOs enabled work fine), and obviously reduces TX throughput/burst capability. Questions: Is there a known erratum for the S32K311 LPUART1 instance (or a specific LPUART instance limitation) related to the TX FIFO causing duplicated frames? Is there any additional register/bit (beyond FIFO[TXFE], WATER, BAUD[TDMAE]) that needs different handling specifically for LPUART1 vs LPUART0 on this device? Has anyone else observed this same "byte transmitted 3 times when TX FIFO is enabled" behavior on a specific LPUART instance rather than all instances uniformly? Any pointers to the errata sheet, silicon revision notes, or a known workaround explanation would be greatly appreciated. Re: LPUART1 TX FIFO Failed Hi @ijm1, I have seen unpredictable behavior in hardware modules when the ratios between clock domain frequencies do not match any of the supported clock options. The system clock must always be configured according to one of the valid clocking options listed in the RM. The key requirement is that the ratios between the clocks remain exactly as defined. As stated under Table 151 (For S32K312, S32K311, and S32K310) in the RM: "…any clock frequency selected must adhere to the same clock divider ratios shown in System clocking configurations." Could you please verify this first? Regards, Daniel
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The s32k3 mbdt (version 1.4.2) is reporting a missing file when using the wdg module. I'm using version 1.4.2 of the mbdt library on my S32K3, using the wdg module, and I'm getting the error "AeWdog_Ip_Irq.c:45:10:" when generating the code.fatal error: AeWdog_Ip_Cfg_Defines.h:No such file or directory. (This file is indeed missing.) When I manually added him from the RTD library, everything else threw errors. There were even more errors. What's going on? Did I make a configuration error? Please help!
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s32k3 mbdt(版本1.4.2)使用wdg模块报缺少文件 我使用S32K3的mbdt库版本是1.4.2版本,使用wdg模块,生成代码的时候报AeWdog_Ip_Irq.c:45:10: fatal error: AeWdog_Ip_Cfg_Defines.h: No such file or directory。确实此文件 当我把他从rtd库手动加进去他,其他都报错了。错误更多了 这是咋回事,我配置出问题了吗?请求解答
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ADS Model of AFT05MS004NT1 The particular Keysight ADS model of AFT05MS004NT1 with RF Power ADS DK is not valid for ADS 2027. It returns back with this error. Simulation Messages Warning detected by hpeesofsim during netlist parsing. Model `FSL_AFT05MS004N_FET2.FET2M1' (defined in file 'C:/ADS_USER/PDK and Supplier Libraries/AFT05MS004N_Level1_Rev0_DK//circuit/models/fsl_AFT05MS004N_pkg_netlists.net' around line 31): `FSLRFPK_FET2' is an undefined primitive device. Error detected by hpeesofsim during netlist flattening. `FSL_AFT05MS004N_FET2.FSL1' is an instance of an undefined model `FET2M1'. Status / Summary hpeesofsim (*) 650.shp Jul 29 2026, MINT version 5 (64-bit windows built: Wed Jul 29, 2026 11:10:28 +0000) ***** Simulation started at Wed Sep 16 15:58:10 2026 Running on host: "XXXX" In Directory: "C:\ADS_USER\AFT05MS004NT1_Project\AFT05MS004NT1_wrk\data" Process ID: 19040 -------------------- Simulation terminated due to error. -------------------- This transistor is still available in distributors. RF Re: ADS Model of AFT05MS004NT1 Hello Mohamed I wouldn't say it has been completely abandoned; for the moment, I would describe it as being on hold—a situation that could change in the future if demand remains high, though there are currently no plans for new releases or updates. We apologize for any inconvenience this may cause. Re: ADS Model of AFT05MS004NT1 Thank you for the quick response. You say NXP leaves the RF business, but there is a huge demand for RF products shown below. Thanks anyway, I will change my way in this case. Screenshot_16-9-2026_1682_www.mouser.fr.jpegScreenshot_16-9-2026_1682_www.mouser.fr.jpeg Re: ADS Model of AFT05MS004NT1 Hello tbursali Good day! The existing models have not been tested in version 2027. Currently, the latest version that was used and verified as functional is the 2025 kit. Therefore, I recommend visiting our official website to re-download and install the model kit recommended there, as well as the model design for the AFT05MS004N. https://www.nxp.com/products/radio-frequency-rf/rf-high-power-models/models-for-ads-keysight-advanced-design-system:RF_HIGH_POWER_MODELS_KEYSIGHT NXP has decided to ramp down its RF division, leading many colleagues in that area to leave the company; consequently, there are currently no plans to release further updates or new products. We apologize for any inconvenience this may cause. I hope this information has helped you, please let me know if you need help with anything else. Have a great day and best of luck.
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EVBMA7518S48V I want to run an example on it Please help, need details on the entire tool chain flow to flash an initial program on this board. I have attached the errors we are facing below. I also need the link to user guides and manual and also, the getting started guide has a open GUI tool, which I couldn't find anywhere for the BMA7518 And also is there a direct .hex file or something, we can run the board directly? The user guide says the required software are below.  I got s32DS (mention if version matters) and I don't know where to download unionGUI, I downloaded the EVALGUI that doesn't support 7318 or 7518. Where to find the example code? • S32DS-ARM: S32 Design Studio for S32 • UnionGUI • EVBMA7518S48V example code WhatsApp Image 2026-09-16 at 1.00.17 PM (1).jpegWhatsApp Image 2026-09-16 at 1.00.17 PM (1).jpeg WhatsApp Image 2026-09-16 at 1.00.17 PM.jpegWhatsApp Image 2026-09-16 at 1.00.17 PM.jpeg
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ADSモデル・オブ・AFT05MS004NT1 RFパワーADS DKを搭載した特定のKeysight ADSモデルAFT05MS004NT1は、ADS 2027には適用できません。 このエラーが返されます。 シミュレーションメッセージ hpeesofsimがネットリスト解析中に警告を検出しました。 モデル『FSL_AFT05MS004N_FET2』。FET2M1」(ファイル『C:/ADS_USER/PDK and Supplier Libraries/AFT05MS004N_Level1_Rev0_DK//circuit/models/fsl_AFT05MS004N_pkg_netlists.net』の31行付近に定義):『FSLRFPK_FET2』は未定義のプリミティブデバイスです。 hpeesofsimによるネットリストのフラット化中にエラーが検出されました。 「FSL_AFT05MS004N_FET2。FSL1」は未定義モデル「FET2M1」のインスタンスです。 ステータス/概要 hpeesofsim (*) 650.shp 2026年7月29日、MINTバージョン5 (64ビット版Windowsビルド日時: 2026年7月29日(水) 11:10:28 +0000) ***** シミュレーションは2026年9月16日(水) 15:58:10に開始されました ホスト上で実行中: "XXXX" ディレクトリ: "C:\ADS_USER\AFT05MS004NT1_Project\AFT05MS004NT1_wrk\data" プロセスID: 19040 -------------------- エラーのためシミュレーションが終了しました。 -------------------- このトランジスタは現在も代理店で入手可能です。 RF Re: ADS Model of AFT05MS004NT1 こんにちは、モハメドさん 完全に放棄されたとは言えません。現時点では保留状態と表現します。需要が高まれば状況は変わるかもしれませんが、現時点では新しいリリースやアップデートの計画はありません。 ご迷惑をおかけして申し訳ありません。 Re: ADS Model of AFT05MS004NT1 迅速なご対応ありがとうございます。 NXPがRF事業から撤退したと言いますが、以下に示すRF製品への需要は非常に高いです。 とにかくありがとうございます。この場合はやり方を変えます。 Screenshot_16-9-2026_1682_www.mouser.fr.jpegScreenshot_16-9-2026_1682_www.mouser.fr.jpeg Re: ADS Model of AFT05MS004NT1 こんにちは、tbursaliさん 良い一日! 既存のモデルは2027年版でテストされていません。 現在、使用実績があり、動作確認済みの最新バージョンは2025年版キットです。 したがって、公式ウェブサイトで推奨されているモデルキットとAFT05MS004Nのモデルデザインを再ダウンロード・インストールすることをお勧めします。 https://www.nxp.com/products/radio-frequency-rf/rf-high-power-models/models-for-ads-keysight-advanced-design-system:RF_HIGH_POWER_MODELS_KEYSIGHT NXPはRF部門の縮小を決定し、多くの同僚が離社しました。その結果、今後のアップデートや新製品のリリース計画はありません。 ご迷惑をおかけして申し訳ありません。 この情報がお役に立てば幸いです。他に何かご不明な点がありましたら、お気軽にお問い合わせください。 良い一日をお過ごしください。幸運を祈ります。
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NXP S32k118 I2C emulation Hello, I am evaluating an approach to drive 10 identical-address I2C slaves simultaneously from an S32K118 (Q48) master without using an I2C multiplexer. My plan is to emulate 10 parallel I2C buses by using a hardware timer to generate the clock, combined with DMA transfers to simultaneously update 10 GPIO pins on the same port. Could you help confirm if the S32K118’s DMA and timer peripherals support triggering port-wide GPIO updates in this manner? Are there any hardware limitations or edge cases I should be aware of with this architecture? Best regards, Re: NXP S32k118 I2C emulation Hi @Luke_John, Yes, this architecture does fundamentally support. Refer to S32K1xx Series Reference Manual, Rev. 14: Section 13.3.1 GPIO register descriptions. As you can see, all the GPIO ports are accessible from 32bit registers. Section 17.4.1 "Using the GPIO ports to drive or sample waveforms By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip memory." The DMA tranfers can be triggered by a timer through DMAMUX, TRGMUX. Crossbar must be programmed to round-robin arbitration (configuring MCM_CPCR[CBRR] as '1') for seamless DMA transfers. Regards, Daniel
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EVBMA7518S48Vでサンプルを実行したい 助けてください。このボードに初期プログラムを書き込むためのツールチェーン全体の流れについて、詳細な情報が必要です。発生しているエラーを以下に添付しました。ユーザーガイドとマニュアルのリンクも欲しいですし、入門ガイドにはオープンなGUIツールがあるのですが、BMA7518はどこにも見つかりませんでした また、直接.hexファイルはありますか?ファイルか何か、直接理事会を運営できる? ユーザーガイドには必要なソフトウェアが以下にあると書かれています。 私はs32DSを手に入れました(バージョンが重要かどうかも言及してください)が、unionGUIのダウンロード先がわからず、7318や7518をサポートしていないEVALGUIをダウンロードしました。サンプルコードはどこで入手できますか? • S32DS-Arm: S32 Design Studio ・UnionGUI ・EVBMA7518S48V例コード WhatsApp Image 2026-09-16 at 1.00.17 PM (1).jpegWhatsApp 画像 2026-09-16 午後1時00分17秒 (1).jpeg WhatsApp Image 2026-09-16 at 1.00.17 PM.jpegWhatsApp 画像 2026-09-16 午後1時00分17秒.jpeg
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NXP S32k118 I2C 仿真 你好, 我正在评估一种方法,即在不使用 I2C 多路复用器的情况下,从 S32K118 (Q48) 主设备同时驱动 10 个地址相同的 I2C 从设备。 我的计划是使用硬件定时器生成时钟来模拟 10 个并行的 I2C 总线,并结合 DMA 传输来同时更新同一端口上的 10 个 GPIO 引脚。 能否帮忙确认一下 S32K118 的 DMA 和定时器外设是否支持以这种方式触发端口范围的 GPIO 更新?这种架构是否存在我需要注意的硬件限制或特殊情况? 顺祝商祺! Re: NXP S32k118 I2C emulation 嗨@Luke_John , 是的,这种架构从根本上来说是支持的。 请参阅 S32K1xx 系列参考手册,修订版 14: 第 13.3.1 节 GPIO 寄存器描述。 如您所见,所有 GPIO 端口均可通过 32 位寄存器访问。 第 17.4.1 节 “使用 GPIO 端口驱动或采样波形 通过配置 DMA 将数据传输到一个或多个 GPIO 端口,可以使用存储在片上存储器中的表格数据创建复杂的波形。反之,利用DMA定期从一个或多个GPIO端口传输数据,可以对复杂的波形进行采样,并将结果以表格形式存储在片上存储器中。 DMA 传输可以通过定时器经由 DMAMUX、TRGMUX 触发。 必须将交叉开关编程为轮询仲裁(将 MCM_CPCR[CBRR] 配置为“1”),才能实现无缝 DMA 传输。 此致, 丹尼尔
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i.MX95:A55 始终无法完成上电或掉电——在两块不同的板上都出现相同的卡顿现象。 摘要 在 i.MX95 的自定义系统管理器配置中,启动 A55 逻辑机器 (LM1) 时,共享驱动程序函数内部出现卡顿。 SRC_MixSoftPowerUp() ( devices/MIMX9/drivers/fsl_src.c ) srcMixIdx = PWR_MIX_SLICE_IDX_A55P (索引 11)。 SRC_MixPowerUpCompleted() 永远不会返回真值, 函数状态 冻结在混合/不一致的状态,SM 自身的 WDOG2 最终触发 FCCU 重置。 关键在于,当强制执行完整的断电再开机循环时, 关机请求始终无法完成 — 硬件对此混音的软件功率控制没有响应 任何一个 方向。 相同的固件在两块物理结构不同的主板(FRDM-IMX95 15x15/LPDDR4x 和 FRDM-IMX95-PRO 19x19/LPDDR5)上都出现了完全相同的卡顿现象,而 两款主板出厂时自带的 eMMC 镜像都能启动到完整的 Linux 用户空间,因此可以证明芯片和主板本身具备这种能力。 我已经用确凿的证据(如下所列)排除了许多可能的病因,希望得到关于剩余病因的指导。 环境 物品价值 SoC i.MX95 (B0) 电路板 FRDM-IMX95(15x15,LPDDR4x) 和 FRDM-IMX95-PRO(19x19,LPDDR5) 系统管理器 nxp-imx/imx-sm 在 lf-6.18.20-2.0.0-5-g3198944 SM配置 自定义(SMCT/.mex 生成), 不是 mx95evk M33/SM状态 功能齐全 M7状态 功能完全正常——SCMI、TRDC分区、STOP/SUSPEND/深度空闲、I2C、以太网MDIO全部功能正常 A55(LM1) 如描述所示,失败了。 启动介质已测试 SD 和 eMMC(结果相同) 症状 A55 可通过 M7 按需启动 SCMI_LmmBoot() (也可以手动重现) lm LM1 启动 来自 SM 调试监视器)。 SCMI 调用本身成功: 状态 = 0 LM1随后报告 SCMI_LMM_STATE_SUSPEND (状态 = 2) 执行停滞 SRC_MixSoftPowerUp() 等待 SRC_MixPowerUpCompleted(PWR_MIX_SLICE_IDX_A55P) 函数状态 已冻结超过 400 万次投票迭代 如果放任不管,SM 的 WDOG2 监控狗会触发 FCCU RESET(错误 ID = 18),导致包括 M7 在内的整个系统崩溃。 登记证据 SRC_XSPR_CORTEXMIX_PLATFORM (混合指数 11) 函数状态 冻结 0x00001010 或者 0x00001011 根据入口状态而定。 解码七个状态字段 PWR_MIX_FUNC_STAT_PUP/PDN: 现场观测状态 PSW_STAT “向上”模式 SSAR_STAT “向上”模式 A55_HDSK_STAT “向上”模式 SYSMAN_STAT “向上”模式 RST_STAT “断电”模式 ISO_STAT “断电”模式 内存状态 “断电”模式 这是一种不一致的状态,既不符合完全启动的状态,也不符合完全关闭的状态,而且它不会取得进展。 硬件测量 一个内窥镜被放置在 VDD_ARM (电感 L7 之后、分立式 PPF5301 DCDC 下游的输出电容 C211–C215——该板具有真正的专用 ARM 电源轨)。在 lm LM1 启动 试图: 该铁路已经投入使用。 约 0.92 V 尝试 它 明显下降 尝试 所以这是一个真实存在的、可物理观察到的不完全电源转换,而不仅仅是权限/时序/软件方面的问题。 最具信息量的单个数据点 强制 A55P 混合模式执行整个断电-再断电循环(无条件执行)(绕过 MEM_STAT == 0 大门——即 SLICE_SW_CTRL |= PDN_SOFT,等待 关机完成 SLICE_SW_CTRL &= ~PDN_SOFT,等待 PowerUpCompleted)显示 即使明确发出关机请求,也无法完成。 函数状态 整个等待过程中保持不变。 这表明问题出在 SRC 寄存器接口之下——例如 GPC 握手前提条件、SRC 模块本身缺少时钟信号,或者板/PMIC 响应问题——而不是任何可纠正的问题。 SRC_MixSoftPowerUp() 自身的排序逻辑。 已经调查并排除(有证据支持) PERF_A55 争论 (3 → 0,ODV → PRK 电压等级)— 任一值均出现字节相同的故障。排除了DVS/电压等级不匹配的可能性。 config_bctrl.h (SM_BCTRL_A_CONFIG / SM_BCTRL_W_CONFIG) — 我的配置中为空;正在填充它 mx95evk 的值没有任何变化。然后我阅读了实时登记表。 工厂运作系统 通过 SM 监测 (BLK_CTRL_NS_AONMIX) 0x44210008–0x44210024, BLK_CTRL_WAKEUPMIX 0x42420030–0x42420064) — 每个词都匹配 mx95evk 准确引用。 SM_A55P_CONFIG, config_user.h、TRDC SRC/GPC/ANATOP 授权、WDOG2 超时 — 全部确认与 mx95evk,或已确认不是阻塞者。(SM 自身的 DOM2 TRDC 对这些寄存器的访问已被证实有效——我可以读取和写入改变的寄存器值。)笔记 SM_A55P_CONFIG 和 SM_DDR_CONFIG 为空 mx95evk 自己的配置也是如此。 SRC_MixIsPwrReady() 警卫 — 逻辑正确,但在这里它确实返回 false(混合位状态),所以它的行为永远不会改变。 无条件 SRC_MixSetA55HdskMode(..., ACK_WAIT) — 无效; A55_HDSK_STAT 一直以来都处于正确的“向上”模式。 较新的SM固件 — 跨越 Walnascar → Whinlatter 跨度的固定 SRCREV 的差异: 零变化 到 设备/MIMX9/ (包括 fsl_src.c, dev_sm_cpu.c, dev_sm_power.c)。 uboot-imx 差异 ——不同版本之间确实存在差异,但没有哪一方面是致命的。 PD_A55P/SRC_XSPR/A55 上电。从构造上来说也是如此:U-Boot SPL 运行 在 A55 公路上,即只有在这次强化成功之后。 ERR053228 模拟 (MTR_ACK_CTRL) — i.MX95 具有每种混合比例 MTR_ACK_CTRL/MTR_ACK_STAT 握手(偏移量 0x90/0x94)的复位默认值(CNT_MODE = 0)会无限期地等待硬件 MTR 确认,这看起来与卡住的情况很吻合。 MEM_STAT。我写 CNT_MODE = 3 (超时模式)最大 MTR_CNT_CFG 在上电转换之前,并通过回读确认写入生效(无)。 LOCK_CFG 干涉)。 没有变化。 真实工厂 AP 二进制文件 — 提取 bl31.bin / tee.bin / u-boot* 我从这块 板 自带的已知良好的工厂eMMC镜像中获取了这些信息,并将它们构建到我的系统中。 flash.bin。 无变化 (这是意料之中的,因为停顿发生在 U-Boot 的第一条指令之前)。 熔丝/OTP — 已排除:每个芯片的熔丝只烧断一次,而工厂镜像和我的镜像都运行在同一个芯片上。 同一块物理电路板。 启动介质 — SD卡和eMMC卡均经过测试,结果相同。 工厂 SM 二进制来源 — 我想重点强调这一点,因为它否定了“NXP 可能会发布不同的 SM 版本”这种说法。我提取了工厂 eMMC 自身的 M33 镜像(ROM 容器 3,镜像 3, CORE_CM33,容器相对偏移 0x79000,大小 使用 0x2C800 使用 mkimage_imx8 -soc IMX9 -parse 命令解析图像,并验证了提取结果。 与容器自身记录的哈希值完全匹配的 SHA384 值。其版本横幅显示:   来自 SM 的问候(版本 819,提交 c450f539,2026 年 3 月 9 日 03:24:50)   c450f539 已确认(git merge-base --is-ancestor)为 我自己的版本,以及唯一涉及此构建的中间提交 fsl_src.c/dev_sm_cpu.c/dev_sm_power.c 纯粹是测试框架清理,没有功能性改变。 所以,能够成功启动 A55 的工厂镜像,其运行的功能与我这边失败的 SM 源相同。 问题 鉴于工厂镜像使用功能相同的SM源启动A55,那么区别在哪里? 外部 imx-sm 源和 BCTRL 寄存器配置如何影响 A55P 混合电源的启动?具体来说,是否存在 AHAB/ELE 容器签名或配置元数据会影响 A55 平台组合是否能够启动? 观察到的 函数状态 模式(PSW/SSAR/A55_HDSK/SYSMAN) 向上, RST/ISO/MEM 向下(而非向前)已知的签名?从该状态到下一个预期转变是什么?驱动这种转变的因素是什么? 为什么会明确地掉电 请求也一直无法完成吗? 这似乎是最有力的线索——必须具备哪些前提条件 SRC_XSPR 回应 SLICE_SW_CTRL.PDN_SOFT 这个混音有什么特别之处吗? 除了 ERR053228 之外,是否存在已知的 i.MX95 B0 勘误会影响 A55P 混合电源时序? 参考资料中提到的 A55 平台组合是否需要任何初始化? mx95evk 流动但 不是 以生成的形式表达 config_*.h 文件——也就是说,自定义的基于 SMCT 的配置会默默省略的某些内容? 说明 PRO 板上没有 JTAG(没有接头),而且我也没有选择在 15x15 板上使用脆弱的 0.5 毫米测试焊盘。 以上所有诊断均通过SM自身的调试监视器(lm info, 犯错, btime, md),直接寄存器读取和示波器测量。 我已经实施了一个隔离修复方案(用有界等待替换了原来的无界等待)。 while (!SRC_MixPowerUpCompleted()) {;} 循环)以便故障现在可以优雅地降级为 LM1 = 已停用 而不是通过看门狗重置整个系统。如果需要,我很乐意单独分享。 Re: i.MX95: A55 never completes power-up or power-down — stalls identically on two different boards 请忽略以上帖子并关闭此工单……我刚用 Wrynose 重新编译了一个版本,它能用了!我之前的版本使用的是 whinlatter(选择它是因为 FRDM-IMX95 出厂时就预装了 whinlatter),但是那并没有成功。
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S32K3X4EVB-T172 Unable to Program using OpenSDA I have a fresh-out-the-box S32K3X4EVB-T172 Eval board. The S32 processor seems to be running some factory default code, but when I try to debug/reprogram using the on-board debugger (connected to my computer using USB) both the S32 and the on-board debugger go into reset. I am using the correct Power On/Plug in procedure as described by the S32K3X4EVB-T172 quick start guide. I also have installed the software and addons described there as well. Tried same process with a co-worker's S32K3X4EVB-Q172 and it worked just fine.\ Thanks in advance, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA 1. Please refer to the discussion: PEmicro Connection Assistant Issue on S32K3X4EVB-T172. Do the red LEDs D15(RST_OSDA) and D3(RESET_K3) remain lit, or do they flash periodically? Is your board experiencing the same issue as this customer?   2. Is FS26(U12) hot? 3. Did you follow the steps "3.2 Plug in the Power Supply" and then "3.3 Connect the Debugger Cable"? 4. Plug in the J40 micro-USB cable and observe the D14STATUS OSDA LED. If the D14 orange LED does not light up: Check whether the USB cable is a data cable, verify if the PC enumerates the OpenSDA device, and ensure the USB port and drivers are functioning correctly. Connecting the USB cable to the PC via a USB hub is not recommended. 5. The onboard debugger is provided by PEMicro, it is recommended to download the latest "USB Multilink Resources Installer" from the "Support & Downloads" category of the "Multilink Debug Probes". After installation, open PEFirmwareConfig.exe located in C:\PEMicro\Multilink_Resources to check the firmware version. My onboard debugger's firmware version is 10.98. What version is your board? If the version is too old, it is recommended to update. If the update fails, it is recommended to contact PEMicro technical support. check the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.png 6. Please use a multimeter in voltage mode or an oscilloscope to observe the voltage of P3V3_SDA (J34). S32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.png 7. The SDA_RST_TGTMCU is controlled by the output of the onboard debugger K26. If the SDA_RST_TGTMCU outputs a low level, both red LEDs D15 and D3 will light up. Please observe the SDA_RST_TGTMCU (J36) level using an oscilloscope. Is it always low, or is it periodically pulled low? Normally, when downloading a program or resetting the S32K3 via the onboard debugger, a 10ms low level should be observed in the SDA_RST_TGTMCU, causing red LEDs D15 and D3 to light up briefly. 8. Is it possible to debug the onboard S32K3 chip after connecting via J12 using an external debugger? Best Regards, Robin Re: S32K3X4EVB-T172 Unable to Program using OpenSDA I am not sure which version of the RTD Port_Example_S32K344 you are currently testing. However, I suggest setting J31 to positions 2-3 and trying again. Re: S32K3X4EVB-T172 Unable to Program using OpenSDA After some more testing: 5. I was able to update the onboard debugger firmware using the PEFirmwareConfig exe.  The behavior remains the same though when I try to debug/program. 6. J34 voltage is at 3.25V when USB is plugged in. 7. J36 is high until I try to debug/program. At which point it goes low and stays low until the micro USB is disconnected. Still waiting on an adapter for point 8.  It should arrive today. Thank you, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA How can I determine what the version of the example project is? I switched J31 to 2-3. Same behavior. Thanks, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Please take a photo of the S32K3X4EVB-T172 board after connecting the external 12V power supply to J14 and plugging in the USB cable; the image must be clear enough to show the jumper settings and which LEDs are lit. Please record a video of the S32DS interface, starting from when you click the debug button and continuing until the error screen appears. This will allow me to see exactly what is happening and help troubleshoot the issue quickly. If you cannot record a video of the operations performed in S32DS on the screen, could you take a few screenshots to show the error? Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Hello Robin, 1. Once I attempt to debug/program, both LEDs (D15 and and D3) remain lit. They do not flash.  I believe my board is experiencing the same issue as the customer in https://community.nxp.com/t5/S32K/PEmicro-Connection-Assistant-Issue-on-S32K3X4EVB-T172/m-p/2252525, but it seems he bypassed his issue by purchasing another EVB, which is unfortunate. 2. no 3. yes 4. D14 does light up when I plug in the micro-USB cable.  Device Manager shows "OpenSDA - CDC Serial Port (http://www.pemicro.com/opensda)".  There is no USB hub in the system, and my PC+cable can program other S32K344 EVBs using S32DS.  The issue seems tied specifically to this board. 5-7.  Give me some time to run these down.  I will respond shortly. 8. I have yet to try to JTAG directly as I am waiting on an adapter so I can interface with J12. Thank you for your detailed response, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Please check whether the jumper settings match those described in "3.1 Set Up Jumpers in the S32K3X4EVB-T172 Evaluation Board." Is the input voltage for J14 12V? Which project did you debug? Would it be possible for you to record a video of the debugging process and share it with me? Re: S32K3X4EVB-T172 Unable to Program using OpenSDA The jumper settings do match. J16 is showing 12V (seemed easier than measuring the jack directly). I am using the project Port_Example_S32K344 as recommended in the quick start guide.  I don't think I will be able to video. -Tobiah
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Anyone using TapLinx? Is anyone using the TapLinx SDK from NXP to interface with MIFARE cards? I’m interested in some minimal console app examples. The sample app is a bit of a pain to get working as it a GUI app with a whole bunch of features. I’d like to locate some minimal console apps that just read/write some data to a card, authenticate, etc. Even better if they were Kotlin examples, but Java us fine too. Getting Started Re: Anyone using TapLinx? Hello @reid88  The TapLinx SDK supports MIFARE DESFire, Plus, Classic, Ultralight, NTAG, and more. You can check the design resources by going: TapLinx SDK for MIFARE, NTAG, ICODE and UCODE | NXP Semiconductors
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S32K358 快速备用 你好, 我想测试一下S32K358的快速待机功能。我在 S32DS 中创建了一个 IP 层演示,其中程序在启动后 5 秒进入快速待机状态,并在 3 秒后通过 RTC-API 唤醒。这样操作没有任何问题。 然后我参考了这个项目,配置了一个 EB 项目来创建一个 MCAL 层演示,但是失败了。快速待机 3 秒后,电流增大,这表明设备已唤醒,但并未进入主功能。连接 PE Micro 后,出现以下错误信息: 已收到中断命令。停止执行。 UsageFault:执行指令时使用了无效的 EPSR.T 或 EPSR.IT 字段。 总线故障:发生不精确(异步)数据访问错误。 硬故障:故障已升级为硬故障。 唤醒后的向量表如下所示: 1.png1.png PC寄存器为0x0。检查堆栈内容,可以看到已进入 FastWkup_EntryAddress,并且在跳转到 Reset_Handler 后发生 HardFault。 2.png2.png 3.png3.png 4.png4.png 如果我在 FastWkup_EntryAddress 中添加一个 while(1) 循环,则 HardFault 仍然会发生。 5.png5.png 如果我进入待机模式,它会…… 在该项目中,PMIC_PGOOD_HNDSHK_BYP 已启用。由于该板没有外部晶振(晶体振荡器),因此使用 FIRC 作为核心时钟。 S32K358 RTD6.0.0 S32DS3.6.3 EB29.0 BR, 杰森 Re: S32K358 FAST STANDBY 你好@Jason07 , 在快速待机唤醒时,sBAF 将 VTOR 设置为您的自定义向量表地址。 但是,您的向量表只定义了三个条目: 初始SP, 重置处理程序(FastWkup_EntryAddress), NMI 处理程序。 因此,HardFault 向量缺失。 当发生任何故障时,CPU 会获取未定义的 HardFault 处理程序地址,这可以解释观察到的 PC 值。 为了进一步调试此问题,请在向量表中添加一个合适的 HardFault 处理程序。一旦这些就位,就会调用处理程序而不是崩溃到 0x0,从而使您可以访问原始故障的堆叠 PC、LR 和可配置故障状态寄存器 (CFSR/BFAR)。 谢谢! BR,丹尼尔
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i.MX93 并行透传接口 您好, 我正在设计一块采用 i.MX93 (MIMX9332CVVXMAC) 的电路板,该电路板需要驱动一个带并行接口的 RGB 显示器。从配置工具中,数据位被标记为 data0-23,不参考 R、G、B 通道。我还查看了 evb FRDM 和 TM050RDH03-41,但遗憾的是,FRDM 的数据与配置工具中的数据相同,而 TM050RDH03-41 的原理图没有提供。 能否提供这样的原理图来确认引脚排列? 或者您能否确认 24 位数据可以在 R、G 和 B 通道之间自由复用? 谢谢! 恩里科 Re: i.MX93 parallel diaply interface 您好, 感谢您对恩智浦半导体产品的关注, 如果您对完整的原理图感兴趣,请参阅 TM050RDH03-41 显示连接器原理图,请提交技术案例。 JosephAtNXP_0-1789574219944.pngJosephAtNXP_0-1789574219944.png 此致
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MRF13750H AWRモデル こんにちは、 公式の設計ファイルを使って、Cadence AWR Microwave OfficeにMRF13750Hトランジスタモデルをインポートしようとしています。 設計キットとトランジスタモデルの両方をダウンロードした後、モデルを開こうとするとエラーが発生します。エラーメッセージのスクリーンショットを添付しました。 Luis_V_0-1789581238483.pngLuis_V_0-1789581238483.png すでにCadenceの技術サポートには連絡済みです。彼らのチームもモデルのダウンロードと開封を試み、まったく同じ問題に遭遇したと確認しました。 これらのファイルを確認して、どう解決すればいいか教えていただけますか? 最高、 ルイス・V. RF Re: MRF13750H AWR MODEL こんにちは、Luis_Vさん 良い一日! エラーの原因は互換性の問題です。あなたがインストールしようとしているモデルはかなり古く、以前のAWR Design Environment用に設計されています。現時点では、ソフトウェアの新しいバージョン向けにアップデートする計画はありません。 このモデルを使う必要がある場合、最も実用的な解決策は、2015年頃の古いバージョン(例えばAWR v11やv12)を導入することです。これはこのモデルと互換性があります。これにより、GetIAwrUserIO DLLエラーに遭遇することなく作業を進めることができるはずです。 ご迷惑をおかけして申し訳ありません。 この情報がお役に立てば幸いです。他に何かご不明な点がありましたら、お気軽にお問い合わせください。 良い一日をお過ごしください。幸運を祈ります。 Re: MRF13750H AWR MODEL こんにちは、ラファさん。 Cadenceに連絡して、古いバージョンのAWRを提供できるか確認しています。その間に、MRF13750H-915MHzボードを設計したエンジニアか、数値集めを手伝ってくれる方をつなげていただけますか?NXPの製品を使っていて、使う必要があります。 さらに、先ほどADS/AWRを開いてT字の不連続点や斜めの曲げ、開いた端の効果などを確認できるとおっしゃっていましたね。マイクロストリップの寸法や特性を確認するために、ウィンドウのスクリーンショットを送ってもらえますか?Cadenceの出番を待つ間に、ソースと負荷インピーダンスの値を調べるために負荷プル解析をしていただけるとありがたいです。 最高、 ルイス・ビジャヌエバ
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SE052 adoption questions: EdDSA/X25519 availability, non-FIPS variant roadmap, applet limits Hello, We currently use the SE050E2 (applet 7.2.0, die reports "SE051" in the ATR, AppletConfig 0x3F9F) in two designs, and we are evaluating the SE052 for the next hardware revision. Before committing, we read the SE052 data sheet (Rev 1.5), AN14028, AN14277, AN13904, AN12543 (Rev 4.5) and the Plug & Trust MW documentation (AN13030 Rev 2.7), and a few points block the decision. We would appreciate clarification. Our two use cases: A mesh/transport node (LoRa + Ethernet) whose identity is an X25519 + Ed25519 key pair generated and used inside the SE (ECDH via ECDHGenerateSharedSecret on ID_ECC_MONT_DH_25519, signing via EdDSASign with ED25519PURE_SHA_512). A signing device using secp256k1 ECDSA (pre-computed digest) and Ed25519 for different targets, with a UserID-protected session. Questions: Variants. AN14277 states that SE052F (OEF B501, FIPS 140-3) is "the only released variant", and its GetInfo shows WithOut EDDSA / WithOut DH_MONT. Is there any roadmap for a non-FIPS SE052 configuration (equivalent to SE050E / SE051 with CONFIG_EDDSA and CONFIG_DH_MONT enabled)? If so, approximate timeframe and OEF? Enabling EdDSA / Montgomery DH on SE052F. Since SetAppletFeatures requires RESERVED_ID_FEATURE (0x7FFF0204), which is NXP-owned, is there any customer path to enable Ed25519/X25519 on SE052F (e.g. a custom configuration through EdgeLock 2GO), accepting loss of FIPS-approved mode? Or does the FIPS OS build block those curves regardless of the applet feature bits? FIPS and EdDSA. FIPS 186-5 approves EdDSA. Is there a plan for a future SE052 applet/OS version (via SEMS Lite or a new OEF) that supports Ed25519 and X25519 while remaining FIPS 140-3 approved? APDU throughput limit. AN14028 §2.3.1 / AN13904 §8.4 describe the 1,000,000 APDU / 34-day limit (SW 66A6) and the FIPS self-test every 500,000 APDUs. Are these tied to the FIPS certification only, and would they be absent in a hypothetical non-FIPS SE052 variant? Is a reset via RST_N enough to clear the counter with no NVM impact? Applet feature roadmap for signing use cases. We could not find any of the following in AN12543 Rev 4.5. Are any planned for the 7.2.x line or a future applet? Hardened child-key derivation inside the SE (scalar addition mod n, BIP32-style), so derived private keys never leave the chip. Schnorr signatures (BIP340) on secp256k1. Deterministic ECDSA nonces (RFC 6979) and/or low-S normalisation. Pre-hashed Ed25519 (Ed25519ph) or a streaming EdDSA mode, so messages longer than the IFSC (0xFE) do not depend on T=1 chaining. UserID behaviour on applet 7.2.22. On SE050E2 (7.2.0) we observed that a UserID object whose TAG_MAX_ATTEMPTS is exhausted can no longer be deleted (DeleteSecureObject → 6986 even over Platform SCP03), and the attempts counter attribute always reads 0. AN14028 Table 1 says the attributes now show the maximum number of attempts. On 7.2.22: (a) is the remaining/used counter reported? (b) can an exhausted UserID be deleted by the SCP03 platform user? ECDH NVM wear (applies to our current SE050E2 too). AN12543 §4.10.3 says ECDHGenerateSharedSecret on MONT_DH_25519 writes NVM on each call when the public key is passed as a byte array (TAG_2), but not when passed via a transient ECPublicKey object (TAG_3). Can you confirm this also holds for SE050E with applet 7.2.0, and that updating the transient object's content with WriteECKey between calls does not itself write NVM? Longevity. Is the SE050E2 covered by NXP's product longevity program, and is there any planned EOL? This decides whether we stay on SE050E2 for the next revision. Thank you in advance. SE050 Re: SE052 adoption questions: EdDSA/X25519 availability, non-FIPS variant roadmap, applet limits Hi @cvaldess , Thank you for the reaching out! Let me work through each one. Q1 — Non-FIPS SE052 variant roadmap As you correctly identified, SE052F (OEF B501) is currently the only released SE052 variant, and its AppletConfig 0x26F2 does not include EdDSA or DH_MONT. We cannot share specific roadmap timelines on a public forum, but I recommend reaching out to your local Disti/NXP FAE to discuss your requirements under NDA, where roadmap details can be addressed directly. Q2 — Enabling EdDSA / Montgomery DH on SE052F There is no customer path to enable these algorithms on SE052F. RESERVED_ID_FEATURE (0x7FFF0204) is an NXP-owned object and cannot be modified or deleted by customers — EdgeLock2GO is not a mechanism for enabling it. More fundamentally, the SE052F FIPS 140-3 OS build excludes Twisted Edwards (Ed25519) and Montgomery (Curve25519) curve support at the OS/hardware level as part of the certified configuration. Even loading a custom applet via SEMS Lite cannot re-enable curves absent from the OS layer — and doing so would in any case render the module non-FIPS compliant, as AN14277 explicitly notes. Q3 — FIPS 140-3 + EdDSA in a future SE052 applet/OEF FIPS 186-5 (Feb 2023) does approve EdDSA, so the standards basis exists. However, any SE052 OEF supporting Ed25519/X25519 under a new FIPS 140-3 certificate would require a full CMVP recertification submission. We are not in a position to confirm plans or timelines on a public forum. Please check with your local Disti/NXP FAE for an NDA conversation on this point. Q4 — APDU throughput limit (SW 66A6) Yes, the 1,000,000-APDU / 34-day counter and the 500,000-APDU periodic self-test are FIPS 140-3 compliance requirements specific to SE052F. A hypothetical non-FIPS SE052 variant would not be subject to these constraints. Regarding reset: a T=1oI2C chip reset (RST_N toggle or power cycle) is the documented recovery path. The APDU counter is a session-resident in-RAM value — it is cleared by the cold reset with no NVM write. The Plug & Trust MW includes an apdu_throughput_limit demo that demonstrates exactly this recovery using phNxpEse_reset . For your mesh/transport node use case, at ~340 APDUs/minute sustained this limit should not be a concern in practice, but please ensure your host driver handles SW_66A6 gracefully with an automatic reset. Q5 — Applet feature roadmap (BIP32, Schnorr, RFC 6979, Ed25519ph) None of the features you listed — BIP32 hardened child-key derivation on-chip, Schnorr/BIP340, deterministic ECDSA nonces (RFC 6979), low-S normalisation, or Ed25519ph — appear in AN12543 Rev 4.5 or any current SE05x documentation, and there are no public announcements for these in the 7.2.x line. I'd encourage you to submit a formal product enhancement request via your local Disti/NXP FAE so these can be tracked by our product team. A note on the T=1 chaining concern for Ed25519: the applet does support multi-block T=1 chaining for APDU data beyond IFSC (0xFE), so message length is handled at the transport layer and is not a functional restriction on EdDSA operations. Q6 — UserID behaviour on applet 7.2.22 (a) Counter readability: The GetAttributes response returns the configured TAG_MAX_ATTEMPTS value (the maximum), not the remaining count. The internal decrement counter is not exposed as a directly readable attribute in the current applet version. (b) Deleting an exhausted UserID over SCP03: The 6986 error on deletion of a locked UserID that you observed on 7.2.0 is a known limitation. AN13904 does not explicitly document a change to this behaviour for 7.2.22 in the context of Platform SCP03 deletion. I recommend verifying this directly on the SE052F evaluation hardware (or an SE051 sample running 7.2.22). As a workaround, a Factory Reset via RESERVED_ID_FACTORY_RESET over Platform SCP03 is the confirmed path if a locked UserID blocks object management — though this clears all user objects, so object layout planning matters here. Q7 — ECDH NVM wear (SE050E with applet 7.2.0) Confirmed. AN12543 explicitly states that ECDHGenerateSharedSecret on ID_ECC_MONT_DH_25519 causes NVM writes per call only when the public key is passed as a byte array (TAG_2). When the public key is passed via a transient ECPublicKey object (TAG_3), no NVM write occurs. This behaviour applies to SE050E with applet 7.2.0, as the SE050E2 uses the same 7.x applet generation (the SE051 die and applet family, as your GetInfo ATR confirms). WriteECKey on a transient object writes to SRAM only — there is no NVM wear from updating the transient object's content between calls. The recommended pattern for your node is: allocate one persistent transient ECPublicKey at startup, call WriteECKey (SRAM only) before each ECDH operation, then call ECDHGenerateSharedSecret with TAG_3 referencing that transient object. This fully avoids per-call NVM wear. Q8 — SE050E2 product longevity The SE050E2 was launched in 2022. NXP's Product Longevity Program commits to a minimum of 10 or 15 years' availability from launch date for enrolled products. For the definitive enrollment status and longevity horizon for SE050E2, please check the NXP Product Longevity page (sign-in required for the full table) or ask your NXP FAE to confirm. Overall recommendation for your two use cases Given that your designs rely on Ed25519 (EdDSASign) and X25519 (ECDHGenerateSharedSecret on MONT_DH_25519), SE052F does not currently satisfy your cryptographic requirements. The SE050E2 / SE051 family remains the appropriate choice until a SE052 variant with those algorithms is available. We recommend confirming SE050E2 longevity status with your NXP FAE and registering a product requirement for a non-FIPS SE052 equivalent. Hope this helps clarify the decision. Please let me know if you have follow-up questions. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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FRDM-IMX8MPLUSボード用のロボットエッジイメージ1.0.0を探しています みなさんこんにちは、 私はFRDM-IMX8MPLUSボード(IMX8MP-EVKではない)のRobotics Edge Image 1.0.0のリリースパッケージ。 IMX8MP-EVKやIMX95EVK用のプリビルドイメージは見つかりますが、FRDM-IMX8MPLUSについては何も見つかりませんでした。このボードはサポートされています(https://mcuxpresso.nxp.com/RoboticsEdgePlatform/latest/html/gsd/prebuilt-images.html) ソース(Yocto)からビルドするのは本当に面倒で、約1TBの容量を消費し、途中で多くのエラーが発生します。 良い回答が得られることを願っています。 よろしくお願いいたします。 Re: Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board すみません、FRDM-IMX8MPLUSファイルはIMX8M-EVKのzipファイルにまとめられています。 名前は一つだが、宛先は二つの委員会だ。
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MRF13750H AWR 型号 你好, 我正在尝试使用贵公司网站上提供的官方设计文件,将 MRF13750H 晶体管模型导入 Cadence AWR Microwave Office。 下载完设计套件和晶体管模型后,尝试打开模型时出现错误。我已附上错误信息的截图。 Luis_V_0-1789581238483.pngLuis_V_0-1789581238483.png 我已经联系了Cadence的技术支持。他们的团队也尝试下载并打开该模型,并确认遇到了完全相同的问题。 请您核实这些文件,并告知我如何解决这个问题? 最好的, 路易斯·V. 射频 Re: MRF13750H AWR MODEL 你好 Luis_V 再会! 该错误是由于兼容性问题导致的。您尝试安装的模型比较老旧,是为早期版本的 AWR 设计环境设计的。目前尚无计划对其进行更新以适应新版本的软件。 如果您需要使用此型号,最实用的解决方案是安装一个较旧版本的 AWR,例如 2015 年左右的版本(例如 AWR v11 或 v12),该版本与此型号兼容。这样应该可以避免遇到 GetIAwrUserIO DLL 错误。 对于可能由此导致的不便,我们深感抱歉。 希望这些信息对您有所帮助,如果您还需要其他帮助,请告诉我。 祝你今天过得愉快,一切顺利。 Re: MRF13750H AWR MODEL 你好,拉法, 我正在联系 Cadence 公司,看看他们是否可以提供旧版本的 AWR。与此同时,您能否帮我联系一下设计 MRF13750H-915MHz 板的工程师,或者其他可以帮我收集一些数据的人?我这里有NXP的这款产品,我们需要用它。 此外,您之前提到过您可以在您那边打开 ADS/AWR 来查看 T 型接头不连续性、斜接弯头、开路效应等。您能否给我发送一个窗口截图,以便我检查微带线的尺寸和特性?在等待 Cadence 的回复期间,如果您能运行负载牵引分析来找出源阻抗和负载阻抗值,我将不胜感激。 最好的, 路易斯·维拉纽瓦
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