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MCXW23x — BLE connection drops repeatedly when using FRO32K MCXW235B BLE connection drops repeatedly, `disconnect reason=0x08` (LL supervision timeout), consistently a few seconds after connect  Hardware constraint (fixed, not changeable on this design):** the custom board does **not** populate a 32.768kHz crystal on `XI32K`/`XO32K` — both pins are left open. The board only has a 32MHz crystal on `XI32M`/`XO32M` Board Design
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MCXW23x — FRO32K使用時にBLE接続が繰り返し切断される MCXW235B BLE接続が繰り返し切断される。`切断理由=0x08`(LL監視タイムアウト)、接続後数秒で必ず切断される。 ハードウェア制約(この設計では固定、変更不可):** カスタムボードは**XI32K/'XO32K'の32.768kHzクリスタルを**埋めていません** — 両方のピンが開いたままです。このボードには、`XI32M`/`XO32M`にのみ32MHzの水晶発振子が搭載されています。 ボード設計
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MCXW23x — 使用 FRO32K 时 BLE 连接反复断开 MCXW235B BLE 连接反复断开,断开原因为 `0x08`(LL 监控超时),每次连接后几秒钟都会断开。 硬件限制(此设计中固定且不可更改):** 定制板** 未** 在 `XI32K`/`XO32K` 上安装 32.768kHz 晶振 — 两个引脚均未连接。该电路板仅在 `XI32M`/`XO32M` 上配备了 32MHz 晶振。 电路板设计
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TEA1716 计算文件 您好,我正在寻找TEA1716 IC的Excel计算文件,类似于TEA系列其他芯片开发工具中提供的计算文件。我使用的是TEA1716DB1255开发板,并按照相关文档进行操作,但我也想获取该计算文件(如果存在的话)。谢谢您的回复,祝您一切顺利! 电源解决方案 Re: TEA1716 сalculation file 你好, TEA1716 有一个基于 Excel 的计算表(“TEA1716 计算表草案 V1_4”),它取代了不再运行的原始在线设计工具。请查收附件。 除计算表外,您完成 TEA1716DB1255 工作所需的关键文件如下: AN11179 — 详细设计指南,包括计算示例 UM10557 — TEA1716DB1255 演示板文档 BRs,托马斯
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オンチップセキュアNVM(S32K314) HSE FW install for S32K3xx.pdfに記載されているセキュアNVMマッピング(FULL_MEM)は以下のとおりです。 HSEデータフラッシュは160KB、APPデータフラッシュは88KB、合計:160KB+88KB=248KB luojing_0-1789619650388.png羅京_0-1789619650388.png luojing_1-1789619740147.pngluojing_1-1789619740147.png ただし、S32K3XXRM.pdfに記載されているdflashの割り当ては以下のとおりです。 dflashの合計サイズは128KBです。 luojing_2-1789619854070.pngluojing_2-1789619854070.png なぜ2つの文書に記載されているDflashのサイズが異なるのですか? 注:私はHSEファームウェアバージョンHSE_FW_S32K344_0_2_55_0_S2502.exeを使用しています。 luojing_3-1789620886731.pngluojing_3-1789620886731.png Re: sRe: On-chip secure NVM (S32K314) これらの情報はすべてHSE-Bファームウェアリファレンスマニュアルに記載されています。 これは安全なファイルなので、すでに行ったことがない限り、以下の手順に従う必要があります。 https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf より理解を深めるために、以下のリンクもご参照ください。 https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS Re: sRe: On-chip secure NVM (S32K314) S32K3xx 用の HSE FW インストールに関する PDF ファイルでは、HSE Pflash と dflash の範囲のみが指定されており、RAM の範囲は指定されていません。HSEが使用するRAMの範囲は? 開始地点の住所とサイズを教えてください。 それについて説明した特定の文書はありますか? Re: sRe: On-chip secure NVM (S32K314) セキュアデータフラッシュは、0x10016000 (FULL_MEMの場合) から始まり、168KB の容量を持ちます。これは全てのデリバティブ商品に共通する。 アプリケーションノートは最新ではありません。 Re: sRe: On-chip secure NVM (S32K314) luojing_0-1789654909700.png羅京_0-1789654909700.png HSE(FULL UMEM)のDflashサイズが160KBというのは間違いでしょうか?128KB-88KB=40KBになるべきでしょうか? sRe: On-chip secure NVM (S32K314) 以下に説明します。 davidtosenovjan_0-1789654479428.pngdavidtosenovjan_0-1789654479428.png
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S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed Hello NXP support, My NXP account holds valid entitlement for S32DS v3.5, but the generated license expired. Fulfillment ID: 113445398 IDE: S32 Design Studio for S32 Platform v3.5 License Expiry: Aug 8, 2026 Entitlement Expiry: Sep 16, 2030 Machine ID: A5883F5CCBF60C6BECC55C5A0CC9D1C68DA192AD Current situation: 1. The license management page has no EXTEND button. 2. Return license is disabled, cannot release this fulfillment. 3. The entitlement is still valid until Sep 16, 2030. Could you help refresh this fulfillment license to entitlement expiry date Sep 16,2030? I have attached the screenshot of license list for your reference. Thanks. LicenseNotAllow.png Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed Thank you very much for your help. I have reactivated S32DS successfully. Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed Hi,  I returned old licenses, you should be able activate S32DS again with your old code. 
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关于 AFM907N PA 如果有的话,能否分享一下针对 915MHz 频率范围的调谐布局? Re: Regarding AFM907N PA 你好 lavanyaemsec 再会! 很遗憾地通知您,我们没有 915 MHz 的参考布局图;最接近的应该是…… AFM907N 760-870 MHz 参考电路设计文件 可以在AFM907N官方页面的设计资源部分找到。 对于可能由此导致的不便,我们深感抱歉。 祝你今天过得愉快,一切顺利。
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S32DS v3.5 许可证已过期,授权仍然有效,没有“延长”按钮,且不允许退货。 Hello NXP support, My NXP account holds valid entitlement for S32DS v3.5, but the generated license expired. Fulfillment ID: 113445398 IDE: S32 Design Studio for S32 Platform v3.5 License Expiry: Aug 8, 2026 Entitlement Expiry: Sep 16, 2030 Machine ID: A5883F5CCBF60C6BECC55C5A0CC9D1C68DA192AD Current situation: 1. The license management page has no EXTEND button. 2. Return license is disabled, cannot release this fulfillment. 3. The entitlement is still valid until Sep 16, 2030. Could you help refresh this fulfillment license to entitlement expiry date Sep 16,2030? I have attached the screenshot of license list for your reference. Thanks. LicenseNotAllow.png Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed 非常感谢您的帮助。我已经成功重新激活了S32DS。 Re: S32DS v3.5 license expired, entitlement valid, no EXTEND button and Return not allowed 你好, 我已经退回了旧的许可证,您应该可以使用之前的激活码再次激活S32DS。
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Question regarding removal of W8997 firmware from imx-firmware Hello NXP team, I’m contacting you regarding the following commit in the imx-firmware repository: “Remove SD/PCIE W8997 support from BSP from 26Q1 onwards” Could you please clarify whether the W8997 firmware was only removed from the standard  imx-firmware package or wheter support for these devices has been discontinued entierly ?  We can retrieve the last W8997 firmware files from the Git history, so our main question is about the recommended way to maintain W8997 support while continuing to use the latest imx-firmware releases. Is it supported to install the latest imx-firmware package and add the W8997 firmware files from the last release that contained them? If so, is there any recommended procedure or packaging approach to do this cleanly and avoid conflicts with future imx-firmware updates? Our goal is to keep systems on the latest i.MX firmware package while preserving support for older deployed hardware based on the 88W8997. Best regards, Antoine Gennart
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关于从 imx-firmware 中移除 W8997 固件的问题 您好,NXP团队, 我联系您是关于imx-firmware仓库中的以下提交: “从 26 年第一季度开始,从电路板支持包中移除 SD/PCIE W8997 支持” 请问W8997固件只是从标准imx固件包中移除,还是已经完全停止对这些设备的支持? 我们可以从 Git 历史记录中检索到最新的 W8997 固件文件,因此我们的主要问题是,在继续使用最新的 imx-firmware 版本的同时,保持对 W8997 支持的推荐方法是什么。 是否支持安装最新的 imx-firmware 软件包,并添加包含这些文件的上一版本中的 W8997 固件文件? 如果是这样,是否有推荐的步骤或打包方法可以干净利落地完成此操作,并避免与未来的 imx 固件更新发生冲突? 我们的目标是在保持对基于 88W8997 的旧已部署硬件的支持的同时,使系统保持最新的 i.MX 固件包。 顺祝商祺! 安托万·热纳尔
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Seeking guidance: se05x_Minimal fails in OP-TEE environment Hello NXP Community, I am attempting to run se05x_Minimal on our target board running Linux with OP-TEE. Following the solution recommended in this community post (How to integrate Plug and Trust MW into OP-TEE), we built the environment accordingly. In particular, for Step 2, we configured the setup without enabling "keep CAAM enabled". As a result of this configuration, the I2C bus connected to SE05x is managed by OP-TEE (Secure World), and the standard Linux I2C device node /dev/i2c-1 is not visible/available in the Normal World (Linux). When executing `./se05x_Minimal` directly from the Linux user-space console, we encounter the following error: App :INFO :Running ./se05x_Minimal App :INFO :If you want to over-ride the selection, use ENV=EX_SSS_BOOT_SSS_PORT or pass in command line arguments. App :INFO :PlugAndTrust_v04.07.01_20250519 App :INFO :Using default PlatfSCP03 keys. You can use keys from file using ENV=EX_SSS_BOOT_SCP03_PATH smCom :ERROR:opening failed... Failed to open the i2c bus: No such file or directory smCom :INFO :Pass i2c device address in the format : . smCom :INFO :Example ./example /dev/i2c-1:0x48 OR ./example /dev/i2c-1 smCom :ERROR:phPalEse_i2c_open_and_configure Failed retry smCom :ERROR:I2C init Failed: retval d smCom :ERROR:phPalEse_Init Failed smCom :ERROR: Failed to create physical connection with ESE sss :ERROR:SM_I2CConnect Failed. Status 7012 App :ERROR:sss_session_open failed App :ERROR:ex_sss_session_open Failed App :ERROR:!ERROR! ret != 0. Environment & Hardware Setup: Evaluation Board: MCIMX8M-WEVK (i.MX 8M Dual/Quad) Secure Element Board: OM-SE051ARD Secure Element: SE05x (Plug & Trust MW v04.07.01) OS: Linux (Normal World) + OP-TEE (Secure World) Middleware Options (CMake): -DPTMW_Host=iMXLinux, -DPTMW_SMCOM=T1oI2C Note: se05x_Minimal works fine if Linux kernel-space direct I2C (/dev/i2c-1) is enabled. It appears smCom is still attempting to open the physical Linux I2C device (/dev/i2c-X), which no longer exists in our Normal World environment. Could you please provide instructions on what we need to do or modify so that se05x_Minimal can run successfully in this setup? SE050 Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment @Kan_Li  Thank you very much for your detailed explanation and the C code samples. Following your guidance, we implemented a C application using the standard PKCS#11 API (libckteec.so.0) under Option 1 (OP-TEE exclusive I2C setup). All operations -- including key generation, AES encrypt/decrypt, RSA sign/verify, and RSA encrypt/decrypt -- are now working completely as expected. We appreciate your support in resolving this issue. Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment Hi @Uc_S , This is an excellent and important question. The short answer is: In Option 1 (OP-TEE exclusive I2C), the Plug & Trust MW SSS APIs cannot be used from Linux userspace directly. You must use the standard PKCS#11 C API via libckteec.so . Below is a detailed explanation and complete C code samples for all the operations you need. Why SSS APIs Cannot Be Used in This Setup The Plug & Trust MW SSS APIs ( sss_session_open , sss_key_store_set_key , sss_asymmetric_sign_digest , etc.) rely on a transport layer to communicate with the SE051. All supported transports ( T1oI2C , JRCP_V1_AM , etc.) ultimately require either Linux I2C access or a proxy server — neither of which is available when OP-TEE exclusively owns the I2C bus. The correct path in the OP-TEE exclusive setup is: Your C App → PKCS#11 C API (cryptoki.h) → libckteec.so → OP-TEE PKCS#11 TA → SE051 libckteec is provided by optee-client and implements the Cryptoki interface with the OP-TEE PKCS#11 TA as its backend. The TA in turn routes crypto operations to SE051 via OP-TEE's native I2C driver. Required Headers and Linking #include /* Standard Cryptoki header — from optee-client or OpenSC */ Compile and link: gcc -o my_app my_app.c -ldl # Or link directly: gcc -o my_app my_app.c /usr/lib/libckteec.so.0 At runtime, set the module path if using dynamic loading: #define PKCS11_MODULE "/usr/lib/libckteec.so.0" Initialization and Token Setup (call once at startup) #include #include #include #define CHECK_RV(rv, msg) \ if ((rv) != CKR_OK) { fprintf(stderr, "%s failed: 0x%lX\n", (msg), (rv)); goto cleanup; } /* User PIN — must match what was set with pkcs11-tool --init-pin */ static CK_UTF8CHAR user_pin[] = "1234"; static CK_ULONG user_pin_len = 4; CK_FUNCTION_LIST *p11 = NULL; /* Global function list pointer */ CK_SESSION_HANDLE session = CK_INVALID_HANDLE; int pkcs11_init(void) { CK_RV rv; CK_ULONG slot_count = 0; CK_SLOT_ID slot_id; CK_SLOT_ID slot_list[8]; /* Load function list — if using dynamic linking, use C_GetFunctionList() */ rv = C_Initialize(NULL_PTR); CHECK_RV(rv, "C_Initialize"); /* Get available slots */ rv = C_GetSlotList(CK_TRUE, NULL_PTR, &slot_count); CHECK_RV(rv, "C_GetSlotList (count)"); rv = C_GetSlotList(CK_TRUE, slot_list, &slot_count); CHECK_RV(rv, "C_GetSlotList"); slot_id = slot_list[0]; /* Use first slot — OP-TEE PKCS#11 TA */ /* Open a read-write session */ rv = C_OpenSession(slot_id, CKF_SERIAL_SESSION | CKF_RW_SESSION, NULL_PTR, NULL_PTR, &session); CHECK_RV(rv, "C_OpenSession"); /* Login as normal user */ rv = C_Login(session, CKU_USER, user_pin, user_pin_len); CHECK_RV(rv, "C_Login"); return 0; cleanup: return -1; } void pkcs11_cleanup(void) { C_Logout(session); C_CloseSession(session); C_Finalize(NULL_PTR); } Operation 1: Generate an RSA Key Pair and Store in SE051 int generate_rsa_keypair(CK_OBJECT_HANDLE *pub_key, CK_OBJECT_HANDLE *priv_key) { CK_RV rv; CK_MECHANISM mech = { CKM_RSA_PKCS_KEY_PAIR_GEN, NULL_PTR, 0 }; CK_ULONG key_bits = 2048; CK_BYTE pub_exponent[] = { 0x01, 0x00, 0x01 }; /* 65537 */ CK_BBOOL ck_true = CK_TRUE; CK_BBOOL ck_false = CK_FALSE; /* Key ID stored in SE051 NVM — choose a unique 4-byte ID */ CK_BYTE key_id[] = { 0x10, 0x10, 0x10, 0x10 }; CK_ATTRIBUTE pub_tmpl[] = { { CKA_MODULUS_BITS, &key_bits, sizeof(key_bits) }, { CKA_PUBLIC_EXPONENT, pub_exponent, sizeof(pub_exponent) }, { CKA_VERIFY, &ck_true, sizeof(ck_true) }, { CKA_ENCRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_ID, key_id, sizeof(key_id) }, }; CK_ATTRIBUTE priv_tmpl[] = { { CKA_SIGN, &ck_true, sizeof(ck_true) }, { CKA_DECRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_SENSITIVE, &ck_true, sizeof(ck_true) }, { CKA_EXTRACTABLE, &ck_false, sizeof(ck_false) }, { CKA_ID, key_id, sizeof(key_id) }, }; rv = C_GenerateKeyPair(session, &mech, pub_tmpl, sizeof(pub_tmpl) / sizeof(pub_tmpl[0]), priv_tmpl, sizeof(priv_tmpl) / sizeof(priv_tmpl[0]), pub_key, priv_key); CHECK_RV(rv, "C_GenerateKeyPair"); printf("RSA-2048 key pair generated. Private key stays in SE051 NVM.\n"); return 0; cleanup: return -1; } Operation 2: Generate an AES Key and Store in SE051 int generate_aes_key(CK_OBJECT_HANDLE *aes_key) { CK_RV rv; CK_MECHANISM mech = { CKM_AES_KEY_GEN, NULL_PTR, 0 }; CK_ULONG key_len = 32; /* 256-bit AES */ CK_BBOOL ck_true = CK_TRUE; CK_BBOOL ck_false = CK_FALSE; CK_BYTE key_id[] = { 0x20, 0x00, 0x00, 0x01 }; CK_ATTRIBUTE aes_tmpl[] = { { CKA_VALUE_LEN, &key_len, sizeof(key_len) }, { CKA_ENCRYPT, &ck_true, sizeof(ck_true) }, { CKA_DECRYPT, &ck_true, sizeof(ck_true) }, { CKA_TOKEN, &ck_true, sizeof(ck_true) }, { CKA_SENSITIVE, &ck_true, sizeof(ck_true) }, { CKA_EXTRACTABLE, &ck_false, sizeof(ck_false) }, { CKA_ID, key_id, sizeof(key_id) }, }; rv = C_GenerateKey(session, &mech, aes_tmpl, sizeof(aes_tmpl) / sizeof(aes_tmpl[0]), aes_key); CHECK_RV(rv, "C_GenerateKey (AES)"); printf("AES-256 key generated and stored in SE051.\n"); return 0; cleanup: return -1; } Operations 3 & 4: AES-CBC Encrypt / Decrypt int aes_encrypt(CK_OBJECT_HANDLE aes_key, const CK_BYTE *plaintext, CK_ULONG plaintext_len, CK_BYTE *ciphertext, CK_ULONG *ciphertext_len) { CK_RV rv; CK_BYTE iv[16] = { 0 }; /* All-zero IV for example; use a random IV in production */ CK_MECHANISM mech = { CKM_AES_CBC_PAD, iv, sizeof(iv) }; rv = C_EncryptInit(session, &mech, aes_key); CHECK_RV(rv, "C_EncryptInit"); rv = C_Encrypt(session, (CK_BYTE *)plaintext, plaintext_len, ciphertext, ciphertext_len); CHECK_RV(rv, "C_Encrypt"); return 0; cleanup: return -1; } int aes_decrypt(CK_OBJECT_HANDLE aes_key, const CK_BYTE *ciphertext, CK_ULONG ciphertext_len, CK_BYTE *plaintext, CK_ULONG *plaintext_len) { CK_RV rv; CK_BYTE iv[16] = { 0 }; /* Must match the IV used for encryption */ CK_MECHANISM mech = { CKM_AES_CBC_PAD, iv, sizeof(iv) }; rv = C_DecryptInit(session, &mech, aes_key); CHECK_RV(rv, "C_DecryptInit"); rv = C_Decrypt(session, (CK_BYTE *)ciphertext, ciphertext_len, plaintext, plaintext_len); CHECK_RV(rv, "C_Decrypt"); return 0; cleanup: return -1; } Operations 5 & 6: RSA Sign (private key stays in SE051) and Verify int rsa_sign(CK_OBJECT_HANDLE priv_key, const CK_BYTE *data, CK_ULONG data_len, CK_BYTE *signature, CK_ULONG *sig_len) { CK_RV rv; /* SHA256-PKCS1v1.5 — SE051 computes SHA-256 digest internally then signs */ CK_MECHANISM mech = { CKM_SHA256_RSA_PKCS, NULL_PTR, 0 }; rv = C_SignInit(session, &mech, priv_key); CHECK_RV(rv, "C_SignInit"); rv = C_Sign(session, (CK_BYTE *)data, data_len, signature, sig_len); CHECK_RV(rv, "C_Sign"); printf("RSA signature generated (%lu bytes). Private key never left SE051.\n", *sig_len); return 0; cleanup: return -1; } int rsa_verify(CK_OBJECT_HANDLE pub_key, const CK_BYTE *data, CK_ULONG data_len, const CK_BYTE *signature, CK_ULONG sig_len) { CK_RV rv; CK_MECHANISM mech = { CKM_SHA256_RSA_PKCS, NULL_PTR, 0 }; rv = C_VerifyInit(session, &mech, pub_key); CHECK_RV(rv, "C_VerifyInit"); rv = C_Verify(session, (CK_BYTE *)data, data_len, (CK_BYTE *)signature, sig_len); if (rv == CKR_OK) { printf("Signature verification: SUCCESS\n"); return 0; } else if (rv == CKR_SIGNATURE_INVALID) { printf("Signature verification: INVALID\n"); return 1; } CHECK_RV(rv, "C_Verify"); cleanup: return -1; } Operations 7 & 8: RSA Encrypt / Decrypt int rsa_encrypt(CK_OBJECT_HANDLE pub_key, const CK_BYTE *plaintext, CK_ULONG plaintext_len, CK_BYTE *ciphertext, CK_ULONG *ciphertext_len) { CK_RV rv; /* RSA-OAEP with SHA-256 — recommended over PKCS1 v1.5 for new designs */ CK_RSA_PKCS_OAEP_PARAMS oaep_params = { .hashAlg = CKM_SHA256, .mgf = CKG_MGF1_SHA256, .source = CKZ_DATA_SPECIFIED, .pSourceData = NULL, .ulSourceDataLen = 0 }; CK_MECHANISM mech = { CKM_RSA_PKCS_OAEP, &oaep_params, sizeof(oaep_params) }; rv = C_EncryptInit(session, &mech, pub_key); CHECK_RV(rv, "C_EncryptInit (RSA-OAEP)"); rv = C_Encrypt(session, (CK_BYTE *)plaintext, plaintext_len, ciphertext, ciphertext_len); CHECK_RV(rv, "C_Encrypt (RSA-OAEP)"); return 0; cleanup: return -1; } int rsa_decrypt(CK_OBJECT_HANDLE priv_key, const CK_BYTE *ciphertext, CK_ULONG ciphertext_len, CK_BYTE *plaintext, CK_ULONG *plaintext_len) { CK_RV rv; CK_RSA_PKCS_OAEP_PARAMS oaep_params = { .hashAlg = CKM_SHA256, .mgf = CKG_MGF1_SHA256, .source = CKZ_DATA_SPECIFIED, .pSourceData = NULL, .ulSourceDataLen = 0 }; CK_MECHANISM mech = { CKM_RSA_PKCS_OAEP, &oaep_params, sizeof(oaep_params) }; rv = C_DecryptInit(session, &mech, priv_key); CHECK_RV(rv, "C_DecryptInit (RSA-OAEP)"); rv = C_Decrypt(session, (CK_BYTE *)ciphertext, ciphertext_len, plaintext, plaintext_len); CHECK_RV(rv, "C_Decrypt (RSA-OAEP)"); printf("RSA decryption completed. Private key never left SE051.\n"); return 0; cleanup: return -1; } Accessing Existing Keys (without regenerating) If a key was previously generated and stored in SE051, retrieve it by CKA_ID without calling C_GenerateKey again: int find_key_by_id(CK_BYTE *key_id, CK_ULONG key_id_len, CK_OBJECT_CLASS obj_class, CK_OBJECT_HANDLE *handle) { CK_RV rv; CK_ULONG obj_count = 0; CK_ATTRIBUTE search_tmpl[] = { { CKA_CLASS, &obj_class, sizeof(obj_class) }, { CKA_ID, key_id, key_id_len }, }; rv = C_FindObjectsInit(session, search_tmpl, sizeof(search_tmpl) / sizeof(search_tmpl[0])); CHECK_RV(rv, "C_FindObjectsInit"); rv = C_FindObjects(session, handle, 1, &obj_count); CHECK_RV(rv, "C_FindObjects"); C_FindObjectsFinal(session); if (obj_count == 0) { fprintf(stderr, "Key not found in SE051\n"); return -1; } return 0; cleanup: C_FindObjectsFinal(session); return -1; } Usage example: CK_OBJECT_HANDLE priv_key; CK_BYTE key_id[] = { 0x10, 0x10, 0x10, 0x10 }; CK_OBJECT_CLASS priv_class = CKO_PRIVATE_KEY; find_key_by_id(key_id, sizeof(key_id), priv_class, &priv_key); Supported Mechanisms (verified on OP-TEE PKCS#11 TA + SE051) Operation Mechanism Constant Notes RSA key generation CKM_RSA_PKCS_KEY_PAIR_GEN 256–4096 bits AES key generation CKM_AES_KEY_GEN 16 or 32 bytes RSA sign/verify CKM_SHA256_RSA_PKCS PKCS#1 v1.5 RSA sign/verify (PSS) CKM_SHA256_RSA_PKCS_PSS PSS padding RSA encrypt/decrypt CKM_RSA_PKCS_OAEP OAEP recommended RSA encrypt/decrypt CKM_RSA_PKCS PKCS#1 v1.5 AES encrypt/decrypt CKM_AES_CBC_PAD CBC with PKCS#7 AES encrypt/decrypt CKM_AES_CBC CBC without padding AES encrypt/decrypt CKM_AES_CTR CTR mode ECC sign/verify CKM_ECDSA_SHA256 160–521 bits ECDH key agreement CKM_ECDH1_DERIVE   Can the SSS APIs Still Be Used at All? Yes — but only in the co-existence setup (Option 2) where Linux still has access to the I2C bus (i.e., the lf-6.12.y-i2c-disabled-se050 DTS patch has NOT been applied). In that case, you can use the SSS APIs as described in AN13030 Section 3.3 directly from Linux. If you choose Option 1 (OP-TEE exclusive), the Cryptoki/PKCS#11 C API shown above is the correct and only supported path from Linux userspace. Reference AN13030 Rev. 2.4, Section 3.3 — Full SSS API reference (for co-existence / non-OP-TEE builds) OP-TEE PKCS#11 TA test suite (pkcs11_1000.c): optee-test/host/xtest/pkcs11_1000.c — comprehensive C examples for all Cryptoki operations NXP GitHub: se05x-pkcs11 — NXP's PKCS#11 standalone library (alternative to libckteec.so for non-OP-TEE builds)   Hope that helps,   Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment @Kan_Li  Thank you very much for the clear and detailed explanation. We are currently considering using Option 1 or Option 2 depending on the stage of our future development (e.g., using Option 2 for initial testing/evaluation and Option 1 for production). Regarding Option 1 (OP-TEE PKCS#11 TA), we have a question about application development in C. If we would like to implement cryptographic operations such as key storage, signing / signature generation, signature verification, and encryption/decryption in a C program under Option 1, which approach should we take? Should we write a C program that directly calls standard PKCS#11 APIs (e.g., C_Initialize, C_CreateObject, C_SignInit, C_Sign, C_VerifyInit, C_Verify, etc.) via the OP-TEE PKCS#11 library (libckteec.so)? Or is it still possible/recommended to use the Plug & Trust MW SSS APIs (such as sss_key_store_set_key, sss_asymmetric_sign_digest, sss_asymmetric_verify_digest, sss_cipher_update, etc.) in this setup? If PKCS#11 APIs are required, could you please provide a simple sample code or reference guide for calling libckteec.so in C? Re: Seeking guidance: se05x_Minimal fails in OP-TEE environment Hi @Uc_S , Thank you for the detailed report. The root cause is clear, and I can explain exactly why this happens and what your options are. Root Cause se05x_Minimal was built with -DPTMW_SMCOM=T1oI2C . This tells the smCom layer to open a physical Linux I2C device node ( /dev/i2c-X ) at session open time. Since you applied the lf-6.12.y-i2c-disabled-se050 DTS patch (Step 1 of the integration guide), that I2C controller is disabled in Linux Normal World — the device node simply does not exist. OP-TEE exclusively owns the I2C bus via CFG_IMX_I2C=y , and Linux cannot see or open it. This is by design — the DTS patch is what gives OP-TEE exclusive, uncontended access to SE051. The se05x_Minimal binary built with T1oI2C is fundamentally incompatible with this configuration. Your Two Options ✅ Option 1 — Use OP-TEE PKCS#11 TA (Recommended for Production) This is the intended Linux userspace path in the OP-TEE exclusive setup. Instead of running se05x_Minimal , use pkcs11-tool or OpenSSL with libckteec.so (the OP-TEE PKCS#11 TA library). The TA internally uses SE051 as its crypto backend via OP-TEE's native I2C driver. Quick verification that SE051 is reachable via PKCS#11: # List available PKCS#11 slots — SE051 should appear pkcs11-tool --module /usr/lib/libckteec.so.0 --list-slots # Get a random number from SE051 via OP-TEE pkcs11-tool --module /usr/lib/libckteec.so.0 --generate-random 16 | xxd If you see a slot and random bytes, SE051 is fully accessible through OP-TEE. There is no need to run se05x_Minimal — it duplicates what the PKCS#11 TA already provides. ✅ Option 2 — Co-existence Setup (Recommended for Development/Testing) If you specifically need to run se05x_Minimal and other Plug & Trust MW demos from Linux userspace, use the co-existence setup where Linux DTS still has I2C enabled (i.e., do not apply the I2C-disabled DTS patch). Steps: Step 1 — Revert the Linux DTS to keep I2C enabled in Normal World Build your imx8mq-evk.dtb (or equivalent) from the unmodified Linux DTS (without the lf-6.12.y-i2c-disabled-se050 patch). The I2C controller node for SE051 must remain enabled in Linux. Step 2 — Keep your existing cmake flags unchanged Your current cmake configuration is correct for co-existence: cmake -S . -B ./build/ -DPTMW_Applet=SE05X_C -DPTMW_SE05X_Ver=07_02 -DPTMW_Host=iMXLinux -DPTMW_SMCOM=T1oI2C -DPTMW_HostCrypto=OPENSSL -DPTMW_RTOS=Default -DPTMW_mbedTLS_ALT=None -DPTMW_SCP=SCP03_SSS -DPTMW_SE05X_Auth=PlatfSCP03 -DPTMW_Log=Silent -DCMAKE_BUILD_TYPE=Release -DPTMW_OpenSSL=3_0 -DPTMW_SE_RESET_LOGIC=1 Step 3 — Set the I2C port before running export EX_SSS_BOOT_SSS_PORT=/dev/i2c-1 ./se05x_Minimal Trade-off: In this mode, both OP-TEE and Linux share the I2C bus to SE051. OP-TEE uses it for RSA/ECC offload; Linux uses it for MW demos. Concurrent access is not arbitrated, which can cause APDU collisions under load. Acceptable for development, but not recommended for production. Summary Option I2C DTS se05x_Minimal OP-TEE exclusive Recommended For PKCS#11 TA ( libckteec.so ) Disabled ❌ Not needed ✅ Yes Production Co-existence (T1oI2C) Enabled ✅ Works ⚠️ Shared I2C Development/Testing Clarification on the Integration Guide The community post you referenced (Step 2 — without CAAM) configures OP-TEE to exclusively own I2C. The Linux-side MW compilation shown in that guide (with T1oI2C ) was intended for the initial verification step before switching to OP-TEE mode — not for use alongside the OP-TEE exclusive I2C setup. Once OP-TEE owns I2C exclusively, the correct Linux userspace interface is the OP-TEE PKCS#11 TA, not the Plug & Trust MW SSS API demos directly. Please let us know which option fits your use case and we can provide further guidance. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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I2C read and write using s32k144 MBD toolbox Hello, I am using s32k144 to read and write data from an external EEPROM. I will attach the model below. I am able to write the data but the read returns 255+NACK as output. Am i missing something here Sriram_0-1737789999186.pngSriram_0-1737789999186.png Sriram_1-1737790013461.pngSriram_1-1737790013461.png Is there a way to specify the register address of the EEPROM in the I2Cmaster block Sriram_2-1737790096449.pngSriram_2-1737790096449.png Can you guys help me out with this issue. Thanks Re: I2C read and write using s32k144 MBD toolbox Hi, I am also facing the same issue with I2C communication using the S32K144 as the master and the ST M24C04 EEPROM as the slave. Since you are using the same microcontroller and EEPROM, I wanted to check whether you were able to find a solution. If you have resolved this issue, could you please share the solution or let me know what fixed it? Thank you in advance for your help. Re: I2C read and write using s32k144 MBD toolbox I m using M24C02-DRE EEPROM
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i.MX93 M33 Can't Use System TCM RAM for Allocation We're evaluating the i.MX9352 for an IoT device. I've created an application for the M33 core for time-critical IO operations which include collecting a large number of samples from peripherals. For development purposes, I am loading and starting the M33 code from Linux with remoteproc. Code is written in C and using MPUXpresso 26.06.00 SDK. I got the code working well, but now I need a large buffer for samples (~24 kB). I have tried adding this as either a static array or heap allocated with `malloc`. In either case, I seem to tun out of RAM even though the compile output indicates there is plenty. Working Version: Here's the memory information for a build with a small buffer, which **works OK** (but the buffer is too small for our requirements). Memory region Used Size Region Size %age Used m_interrupts: 1140 B 1144 B 99.65% m_text: 78300 B 129928 B 60.26% m_m33_suspend_ram: 0 B 8 KB 0.00% m_a55_suspend_ram: 0 B 4 KB 0.00% m_data: 48016 B 108 KB 43.42% m_rsc_tbl: 0 B 4 KB 0.00% build finished successfully. Here is some info from the ELF file: readelf -l imx_m33.elf Elf file type is EXEC (Executable file) Entry point 0xffe0595 There are 4 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x0ffe0000 0x0ffe0000 0x00474 0x00474 R 0x1000 LOAD 0x001478 0x0ffe0478 0x0ffe0478 0x131dc 0x131dc RWE 0x1000 LOAD 0x015000 0x20003000 0x0fff3654 0x00170 0x00170 RW 0x1000 LOAD 0x000180 0x20003180 0x0fff37e0 0x00000 0x0ba10 RW 0x1000 Section to Segment mapping: Segment Sections... 00 .interrupts 01 .resource_table .text .ARM .init_array .fini_array 02 .data 03 .bss .heap .stack Large Static Allocation: Here's the memory and ELF file info for a build with a **24 kB static allocated buffer**. I.e.: static uint32_t m_sample_queue[SAMPLE_QUEUE_LENGTH]; // SAMPLE_QUEUE_LENGTH = 6000 Memory region Used Size Region Size %age Used m_interrupts: 1140 B 1144 B 99.65% m_text: 78240 B 129928 B 60.22% m_m33_suspend_ram: 0 B 8 KB 0.00% m_a55_suspend_ram: 0 B 4 KB 0.00% m_data: 72016 B 108 KB 65.12% m_rsc_tbl: 0 B 4 KB 0.00% build finished successfully. ### (As expected, the `m_data` section has increased in size.) ### readelf -l imx_m33.elf Elf file type is EXEC (Executable file) Entry point 0xffe0595 There are 4 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x0ffe0000 0x0ffe0000 0x00474 0x00474 R 0x1000 LOAD 0x001478 0x0ffe0478 0x0ffe0478 0x131a0 0x131a0 RWE 0x1000 LOAD 0x015000 0x20003000 0x0fff3618 0x00170 0x00170 RW 0x1000 LOAD 0x000180 0x20003180 0x0fff37a0 0x00000 0x117d0 RW 0x1000 Section to Segment mapping: Segment Sections... 00 .interrupts 01 .resource_table .text .ARM .init_array .fini_array 02 .data 03 .bss .heap .stack When I try to start this version in Linux with remoteproc, it fails to start and dmesg shows the following errors: [ +0.001258] imx-rproc remoteproc-cm33: Translation failed: da = 0xfff37a0 len = 0x117d0 [ +0.000021] remoteproc remoteproc0: bad phdr da 0xfff37a0 mem 0x117d0 [ +0.000006] remoteproc remoteproc0: Failed to load program segments: -22 [ +0.008868] remoteproc remoteproc0: Boot failed: -22 Claude tells me this is a problem with the .bss .heap .stack section, because the PhysAddr is `0x0fff37a0` and the size is now `0x117d0`. `0x0fff37a0 + 0x117d0 = 0x10004f70` which exceeds the M33 Code TCM address range 0x0ffe0000 .. 0x10000000. The explaination was confusing but my interpretation is that the static initialisation has to go into the "code" section, causing it to overflow even though there is plenty of space in the "system" TCM range (the other 128 kB). So maybe this makes sense. Dynamic (Heap) Allocation: E.g.: uint32_t *p_sample_queue = malloc(SAMPLE_QUEUE_LENGTH, sizeof(uint32_t)); The default heap size available to C is only 1 kB, so malloc fails with our large buffer. I modified the CMake for the project to allocate a larger heap (32 kB) via __heap_size__ which feeds into the linker script: mcux_add_linker_symbol( SYMBOLS "__stack_size__=0x400 \ __heap_size__=0x8000 \ <---- Added __use_shmem__=1 \ __multicore__=1 \ " ) Build output and ELF file info: Memory region Used Size Region Size %age Used m_interrupts: 1140 B 1144 B 99.65% m_text: 78240 B 129928 B 60.22% m_m33_suspend_ram: 0 B 8 KB 0.00% m_a55_suspend_ram: 0 B 4 KB 0.00% m_data: 103760 B 108 KB 93.82% m_rsc_tbl: 0 B 4 KB 0.00% build finished successfully. #### ELF file info: #### readelf -l imx_m33.elf Elf file type is EXEC (Executable file) Entry point 0xffe0595 There are 4 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x0ffe0000 0x0ffe0000 0x00474 0x00474 R 0x1000 LOAD 0x001478 0x0ffe0478 0x0ffe0478 0x131a0 0x131a0 RWE 0x1000 LOAD 0x015000 0x20003000 0x0fff3618 0x00170 0x00170 RW 0x1000 LOAD 0x000180 0x20003180 0x0fff37a0 0x00000 0x193d0 RW 0x1000 Section to Segment mapping: Segment Sections... 00 .interrupts 01 .resource_table .text .ARM .init_array .fini_array 02 .data 03 .bss .heap .stack This seems to make the problem WORSE, not better (.bss/.heap/.stack at PhysAddr 0x0fff37a0, size 0x193d0). [ +0.001320] imx-rproc remoteproc-cm33: Translation failed: da = 0xfff37a0 len = 0x193d0 [ +0.000019] remoteproc remoteproc0: bad phdr da 0xfff37a0 mem 0x193d0 [ +0.000006] remoteproc remoteproc0: Failed to load program segments: -22 [ +0.002908] remoteproc remoteproc0: Boot failed: -22 I thought using heap allocation should allow the code section to be smaller and allocate the memory from the data section. The "m_data" section shown in the build output above is indeed bigger. I don't really understand the "PhysAddr", which matches the "Code TCM" range from the ref manual, even for things which should be in the "System TCM" region (I think?). The addresses under "VirtAddr" seem correct. Why does the ELF file still try to place this .bss/.heap/.stack data at PhysAddr 0x0fff37a0, why is it so big when using runtime heap allocation, and is there a way to allocate my large buffer in the "System TCM" region? Re: i.MX93 M33 Can't Use System TCM RAM for Allocation Hi @jcolebaker  You can choose to change the LMA for data/bss/heap/stack to System TCM. In the MCUX linker script, change the load address (AT) for the data segment from code TCM to System TCM, so that PhysAddr also falls at 0x2000_0000: .data : { ... } > m_data AT> m_data /* Do not use AT> m_text */ .bss : { ... } > m_data When LMA == VMA and both are in System TCM, PhysAddr becomes 0x2000_xxxx, which matches an entry in the {0x20000000, …, 0x00040000} (256 KB) range in remoteproc driver, allowing remoteproc to translate correctly. Best Regards, Zhiming
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S32DS for ARM 2018.R1 デバッグ問題 ARM 2018.R1用のS32DSでチップのデバッグ時に問題が発生しS32K146、以下の通りです: 送信後にGDBバージョンを特定できませんでした:D:\S32DS\eclipse\./Cross_Tools/gcc-arm-none-eabi-4_9/bin/arm-none-eabi-gdb --version、応答: しかし、Jlinkはチップの編集や消去、プログラムが可能です。私はARM 2018.R1のS32DSでデバッグしていません。助けてください。ありがとうございます! Re: S32DS for ARM 2018.R1 debug Problem Hi@lyz あなたの質問の意味がよく分かりませんでした。エラーのスクリーンショットを投稿してもらえますか?
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S32DS for ARM 2018.R1 调试问题 使用 S32DS for ARM 2018.R1 调试 S32K146 芯片时出现问题,具体如下: 发送以下命令后无法确定 GDB 版本:D:\S32DS\eclipse\../Cross_Tools/gcc-arm-none-eabi-4_9/bin/arm-none-eabi-gdb --version,响应如下: 但是,Jlink 可以连接、擦除和编程芯片。我现在无法使用 S32DS for ARM 2018.R1 进行调试,请帮帮我,谢谢! Re: S32DS for ARM 2018.R1 debug Problem 嗨@lyz 我不太明白你的问题。能否提供一下错误截图?
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T1042NXE BSDLファイル こんにちは、このコンポーネントのBSDLファイルを探しています。 T1042NXE7PQB BGA780 ファイルを送ってもらえますか? よろしくお願いします。 Re: T1042NXE BSDL file こんにちは、 コンポーネントT1042NXE7PQBの BSDL ファイルは、 T1040/T1042 結合 BSDL ファイル(ファイル名: T1040_and_T1042_1.1.bsdl ) に含まれています。この単一のファイルはT1040とT1042の両方のプロセッサに適しています。 ダウンロード方法 このファイルはNXPの製品ページの「 Design Resources → Design Files → モデル」で直接入手可能です: T1040/42用BSDLファイル — ダウンロード(アカウント登録が必要です) ファイルコード: T1040-T1042-BSDL 改訂版:R1A(2019年2月20日) サイズ:110.13 KB よろしくお願いします。
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HSE FWの真正性を確認する方法 今、NXPエンジニアが提供した「HseLib_HseFwInstall」ソフトウェアを使ってHSE FWをインストールしました。 お客様から質問があります:HSE FW自体に署名がないと考えているため、HSE FWの真正性をどのように確認すればよいか。 屏幕截图 2026-09-17 182416.png 画面截图 2026-09-17 182416.png 改ざんされやすいと。 HSEのFWの真正性を証明するためのセキュリティ制度があると教えてくれる人はいますか? Re: How to confirm HSE FW authenticity おそらく新しいチケットを作成することも可能です: https://www.nxp.com/support/support:SUPPORTHOME HSE文書は安全なファイルなので、すでに手続きを済ませている場合は以下の手順に従う必要があります。 https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf プレゼンテーションを共有できるかもしれません。 Re: How to confirm HSE FW authenticity この質問に答えてくださりありがとうございます。これらの内容に関する参考文献をどうやって見つければよいか教えていただけますか?In まだこれらの内容には気づいていません。 Re: How to confirm HSE FW authenticity こんにちは、 HSE FWは確かに保護されており、単なる署名なしバイナリではありません。 ファームウェアイメージは、配布前にNXPによって暗号化および署名されます。 NXPは製造時にHSEサブシステムに ROM鍵 を事前プログラムします(ハードウェアの信頼の基点)。これらの鍵は外部からは決してアクセスできません。 インストール中、オンチップのセキュアBAFは、イメージをフラッシュメモリに書き込む前に、これらのROMキーを使用してイメージを認証します。改ざんされた画像は拒否されます。 結論として、NXPの秘密署名鍵がなければ、改変されたHSEファームウェアをインストールすることは不可能です。その信頼はシリコンに根ざしている。
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T1042NXE BSDL 文件 您好,我正在寻找该组件的BSDL文件: T1042NXE7PQB BGA780 你能把文件发给我吗? 谢谢! Re: T1042NXE BSDL file 你好, 您的元器件T1042NXE7PQB的 BSDL 文件包含在T1040/T1042 组合 BSDL 文件(文件名: T1040_and_T1042_1.1.bsdl )中。这个文件同时适用于 T1040 和 T1042 处理器。 如何下载 该文件可直接在 NXP 产品页面的“设计资源”→“设计文件”→“模型”下找到: T1040/42 的 BSDL 文件 — 下载(需要账号) 文件代码: T1040-T1042-BSDL 修订版:R1A(2019年2月20日) 大小:110.13 KB 此致
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如何确认 HSE FW 的真伪 现在,我使用了NXP工程师提供的“HseLib_HseFwInstall”软件来安装HSE固件。 我们的客户提出了一个问题:如何确认 HSE 固件的真伪,因为他认为 HSE 固件本身没有任何签名。这很容易。 屏幕截图 2026-09-17 182416.png屏幕截图2026-09-17 182416.png被篡改。 谁能告诉我 HSE FW 是否有网络安全措施来确认 HSE FW 的真实性? Re: How to confirm HSE FW authenticity 或许您可以创建一个新的工单: https://www.nxp.com/support/support:SUPPORTHOME HSE 文件属于安全文件,因此除非您之前已经操作过,否则需要遵循以下步骤: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf 我们可以一起做一些演示。 Re: How to confirm HSE FW authenticity 感谢您回答这个问题。请问我该如何找到关于这些内容的参考资料?我在《RM758222-HSE-B 固件参考手册 - V2.2》中还没有注意到这些内容。 Re: How to confirm HSE FW authenticity 您好, HSE固件确实受到保护——它不是普通的未签名二进制文件。 固件镜像在分发前由 NXP 进行加密和签名。 NXP 在制造过程中将ROM 密钥预先编程到 HSE 子系统中(硬件信任根)。这些密钥永远无法从外部获取。 安装过程中,片上安全 BAF会使用这些 ROM 密钥来验证映像,然后再将其写入闪存。篡改过的图片会被拒绝。 结论是:如果没有 NXP 的私钥,就不可能安装修改过的 HSE 固件。信任源于硅谷。
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How to confirm HSE FW authenticity Now,I Used  “HseLib_HseFwInstall”software witch is supply by NXP engineer to install HSE FW。 Our customer raise a question: how to confirm HSE FW authenticity, because he think HSE FW itself don't have any signature,.it is easy 屏幕截图 2026-09-17 182416.png屏幕截图 2026-09-17 182416.pngto be tampered. Who can tell me HSE FW weather have some security scheme to comfirm HSE FW authenticity? Re: How to confirm HSE FW authenticity Possibly you could create new ticket: https://www.nxp.com/support/support:SUPPORTHOME HSE documents are secure files, so following procedure is needed to follow unless you have already done it before: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf We could possibly share some presentation. Re: How to confirm HSE FW authenticity Thank you for answer this question.Could you tell me how can I find these reference about these contents.In I haven't noticed these contents yet. Re: How to confirm HSE FW authenticity Hi, HSE FW is indeed protected — it is not plain unsigned binary. The FW image is encrypted and signed by NXP before distribution. NXP pre-programs ROM keys into the HSE subsystem during manufacturing (hardware Root of Trust). These keys are never accessible externally. During installation, the on-chip Secure BAF uses those ROM keys to authenticate the image before writing it to flash. A tampered image is rejected. Bottom line: without NXP's private signing key, it is impossible to install a modified HSE FW. The trust is rooted in silicon.
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