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Looking for GUI Guider v1.9.0 installer I'm currently working on a project that was originally created with GUI Guider v1.9.0. For compatibility reasons, I need to get the exact v1.9.0 installer, but the official NXP website now only offers newer versions. Does anyone still have the Gui-Guider-Setup-1.9.0 file handy, or know where I can download this specific older version? Also, if I open a v1.9.0 project directly with a newer version (e.g., v1.10.0), will it cause any compatibility issues? Any help or pointers would be greatly appreciated. Thanks! Re: Looking for GUI Guider v1.9.0 installer Hello @李先森 , Thanks for your post. The GUI Guider v1.9.0 installer was not provided any more. However, GUI Guider can upgrade projects created by the last major version and related minor version. Therefore, you can directly use GUI Guider v1.10.x and import project created by GUI Guider v1.9.x. Hope it helps. BR Celeste ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! -----------------------------------------------------------------------------------------------------------------------
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PNEV7642FAMA pack Keil MDK project from SDK_2_12_1_PNEV7642FAMA requires PackID NXP.PN7642_DFP.15.0.0, but it is missing from :·https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.pidx· and direct pack URL returns 404. Please provide NXP.PN7642_DFP.15.0.0.pack or enable access. Re: PNEV7642FAMA pack Hello @Sinrow  PackID NXP.PN7642_DFP.15.0.0 is security file, you need to sign NDA with NXP and then request this file.
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FRDM-IMX95-1 は fsl-se-fw se-fw2: 応答失敗 = 0x29 で停止しています EdgeLock Enclave(ELE)/System マネージャのファームウェアが起動時に初期化に失敗します:   [ 0.182931] fsl-se-fw se-fw2: コマンドID[23]、応答失敗 = 0x29 [ 0.182942] fsl-se-fw se-fw2: ele fw の初期化に失敗しました。 ELEの初期化に失敗したためです。 MaliのGPU(4d900000.gpu)パワードメインはオフのままで、LinuxがGPUをプロブングするとARM64 SError割り込みカーネルパニックを引き起こします。 GPUノードを無効にすると起動は進めますが、 USDHCストレージ(mmc0およびmmc1 )が初期化に失敗しエラー-5が発生し、Linuxがrootファイルシステム(/dev/mmcblk*p2)をマウントできません。 「システムの再インストール」を実行しても、この問題は解決しません。管理者の方が 、FRDM-IMX95-1ユニットのプライマリブートローダー/ELEファームウェアを再フラッシュしてもらえますか? クラウド・ラボ オンラインラボ 仮想テスト Re: FRDM-IMX95-1 is stuck with fsl-se-fw se-fw2: Response Failure = 0x29 こんにちは、 テスト用のソフトウェア/ハードウェアのセットアップについて、もう少し教えていただけますか? カスタム画像を使用している場合は、変更内容を共有してください。 また、基板のファームウェアを再書き込みしてみてください。 よろしくお願いいたします。
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寻找 GUI Guider v1.9.0 安装程序 我目前正在开发一个项目,该项目最初是用 GUI Guider v1.9.0 创建的。出于兼容性考虑,我需要获取 v1.9.0 的安装程序,但 NXP 官方网站现在只提供更新的版本。 请问有人手头还有 Gui-Guider-Setup-1.9.0 文件吗?或者知道哪里可以下载这个旧版本?另外,如果我用新版本(例如 v1.10.0)直接打开 v1.9.0 的项目,会不会出现兼容性问题? 任何帮助或建议都将不胜感激。谢谢! Re: Looking for GUI Guider v1.9.0 installer 你好@李先森, 感谢您的帖子。GUI Guider v1.9.0 安装程序已不再提供。 但是,GUI Guider 可以升级由上一个主要版本和相关的次要版本创建的项目。因此,您可以直接使用 GUI Guider v1.10.x 并导入由 GUI Guider v1.9.x 创建的项目。 希望对您有所帮助。 BR 塞莱斯特 ----------------------------------------------------------------------------------------------------------------------- 注:如果此帖解答了您的问题,请点击“接受为解决方案”按钮。谢谢你! -----------------------------------------------------------------------------------------------------------------------
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NXP牵引/轴向电机参考固件 你好, 我正在进行一个牵引/轴向控制电机项目,我想了解恩智浦半导体(NXP)用于轴向电机开发的参考软件,这将对我们正在进行的项目的研究和开发非常有帮助。 因此,我请求您提供此问题的解决方案,同时,NXP 提供的牵引/轴向电机参考软件将为我们的研发工作提供可靠的参考。 谢谢 帕万 Re: NXP reference firmware for traction/axial motors 你好, NXP 不提供专门用于轴向磁通电机的专用软件。在大多数情况下,轴向磁通永磁同步电机可以使用与传统径向磁通永磁同步电机相同的永磁同步电机FOC参考软件进行控制。主要的改进在于电机参数化(Rs、Ld、Lq、极对数、磁链等),而控制算法基本保持不变。 典型的切入点是: S32K344 / S32K396 电机控制参考设计 永磁同步电机磁场定向控制(FOC)示例 AMMCLIB 电机控制库 基于模型的设计工具箱示例(如果使用 MATLAB/Simulink) 顺祝商祺! Peter
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NXP reference firmware for traction/axial motors Hello, I am working on a Traction/Axial control motor project and I wanted to know about the reference software for the Axial motor based development from NXP,so it will be very helpful for the reasearch and development of our ongoing project. So I am requesting to provide me the solution for this and also the reference software for Traction/Axial motor from NXP will be a solid reference for our R and D. Thank you Pavan Re: NXP reference firmware for traction/axial motors Hello, NXP does not provide dedicated software specifically for axial-flux motors. In most cases, axial-flux PMSM motors can be controlled using the same PMSM FOC reference software as conventional radial-flux PMSM motors. The main adaptation is the motor parameterization (Rs, Ld, Lq, pole-pair count, flux linkage, etc.), while the control algorithm remains essentially the same. Typical starting points are: S32K344 / S32K396 motor-control reference designs PMSM Field-Oriented Control (FOC) examples AMMCLIB motor-control library Model-Based Design Toolbox examples (if MATLAB/Simulink is used) Best regards, Peter
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FRDM-IMX95-1 is stuck with fsl-se-fw se-fw2: Response Failure = 0x29 The EdgeLock Enclave (ELE) / System Manager firmware fails to initialize during boot:   [ 0.182931] fsl-se-fw se-fw2: Command Id[23], Response Failure = 0x29 [ 0.182942] fsl-se-fw se-fw2: Failed to initialize ele fw. Because ELE fails to initialize: The Mali GPU (4d900000.gpu) power domain stays off, triggering an ARM64 SError Interrupt kernel panic when Linux probes the GPU. Disabling the GPU node allows boot to proceed further, but USDHC storage (mmc0 and mmc1) fails initialization with error -5, preventing Linux from mounting the root filesystem (/dev/mmcblk*p2). Using "Reinstall system" does not resolve this issue. Could an admin please reflash the primary bootloader/ELE firmware on unit FRDM-IMX95-1? Cloud Lab online laboratory Virtual test Re: FRDM-IMX95-1 is stuck with fsl-se-fw se-fw2: Response Failure = 0x29 Hello, Could you please share more about your testing SW/HW setup? If you are using a custom image please share the changes. Also, please try to re-flash the board. Best regards.
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FRDM-IMX95-1 卡在 fsl-se-fw se-fw2:响应失败 = 0x29 EdgeLock Enclave (ELE) / 系统管理器固件在启动过程中初始化失败:   [ 0.182931] fsl-se-fw se-fw2:命令 ID[23],响应失败 = 0x29 [0.182942]fsl-se-fw se-fw2:无法初始化ele fw。 因为 ELE 初始化失败: Mali GPU(4d900000.gpu)功率域保持关闭状态,当 Linux 探测 GPU 时,会触发 ARM64 SError 中断内核崩溃。 禁用 GPU 节点后,启动可以继续进行,但USDHC 存储(mmc0 和 mmc1)初始化失败,错误代码为 -5,导致 Linux 无法挂载根文件系统(/dev/mmcblk*p2)。 使用“重新安装系统”无法解决此问题。管理员能否重新刷写FRDM-IMX95-1设备上的主引导加载程序/ELE 固件? 云实验室 在线实验室 虚拟测试 Re: FRDM-IMX95-1 is stuck with fsl-se-fw se-fw2: Response Failure = 0x29 你好, 能否请您详细介绍一下您的测试软硬件配置? 如果您使用的是自定义图片,请分享更改内容。 另外,请尝试重新刷写板。 顺祝商祺!
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NXP製トラクション/アキシャルモーター用リファレンスファームウェア こんにちは、 私は牽引/軸流制御モーターのプロジェクトに取り組んでおり、NXPの軸流モーター開発のリファレンスソフトウェアについて知りたいと思っています。これは進行中のプロジェクトの再調査と開発に非常に役立つでしょう。 そこで、この問題の解決策を提供してほしいとお願いしていますし、またNXPのトラクション/アクシアルモーターのリファレンスソフトも研究開発の有力な参考になるでしょう。 ありがとうございます パヴァン Re: NXP reference firmware for traction/axial motors こんにちは、 NXPは軸流磁束モーター専用のソフトウェアを提供していません。ほとんどの場合、軸方向磁束PMSMモーターは従来のラジアルフラックスPMSMモーターと同じPMSM FOC参照ソフトウェアで制御可能です。主な変更点はモーターのパラメータ設定(Rs、Ld、Lq、極対数、磁束鎖交など)であり、制御アルゴリズムは基本的に同じままです。 典型的な出発点は以下のとおりです。 S32K344 / S32K396 モーター制御のリファレンスデザイン PMSMの磁界指向制御(FOC)の例 AMMCLIB モーター制御ライブラリ モデルベース設計ツールボックスの例(MATLAB/Simulinkを使用する場合) よろしくお願いいたします。 ピーター
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PNEV7642FAMAパック SDK_2_12_1_PNEV7642FAMA の Keil MDK プロジェクトには PackID NXP.PN7642_DFP.15.0.0 が必要ですが、 https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.pidxには存在せず、直接パック URL にアクセスすると 404 が返されます。NXPをご提供ください。PN7642_DFP.15.0.0.pack、またはアクセスを有効にしてください。 Re: PNEV7642FAMA pack こんにちは、 @Sinrow さん。 PackID NXP。PN7642_DFP.15.0.0はセキュリティファイルで、NXPとNDAに署名し、このファイルをリクエストする必要があります。
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GUI Guider v1.9.0 インストーラーを探しています 現在、GUI Guider v1.9.0で作成されたプロジェクトに取り組んでいます。互換性の理由から、正確なv1.9.0インストーラーを入手する必要がありますが、公式NXPのウェブサイトでは今は新しいバージョンしか提供していません。 Gui-Guider-Setup-1.9.0ファイルはまだ手元にある方や、この古いバージョンをダウンロードできる場所をご存知の方はいらっしゃいますか?また、v1.9.0のプロジェクトを新しいバージョン(例:v1.10.0)で直接開いた場合、互換性の問題は起きませんか? 何か助言やアドバイスがあれば大変ありがたいです。ありがとうございます! Re: Looking for GUI Guider v1.9.0 installer こんにちは@李先森さん 投稿ありがとうございます。GUI Guider v1.9.0のインストーラーは提供されなくなりました。 しかし、GUI Guiderは前回のメジャーバージョンおよび関連するマイナーバージョンで作成されたプロジェクトをアップグレードできます。したがって、GUI Guider v1.10.xを直接使い、GUI Guider v1.9.xで作成されたプロジェクトをインポートできます。 お役に立てば幸いです。 BR セレステ ----------------------------------------------------------------------------------------------------------------------- 注:この投稿があなたの質問への回答になっている場合は、「解決策として承認」ボタンをクリックしてください。ありがとう! -----------------------------------------------------------------------------------------------------------------------
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このシステムは、IMX8MPプラットフォーム、SGTL5000サウンドカード、およびLinuxカーネルバージョン5.4.70を使用しています。音声再生時に、カーネルに「アンダーラン」メッセージが表示され、サウンドカードのDMA(データ転送解析)機能が正常に動作しなくなります。 メインコントローラー:imx8mp カーネル: Linux 5.4.70 サウンドカード:SGTL5000 アプリケーション:mmapを使用してデータをDMAバッファに移動します。 障害の症状: アプリケーションが一定時間オーディオを再生すると、カーネルに次のエラーメッセージが表示されます: fsl-sai 30C3000.sai: isr:Transmit。「アンダーランが検出されました」というメッセージが画面に表示され、特定のカーネルファイル(./kernel/kernel-5.4.70/sound/soc/fsl/fsl_sai.c)に対応しています。 .......... if(flags & FSL_SAI_CSR_FEF) { dev_dbg(dev,"isr:送信アンダーランを検出しました\n"); /* 安全のためFIFOをリセット */ xcsr |= FSL_SAI_CSR_FR; } .......... 同時に、`cat /proc/interrupts | grep sdma` コマンドを使用してサウンドカードの DMA 割り込み数をチェックし、増加しないようにします。 現在のコード構成では、FIFOがアンダーランするとFIFOの状態が異常になり、それが原因でDMAが誤動作するというのは本当でしょうか? IMX8MPの仕様を見ると、次のような説明があります。FCONT: IMX8MP PRMドキュメント14.4.2.7.3。FIFOエラー継続が有効になっている場合、FIFOはアンダーラン後もソフトウェアの介入なしにデータの送信を継続します。データが正しい順序で送信されるようにするため、送信機は、FIFO がアンダーランしたフレーム内の同じワード番号から処理を続行しますが、送信 FIFO に新しいデータが書き込まれた後にのみ続行します。 仕様書に記載されているこの構成によると、この状況でDMAがアンダーランした後でも、正常に動作し続けることができるのでしょうか?DMAがデータをFIFOに移動すれば、以前のDMAが誤動作してFIFOがアンダーランする代わりに、以前のサウンドを再生し続けることができるのでしょうか? Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 こんにちは@zhuliushun 1. FCONTの理解は基本的に正しいが、FCONTは根本的な解決策ではない。 2. 根本的な原因は、TX FIFOの供給速度が消費速度よりも遅いことです。この点を確認して、原因を特定してください。 3. 次の2つのパッチのインストールを検討してください。 LKML: Shengjiu Wang: [PATCH] ASoC: fsl_sai: 「FIFO continue on error」FCONTビットを有効にする ASoC: fsl_sai: ISR 内の不要な FIFO リセットを削除 - Patchwork よろしくお願いします、 志明 Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 こんにちは@Zhiming_Liu はい、この問題の原因は、FIFOへのデータ充填速度がFIFOのデータ消費速度よりも遅いことです。そして、FIFOへのデータ充填はDMAに基づいています。 1. 現在のデバッグにより、FIFOが空になるとアンダーランが発生し、DMAも動作を停止するため、FIFOが補充されなくなることが明らかになりました。 2.投稿にある 2 つのパッチを適用した後、デバッグの結果、FIFO がまだアンダーランしており、DMA が機能していないことが判明しました。 fsl_sai.c の割り込みコールバック関数 fsl_sai_isr() では、xcsr と tcr4 の値が出力されます。詳細は以下を参照してください。 fsl-sai 30c30000.saiscsr :ステータス:0xd0170c01 fsl-sai 30c30000.sai isr: 送信インダランを検出しました、tcr4: 0x18010f3a 不具合が発生した際、前述の印刷処理によって画面が繰り返し更新された。 3. 2の知見に基づくと、tcr4のbit[28]は=1、 FCONTが有効です。 4. 私の問題について:オーディオファイルの再生がフリーズします(FIFOアンダーラン、DMAが動作しない、停止)。私が望む解決策は、FIFOアンダーランが発生した場合、ハードウェアデータを保持し、リセットせずに現在の状態を移動させ、DMAは正常に動作することです。バッファにデータが利用可能になったとき(アプリケーションがmmapを使用してデータを埋めたとき)、 DMA(FIFOからのDMA要求に基づく)はデータをFIFOに移動し、オーディオファイルの再生を継続できるようにします。これは実現可能でしょうか?
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PNEV7642FAMA 包 来自 SDK_2_12_1_PNEV7642FAMA 的 Keil MDK 项目需要 PackID NXP.PN7642_DFP.15.0.0,但该 PackID 在:·https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.pidx·中缺失,并且直接的 pack URL 返回 404。请提供 NXP.PN7642_DFP.15.0.0.pack 或启用访问权限。 Re: PNEV7642FAMA pack 你好@Sinrow PackID NXP.PN7642_DFP.15.0.0 是安全文件,您需要与 NXP 签署保密协议,然后才能申请此文件。
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The system uses an IMX8MP platform, an SGTL5000 sound card, and a Linux kernel version of 5.4.70. When playing sound, the kernel displays an "underrun" message, and the sound card's DMA (Data Transfer Analysis) function malfunctions. Main controller: imx8mp Kernel: Linux 5.4.70 Sound card: SGTL5000 Application: Moves data into the DMA buffer using mmap. Fault symptom: When the application plays audio for a period of time, the kernel displays the error message: fsl-sai 30C3000.sai: isr:Transmit. The "underrun detected" message is printed on the screen and corresponds to the specific kernel file: ./kernel/kernel-5.4.70/sound/soc/fsl/fsl_sai.c. ........... if(flags & FSL_SAI_CSR_FEF) { dev_dbg(dev,"isr:Transmit underrun detected\n"); /* FIFO reset for safety */ xcsr |= FSL_SAI_CSR_FR; } ........... At the same time, use the command `cat /proc/interrupts | grep sdma` to check the DMA interrupt count for the sound card and stop it from increasing. In the current code setup, is it true that when the FIFO goes underrun, the FIFO state becomes abnormal, which in turn causes the DMA to malfunction? Looking at the IMX8MP specifications, there's a description like this: FCONT: IMX8MP PRM document 14.4.2.7.3. When FIFO Continue on Error is enbaled, the FIFO continues transmitting data following an underrun without software intervention. To ensure that data transmits in the correct order, the transmitter continues from the same word number in the frame that caused the FIFO to inderrun, but only after new data writes to transmit FIFO ........................................ According to this configuration in the specification, in this situation, after the DMA goes underrun, can it still work normally? As long as the DMA moves the data to the FIFO, it can continue playing the previous sound, instead of the previous DMA malfunctioning and the FIFO going underrun? Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 Hi @zhuliushun 1. The understanding of FCONT is basically correct, but FCONT is not a fundamental solution. 2. The root cause is that the TX FIFO feeding speed is less than the consumption speed. You can check this to see if it is the case. 3. Consider installing the following two patches: LKML: Shengjiu Wang: [PATCH] ASoC: fsl_sai: Enable 'FIFO continue on error' FCONT bit ASoC: fsl_sai: Remove unnecessary FIFO reset in ISR - Patchwork Best Regards, Zhiming Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 Hello @Zhiming_Liu Yes, the reason for this problem is that the FIFO filling speed is slower than the FIFO data consumption speed. And FIFO filling is based on DMA. 1. Current debugging has revealed that when the FIFO is depleted, it undergoes an underrun, and the DMA also stops working, thus preventing the FIFO from being refilled. 2. After applying the two patches from the post, debugging revealed that the FIFO still underruns, and DMA is not working . In the interrupt callback function fsl_sai_isr() in fsl_sai.c, the values of xcsr and tcr4 are printed. See below for details: fsl-sai 30c30000.sai scsr :status:0xd0170c01 fsl-sai 30c30000.sai isr: transmit inderrun detected,tcr4: 0x18010f3a When the malfunction occurred, the above-mentioned printing kept refreshing the screen. 3. Based on the findings in 2, bit[28] in tcr4 =1, FCONT is enabled . 4. Regarding my problem: audio file playback freezes (FIFO underrun, DMA not working, stuck). My desired solution is: when the FIFO underruns, preserve the hardware data and move the current state without resetting, while the DMA functions normally . When data becomes available in the buffer (filled by the application using mmap), the DMA (based on the DMA request from the FIFO) moves the data to the FIFO , allowing the audio file to continue playing. Is this feasible?
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imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 主控:imx8mp 内核:linux5.4.70 声卡:sgtl5000 应用程序:基于mmap方式,向dma buffer中搬移数据。 故障现象:当应用程序播音一段时间,内核出现 fsl-sai 30C3000.sai:isr:Transmit underrun detected的刷屏打印,对应具体的内核文件:./kernel/kernel-5.4.70/sound/soc/fsl/fsl_sai.c文件。 ........... if(flags & FSL_SAI_CSR_FEF) {      dev_dbg(dev,"isr:Transmit underrun detected\n");      /* FIFO reset for safety*/      xcsr |= FSL_SAI_CSR_FR; } ........... 同时使用指令cat /proc/interrupts | grep sdma 查看声卡对那个的dma中断计数,停止增加。 在目前代码的设置里面,是不是当FIFO出现underrun的情形之后,FIF状态异常,进而导致dma工作异常呢? 查看imx8mp的规格书,有这样一个描述FCONT:IMX8MPPRM文档 14.4.2.7.3章节。When FIFO Continue on Error is enbaled,the FIFO continues transmitting data following an underrun without software intervention. To ensure that data transmits in the correct order,the transmitter continues from the same word number in the frame that caused the FIFO to inderrun,but only after new data writes to transmit FIFO ............................................ 按照规格书的这段配置,针对这样的情况 是不是出现underrun之后,dma还可以正常工作,只要dma将数据搬移至fifo,就可以继续之前的声音播放,而不是像之前的dma异常工作,而FIFO处于underrun状态呢? Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 Hi @zhuliushun  1.对FCONT 的理解方向基本正确,但是FCONT不是根本上的解决办法。 2.根本原因还是TX FIFO 投喂速度 < 消耗速度,这个你可以调试看看,是不是这样。 3.可以考虑打入下面的两个补丁: LKML: Shengjiu Wang: [PATCH] ASoC: fsl_sai: Enable 'FIFO continue on error' FCONT bit ASoC: fsl_sai: Remove unnecessary FIFO reset in ISR - Patchwork Best Regards, Zhiming Re: imx8mp platform,sgtl5000声卡,linux内核版本5.4.70,当声音播放的时候,内核出现underrun的刷屏打印,而且声卡执行数据搬移的dma工作异常。 Hello @Zhiming_Liu  是的,这个问题的原因是FIFO填充慢的速度小于fifo的数据消耗速度。而FIFO填充是基于DMA来实现的。 1.  目前调试发现:当FIFO消耗完之后,FIFO发生underrun,同时dma也不工作,这样也不会填充fifo。 2.  将帖子中的2个patch打入之后,调试发现fifo依然后发生underrun,同时dma不工作。 在fsl_sai.c的中断回调函数中fsl_sai_isr()中,打印出xcsr的值与tcr4的值。具体如下所示: fsl-sai 30c30000.sai  scsr :status:0xd0170c01 fsl-sai 30c30000.sai isr: transmit inderrun detected,tcr4: 0x18010f3a 当故障发生的时候,上述的打印一直在刷屏打印 3.  依据2的发现.tcr4中bit[28] =1,FCONT是使能的。 4.  针对我的问题:播放音频文件卡死问题(fifo underrun,dma不工作,一直卡死)。我的一个期望的解决方案:当fifo发生underrun的时候,保留硬件数据搬移现场,不复位,dma工作正常。等到buffer有数据的时候(应用程序以mmap方式填充buffer),dma(依据fifo发过来的dma request)将数据搬移至fifo,这样音频文件可以继续接着播放,不知道这样可以实现吗?
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TJA1040T/CM,118 → TJA1044CT/0Z Migration: Functional & Software Differences 1. Introduction This document provides a detailed technical comparison between the TJA1040T/CM,118 (now EoL) and its recommended replacement, the TJA1044CT/0Z, with a focus on hardware and software compatibility. Our AH1308 Application Hints explicitly confirm that all Mantis-family transceivers (including the TJA1044) are drop-in replacements for the TJA1040 and TJA1042, as long as the SPLIT pin is not used in the existing design. Several functional differences nevertheless require engineering review, as detailed in the sections below. 2. Quick Reference: Key Differences at a Glance 3. Pin 5: SPLIT vs. NC The TJA1040 provides an active VCC/2 voltage source on Pin 5 (SPLIT) in Normal mode, which is intended to be connected to the centre tap of a split bus termination network to stabilise the common-mode voltage and reduce EME. In Standby mode the SPLIT output is floating. The TJA1044CT pin 5 is internally not bonded (NC). The following scenarios apply: • SPLIT pin was NOT connected in the existing design: No hardware modification required. The two devices are pin-compatible in this configuration. • SPLIT pin WAS connected for split termination: The centre-tap capacitor should be reconnected to GND directly (passive split termination). This may cause a marginal EME difference, which should be verified against OEM requirements. 4. Wake-up Behavior (Key Functional/Software Difference) The TJA1040 implements "basic wake-up" per the older ISO 11898-2 standard: the low-power receiver monitors the bus and asserts RXD LOW as soon as a single continuous dominant phase longer than tBUS (0.75–5 µs) is detected. No pattern is required. The TJA1044CT implements "wake-up pattern" wake-up per ISO 11898-2:2024: a complete dominant–recessive–dominant (D-R-D) pattern must be received before RXD is asserted. Each phase must meet minimum filter requirements and the entire pattern must complete within the wake-up timeout window. Software impact: confirm the node is woken using a standard CAN wake-up pattern rather than a single dominant edge. Most CAN stacks already generate a WUP, but this should be verified for the end application. 5. TXD Dominant Time-out Both devices provide the TXD dominant time-out fail-safe (the transmitter is disabled if TXD is held LOW). The function behavior is identical, but the timing parameters differ: The TJA1044 time-out is longer, which lowers the minimum supported bit rate. This is only relevant for very-low-bit-rate designs. 6. Standby-to-Normal Mode Transition Time The transition time from Standby to Normal mode is longer on the TJA1044CT. If the µC firmware drives STB LOW and immediately begins CAN transmission without a guard delay, the first transmitted frames may be corrupted or lost when using the TJA1044CT.  Recommendation: ensure the µC waits a minimum of 47µs after asserting STB LOW before initiating any CAN frame transmission.  7. Undervoltage Detection and OFF Mode  The TJA1040 has two operating modes (Normal, Standby). When VCC is lost, pins TXD/STB/RXD become floating, with no defined bus disengagement. The TJA1044CT introduces a third operating mode, OFF, with two undervoltage detection thresholds on VCC: This is a fail-safe improvement. The bus is properly disengaged (zero load) when VCC is insufficient, preventing an unpowered node from affecting bus communication. No software change is required to benefit from this feature. 8. VCC Range and Additional Electrical Improvements The TJA1044CT offers several electrical improvements over the TJA1040 that are fully backward compatible and require no design changes: 9. Summary of Required Actions
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Methods to update NBU firmware on KW47 and MCX W72 This post provides guidance on how to update the NBU firmware on MCX W72 and KW47 devices through several methods: Bootloader Host Application (blhost), Secure Provisioning Tool, LinkServer. The Narrow Band Unit (NBU) is a dedicated compute subsystem for the Narrowband Radio, present in select NXP wireless microcontrollers. It is comprised of an Arm® Cortex®-M33 and associated peripherals that, in conjunction with the Bluetooth Unit, support the Bluetooth LE protocol. Running at 96 MHz alongside a 2.4 GHz transceiver, the NBU operates independently from the main application core, offloading all radio processing from the primary CPU and freeing it for application tasks. While the NBU allows for flexibility for evolving requirements, firmware to implement radio protocols is intended to be developed and delivered by NXP. Note: It is important that the NBU firmware version matches the SDK version of the application. After downloading the SDK and before running any wireless examples, update the NBU firmware using the binaries provided in the SDK folder. The NBU binary file is located in the SDK folder. Go to the SDK root folder and open the path: path_to_SDK\mcuxsdk\middleware\wireless\ble_controller\bin Prerequisites To follow this guide, the following environment is required: Software Setup Bootloader Host Application (blhost). Download here. MCUXpresso Secure Provisioning Tool. Download here. LinkServer for Microcontrollers. Download here. Hardware Setup Development boards associated with the MCX W72 or KW47 microcontroller families may be used. The ISP button varies by board and is referred to as ISP_button  throughout this guide: Development board ISP_button FRDM-MCXW72 SW3 MCXW72-LOC SW4 KW47-EVK SW4 KW47-LOC SW4 To set the board to the Bootloader ISP mode, press and hold the ISP_button , connect the development board via the MCU-Link connector to the PC, then release ISP_button . Bootloader Host Application (blhost) Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. Verify the COM port assigned to the board by opening Device Manager in Windows and searching for Ports (COM & LPT). Identify and note the corresponding COM port number. Open a command prompt and change the directory to the location of the blhost.exe file: (BLHost_root_location)\blhost_2.6.7\bin\win Verify communication by running the following command, making sure to replace COMX with the COM port assigned to your device: blhost.exe -p COMX get-property 1 Update the NBU firmware image. First, erase the NBU memory: blhost.exe -p COMX flash-erase-all 2 Write the new firmware image using the following command. The write-memory command uses 0x48800000 as the start address, which corresponds to the NBU memory base. Provide the full path to the binary file, or alternatively, copy the .bin file into the same directory as blhost.exe to simplify the command: blhost.exe -p COMX write-memory 0x48800000 .bin MCUXpresso Secure Provisioning Tool Create a workspace for the device. To use the keys same as the development board, select the processor relevant to the FRDM/EVK board. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. To verify communication, click the UART tab, refresh the Port field selection and select the assigned COM Port identified. Click Test connection and confirm that the result displays OK. In the toolbar, select the boot type as Plain unsigned or Plain with CRC. In the Build Image view, load the binary file in Source executable image, enter the start address as  0x48800000  (which corresponds to the NBU memory base), and click Build image. Navigate to the Write Image view, select Use built image, and click Write image. A success message appears when the NBU firmware loading is complete. LinkFlash Tool For this method, a LinkServer debug probe must be available on the board. The steps on how to install the CMSIS-DAP/SEGGER J-link firmware are available here. Navigate to the main LinkServer folder in your computer and execute the  LinkFlash.exe  file. Place the board in ISP mode by pressing and holding ISP_button . Connect the USB cable to the MCU-Link connector and release ISP_button after the connection is established. In the LinkFlash tool, after the device is connected, click the Refresh button to update and set the probe target of the board. Go to the Program tab, click Browse, select the NBU firmware file, and enter the start address  0x48800000 . Ensure to check the boxes Mass erase before programming and Reset target after programming. To load the NBU firmware, click Program.
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How to PORT/PINS 1 Table of Contents • Introduction • Pins Configuration • Configure Port Component • Conclusion • References 2 Introduction Before a microcontroller can interact with external hardware, its pins must be configured correctly. Whether you want to read a button state, drive an LED, communicate with a sensor, or use a peripheral, the first step is to configure the corresponding pins. 3 Pins Configuration First, identify the pin you want to use. In this example, we will use the following pin: RGBLED0_RED PTA29 GPIO29 Note: When working in S32 Configuration Tools, the pin MSCR value (third line) is not required. However, it will be needed later if you also configure the same pins in EB tresos. Configure the pins according to their intended use: input, output, or input/output. To begin, open the Pins Tool by clicking the Pins button in the upper-right corner. In the Pins Tool, the pins are organized into Functional Groups. In the default projects provided with the Model-Based Design Toolbox, these groups are arranged based on the peripheral to which the pins are routed. For this step, focus on the Pins tab in the upper-left area of the window. Search for the pin you want to configure; in this example, PTA29. If the desired functionality is already routed to a different pin, first disable that routing by clearing the corresponding selection before assigning it to PTA29. Next, update the identifier and label as needed, then enable the routing by selecting the checkbox on the left. This opens the routing selection dialog. Select SIUL2:gpio,29 , as it matches the intended functionality. A second dialog then prompts you to select the pin direction.   In this example, the LED is configured as Input/Output, matching the configuration used by the example project. Depending on the intended use of the pin, a different direction may be required — for example, a push button is typically configured as an input. Additional examples can be found in the default projects provided with the Model-Based Design Toolbox. 4 Configure Port Component The Port component must reflect the same pin configuration defined in the Pins Tool. After returning to the Peripherals Tool, the Port component may be highlighted in red because the pin configuration was modified in the Pins Tool and has not yet been updated in the Port component.   In the default Model-Based Design Toolbox projects, PortPins are grouped into PortContainers according to their associated peripheral, such as Dio_Pins or Can_Pins . Locate the Dio_Pins PortContainer and update the PortPin entries so that they match the values configured in the Pins Tool. The pin will already contain the MSCR value inherited from the Pins configuration. Update the pin name as desired so it can be easily identified in the model, then repeat the process for each additional pin. The PortPin Id uniquely identifies each PortPin entry. The identifier must remain unique across all PortContainers. Note: If a duplicate PortPin Id value is used, the configuration will report an error. Assign a unique PortPin Id value to each configured pin. For example, a configuration containing 40 pins can use identifiers within the range described by the tool configuration. 5 Conclusion Once the pin configuration is complete and the Port component has been updated accordingly, you can continue with the configuration of the software components that will use those pins. 6 References NXP Model-Based Design Toolbox – Community Interacting with Digital Inputs/Outputs on MR-CANHUBK344
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How to DIO 1 Table of Contents • Introduction • Component Configuration  • Conclusion • References 2 Introduction Before configuring the DIO component, make sure that the pins you intend to use have already been configured in both the Pins Tool and the Port component. If not, refer to the previous articles on pins and port configuration. 3 Component Configuration In order to configure the Dio peripheral, press on the Dio component on the left side of the screen for the Dio Configuration tab to be opened. There, press on the Dio Config tab. Understanding how the DioPort and DioChannel are organized might prove useful later. The number present under the DioPort label represents the corresponding value of the Dio port that you want to access. Below you can find a table with the correspondence between the values and the registers. Register half DioPort value AL 0 AH 1 BL 2 BH 3 CL 4 CH 5 DL 6 DH 7 EL 8 EH 9 Each of those is half of a register and together every line forms a 32-bit register. For example, AL and AH contain all the pin values that are assigned to PTA. AL contains the first 16 pins and AH contains the next 16 pins. For example, the RGBLED0_RED pin is assigned to PTA29. From that we can conclude that, since 29 is higher than 15 (the 16th value of AL, since the first value is 0), the PTA29 pin must be assigned to the AH register. To reiterate, the PTA0–PTA15 pins belong to the AL register while the PTA16–PTA31 (the value must be offset by -16 when computing the Id) pins belong to the AH register, and this is true for the rest of the registers too: PTB, PTC, PTD, PTE. Note: When computing the channel Id for pins in the upper half of a port (e.g. PTA16–PTA31), subtract 16 from the pin number. To create a new channel, select the appropriate DioPort and click the + button next to DioChannel. A new channel entry will be created. Fill in the required channel information according to the pin that was previously configured in the Pins Tool and Port component. Repeat this process for each newly configured pin, ensuring that the channel is added under the correct DioPort. 4 Conclusion After configuring the required DioChannels, save the configuration and regenerate the code. The configured DIO channels can then be used by the application to access the corresponding digital inputs and outputs. 5 References NXP Model-Based Design Toolbox – Community Interacting with Digital Inputs/Outputs on MR-CANHUBK344
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Software and Hardware Setup for the S32N55 Communication Hub 1 Table of Contents • Introduction • Required Software • Required Hardware • Communication and Board-Specific Setup • References • Conclusion   2 Introduction The Main Node is the central application target used throughout this project. It sits between the simulation environment running on the host PC and the physical hardware that represents the various vehicle domains. While the previous article introduced the purpose of the Main Node and its role within the overall system, this article focuses on the environment that makes that functionality possible. Developing and validating the Main Node requires more than a target board. The application is modeled, tested, configured, deployed, and monitored using a collection of software tools that work together with the hardware platform. Understanding this environment is important for anyone interested in reproducing the setup or following the remaining articles in the series. This article describes the software components used during development, the hardware platform used to run the application, and the communication infrastructure that connects the Main Node to the rest of the system. Figure 1. Position of the Main Node within the system architecture. 3 Required Software The Main Node software environment combines MathWorks modeling tools with NXP target support and development utilities. Together, these tools provide the workflow used to model the application, generate code, configure the hardware platform, deploy the software, and observe its behavior during validation and runtime analysis. 3.1 Modeling and Application Development The Main Node application is developed as a Simulink model. MATLAB and Simulink are used to describe the behavior of the application before any software is deployed to hardware. Communication interfaces, application states, signal handling, and system-level functionality are assembled and validated within the modeling environment, allowing development to begin long before the target board is involved. The software environment used for this project includes: MATLAB R2024a or newer Simulink Simulink Coder Embedded Coder MATLAB Coder Stateflow These tools provide the code-generation workflow that transforms the model into embedded software capable of running on the target hardware. 3.2 Network Definition and Validation Communication is one of the primary responsibilities of the Main Node. It exchanges information with the simulation environment, the zonal gateways, and the remaining vehicle-domain nodes through a shared CAN network. Vehicle Network Toolbox is used to bring those communication interfaces directly into MATLAB and Simulink. By using the same DBC definitions during development and validation, communication behavior can be verified before deployment and remain consistent across the complete system. The shared DBC maintained with CANdb++ acts as a common communication contract between all participating nodes. Required tools: Vehicle Network Toolbox CANdb++ 3.1 or newer 3.3 Target Support and Code Generation The bridge between the Simulink model and the target hardware platform is provided by the required NXP Model-Based Design Toolbox package. The toolbox provides: Main target platform support Peripheral integration blocks Build integration Deployment support FreeMASTER integration Using these components, the generated software can be executed directly on the target hardware without requiring manual integration of low-level peripheral code. 3.4 Build and Configuration Environment After code generation, the application is built and deployed using the NXP software toolchain integrated inside Model-Based Design Toolbox package. These tools are used to compile, link, and deploy the generated software to the target board. In parallel, EB tresos is used to maintain the low-level configuration required by the Main Node environment. CAN communication, UART telemetry, I2C initialization, interrupt configuration, and board-level peripheral settings are all managed through this configuration flow. Together, these tools ensure that the generated software and the target configuration remain aligned throughout development. 3.5 Runtime Monitoring and Validation Once deployed, the Main Node can be observed through two complementary mechanisms. FreeMASTER Lite provides runtime visibility into application variables and internal states, while CAN analysis tools are used to inspect the communication exchanged across the network. These tools are used throughout development and validation activities to verify both application behavior and network communication. Figure 2. Development workflow used by the Main Node application. 4 Required Hardware Unlike the peripheral nodes, the Main Node is responsible for connecting the simulation environment with the physical hardware network. As a result, the hardware environment includes both the target board and the supporting infrastructure used during development, validation, and system-level execution. 4.1 S32N55 Board The Main Node application executes on an S32N55 board selected for the central application role. Within this setup, the board serves as the central application platform and hosts the software responsible for coordinating communication between the simulation environment and the zonal gateways. The board provides: CAN FD communication interfaces UART communication interfaces Debug and deployment connectivity I2C peripherals Processing resources required by the Main Node application The Main Node target board is the primary hardware platform referenced throughout this article series. 4.2 Host PC The host PC provides the environment used to interact with the full setup. Depending on the activity being performed, it may host: MATLAB and Simulink RoadRunner simulation environments FreeMASTER Lite CAN analysis software The host PC communicates with the Main Node both through the CAN network and through the dedicated telemetry interface used by FreeMASTER. 4.3 CAN Analyzer A CAN analyzer is used during development and validation to monitor network traffic exchanged between the Main Node and the zonal gateways. Beyond debugging, the analyzer also provides a convenient method of validating DBC definitions, message timing, and network integration behavior before the full setup is assembled. 5 Communication and Board-Specific Setup Several aspects of the Main Node environment are specific to the selected target board and are worth understanding before reproducing the setup. 5.1 Communication Topology The Main Node does not communicate directly with every vehicle-domain node. Instead, it exchanges information with the two zonal gateways, which distribute the relevant signals toward the corresponding vehicle-domain nodes. This arrangement keeps the system organized around a zonal architecture while allowing each subsystem to be developed and validated independently. 5.2 CAN Transceiver Initialization One hardware-specific detail of the target board concerns the external CAN transceiver. Note: Before CAN communication becomes available, the transceiver must first be switched from standby mode into normal operation. This transition is not controlled directly through a dedicated GPIO. Instead, it is performed through an I2C-connected port expander located on the board. As a result, the startup sequence requires an I2C initialization step before the FlexCAN controller can begin communication. Figure 3. CAN transceiver enable sequence on the target board. 5.3 FreeMASTER Telemetry Interface In addition to the CAN network, the Main Node exposes runtime telemetry through a dedicated UART connection used by FreeMASTER Lite. This interface is used throughout validation and runtime analysis to visualize application variables and monitor system behavior in real time. 6 References Model-Based Design Toolbox (MBDT) Community NXP S32N Vehicle Super-Integration Processors MathWorks Vehicle Network Toolbox NXP FreeMASTER Run-Time Debugging Tool 7 Conclusion This article introduced the environment used to develop, deploy, and validate the Main Node application. It described the software workflow, the hardware platform, and the communication infrastructure that connect the Main Node to both the simulation environment and the physical hardware network. Particular attention was given to the Main Node's position within the system topology, the UART-based telemetry interface used by FreeMASTER, and the I2C-controlled CAN transceiver initialization required by the target board. The next article moves beyond the enablement layer and focuses on the Main Node application itself, describing the information it receives, the processing it performs, and the outputs it publishes back into the system network.
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