S32G399A STMの問題 こんにちは、皆さん STM1 タイマーで問題が発生しています。STM0 (CH0) の 1ms で動作する Counter_1 と STM1 (CH0) の 1us で動作する Counter_2 の 2 つのカウンターを構成しました。STM0 カウンタは正常に動作しますが、STM1 が期待どおりに更新されません。1usごとに更新するのではなく、15〜25秒ごとに更新されます。 構成の詳細: STM0 と STM1 の両方のクロック: 133.33333 MHz 両方のプリスケーラー(PSC):1 値の比較:1msの0x208D5(STM0)と1usの0x85(STM1) 割り込み優先度:STM0の場合は4、STM1の場合は5 Re:S32G399A STMの問題 さて、私はそれを行うことができますが、問題は、両方を1ms使用している場合、それらは機能するということです。だから、私は疑問を持っていました。とにかく、やってみて、お知らせします コードから何か見つけた場合はお知らせください

S32K344)更新霍尔周期 关于示例项目“MCSPTE1AK344_BLDC_6Step_hall_ll”， 霍尔传感器每七个上升沿就会发生一次中断，触发函数“eMIOS1IcuNotify()”。 您能否告诉我如何改变它以触发每个边缘的中断？ 在哪里设置每7次？

i.mx95 lvds HI NXP Teams I am evaluating the I.MX95 for multi-camera and multi-display applications. Since two sets of MIPI-CSI are required simultaneously, DSI cannot be used for the display. I would like to know if the two 1x4 LVDS ports can output different display information separately? What is the supported bitrate and resolution? poyuan Graphics & Display Re: i.mx95 lvds Hello, Yes, the i.MX95 2x 4-lane LVDS display interface capable of 1080p60 resolution. Best regards/Saludos, Aldo. Re: i.mx95 lvds I understand the current status of the I.MX95. Can the two BOE WXGA LVDS panels on the EVK output different information? If I create my own adapter, can it output 1080P, 30FPS information? Re: i.mx95 lvds Hello, Please note that i.MX95 is still in pre-production stage so all information and specifications herein are subject to change without notice. I.MX95 is capable of a 2x 4-lane or 1x 8-lane LVDS display interface capable of 1080p60 resolution. On the EVK there is 2 combinations available either two single-channel LVDS-to-HDMI converter or two BOE WXGA LVDS panel. Best regards/Saludos, Aldo.

LS1046A custom board: BL2: Failed to load image I'm trying to bring up custom LS1046A board, but it fails due to memory initialization failure. TFA version: 1.5 NXP LLDP L6.1.55_2.2.0 Board stuck at BL2. Here is the verbose output: ``` INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x600081f INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080130 = 0x2800000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0xffff INFO: *0x1080280 = 0xffffffff INFO: *0x1080284 = 0xffffff7d INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffffff7d INFO: *0x1080290 = 0x1 INFO: *0x10802a0 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d5a0 INFO: *0x1080408 = 0xe50eb14 INFO: *0x108040c = 0xc8000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80040000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x3002 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10103000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x94000000 INFO: *0x1080f50 = 0x10001000 INFO: *0x1080f54 = 0xf000f00 INFO: *0x1080f58 = 0xd000d00 INFO: *0x1080f5c = 0xc000c00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0INFO: RCW BOOT SRC is IFC NOR VERBOSE: Generic delay timer configured with mult=1 and div=25 INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x600081f INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080130 = 0x2800000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0xffff INFO: *0x1080280 = 0xffffffff INFO: *0x1080284 = 0xffffff7d INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffffff7d INFO: *0x1080290 = 0x1 INFO: *0x10802a0 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d5a0 INFO: *0x1080408 = 0xe50eb14 INFO: *0x108040c = 0xc8000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80040000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x3002 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10103000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x94000000 INFO: *0x1080f50 = 0x10001000 INFO: *0x1080f54 = 0xf000f00 INFO: *0x1080f58 = 0xd000d00 INFO: *0x1080f5c = 0xc000c00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0x70006f INFO: *0x1080f94 = 0x80000000 INFO: *0x1080fb0 = 0x3 INFO: *0x1080fb4 = 0x1f1f1f1f INFO: *0x1080fb8 = 0x1f1f1f1f INFO: *0x1080fbc = 0x1f1f1f1f INFO: *0x1080fc0 = 0x1f1f1f1f INFO: *0x1080fc4 = 0x1f1f1f1f INFO: *0x1080fc8 = 0x1f1f1f1f INFO: *0x1080fcc = 0x1f1f1f1f INFO: *0x1080fd0 = 0x1f1f1f1f INFO: *0x1080fd4 = 0x1f1f1f1f INFO: *0x1080fd8 = 0x1f1f1f1f INFO: *0x1080fdc = 0x1f1f1f1f INFO: *0x1080fe0 = 0x1f1f1f1f INFO: *0x1080fe4 = 0x1f1f1f1f INFO: *0x1080fe8 = 0x1f1f1f1f INFO: *0x1080fec = 0x1f1f1f1f INFO: *0x1080ff0 = 0x1f1f1f1f INFO: *0x1080ff4 = 0x1f1f1f1f INFO: *0x1080ff8 = 0x1f1f1f1f INFO: *0x1080ffc = 0x1f003f38 NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off INFO: Time used by DDR driver 1371 ms VERBOSE: Memory seen by this BL image: 0x10000000 - 0x10013000 VERBOSE: Code region: 0x10000000 - 0x10008000 VERBOSE: Read-only data region: 0x10008000 - 0x1000b000 VERBOSE: DRAM Region 0: 0x80000000 - 0xfbdfffff VERBOSE: Secure DRAM Region 0: 0xfbe00000 - 0xffffffff mmap: VA:0x1000000 PA:0x1000000 size:0xf000000 attr:0x8 granularity:0x40000000 VA:0x10000000 PA:0x10000000 size:0x8000 attr:0x2 granularity:0x40000000 VA:0x10008000 PA:0x10008000 size:0x3000 attr:0x22 granularity:0x40000000 VA:0x10000000 PA:0x10000000 size:0x13000 attr:0xa granularity:0x40000000 VA:0x60000000 PA:0x60000000 size:0x8000000 attr:0xa granularity:0x40000000 VA:0x80000000 PA:0x80000000 size:0x7be00000 attr:0x1a granularity:0x40000000 VA:0xfbe00000 PA:0xfbe00000 size:0x4200000 attr:0xa granularity:0x40000000 VERBOSE: Translation tables state: VERBOSE: Xlat regime: EL3 VERBOSE: Max allowed PA: 0xffffffffff VERBOSE: Max allowed VA: 0xffffffffff VERBOSE: Max mapped PA: 0xffffffff VERBOSE: Max mapped VA: 0xffffffff VERBOSE: Initial lookup level: 0 VERBOSE: Entries @initial lookup level: 2 ... NOTICE: BL2: v1.5(debug): NOTICE: BL2: Built : 07:13:31, Jun 6 2024 INFO: Configuring TrustZone Controller VERBOSE: TrustZone : Configuring region 0 (TZC Interface Base=0x1500000 sec_attr=0x0, ns_devs=0x0) INFO: Value of region base = ffe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 1)... VERBOSE: TrustZone : ... base = fbe00000, top = ffdfffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0x0) INFO: Value of region base = 1ffe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 2)... VERBOSE: TrustZone : ... base = ffe00000, top = ffffffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff) INFO: Value of region base = fbe00000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 3)... VERBOSE: TrustZone : ... base = 80000000, top = fbdfffff, VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff) INFO: Value of region base = a80000000 VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 4)... VERBOSE: TrustZone : ... base = 880000000, top = 9ffffffff, VERBOSE: TrustZone : ... sec_attr = 0x0, ns_devs = 0xffffffff) INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 WARNING: Firmware Image Package header check failed. VERBOSE: Trying FUSE IO WARNING: Failed to obtain reference to image id=3 (-2) ERROR: BL2: Failed to load image (-2) Authentication failure ``` On the QCVS tool 'Centering the clock'  test failed. I got the following log. ``` #################### Result for: wrlvl_searcher ###### Run 1 ###################################### Test result: [ ============================================================ Updated: WRLVL_CNTL = 0x86750605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750607, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750609, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060D, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675060F, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750611, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750613, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750615, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750617, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x86750619, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Incrementing WRLVL_START... ============================================================ Updated: WRLVL_CNTL = 0x8675061B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000 Validation cannot proceed due to other DDR hardware or software issues! Common hardware issues include: - DRAM reset is not implemented correctly - Voltages are not present - Signals not connected correctly - Differential signals connected in wrong polarity Common software issues include: - wrong DDR frequency selected - wrong DDR configuration selected - incorrect SPD data - DDR4 DQn_MAP configured values are incorrect < > {{Validation cannot proceed due to other DDR hardware or software issues!}} Err. capture registers: 0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080 0xE44, 0x00000100 0xE48, 0x00000000 0xE4C, 0x00000000 0xE50, 0x00000000 0xE54, 0x00000000 0xE58, 0x00010000 Dump: 0xF00, 0x00000000 0xF04, 0x00003002 0xF08, 0x0000000D 0xF0C, 0x14000C20 0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000 0xF20, 0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010 0xF30, 0x10101010 0xF34, 0x10103000 0xF38, 0x00000000 0xF3C, 0x00000000 0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x94000000 0xF50, 0x30003000 0xF54, 0x2F002F00 0xF58, 0x3D003D00 0xF5C, 0x3C003C00 0xF60, 0x36000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000 0xF70, 0x0070006F 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000 0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000 0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x00000000 0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000 0xFB0, 0x00000003 0xFB4, 0x1F1F1F1F 0xFB8, 0x1F1F1F1F 0xFBC, 0x1F1F1F1F 0xFC0, 0x1F1F1F1F 0xFC4, 0x1F1F1F1F 0xFC8, 0x1F1F1F1F 0xFCC, 0x1F1F1F1F 0xFD0, 0x1F1F1F1F 0xFD4, 0x1F1F1F1F 0xFD8, 0x1F1F1F1F 0xFDC, 0x1F1F1F1F 0xFE0, 0x1F1F1F1F 0xFE4, 0x1F1F1F1F 0xFE8, 0x1F1F1F1F 0xFEC, 0x1F1F1F1F 0xFF0, 0x1F1F1F1F 0xFF4, 0x1F1F1F1F 0xFF8, 0x1F1F1F1F 0xFFC, 0x1F003F38 Data: 0x00000005 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ``` I tried to adjust Clock control and WL but it failed and threw same error after memory validation on QCVS tool. The following are the parameters for DDR. (TFA version is 1.5 as recommended by NXP for the boards with LS1046A) ``` const struct ddr_cfg_regs static_1600 = { .cs[0].bnds = 0x01FF, .cs[1].bnds = 0x0200023F, .cs[0].config = 0x80010512, .cs[1].config = 0x0202, .cs[2].bnds = 0x0240027F, .cs[3].bnds = 0x028002BF, .cs[2].config = 0x0202, .cs[3].config = 0x0202, .cs[0].config_2 = 0x00, .cs[1].config_2 = 0x00, .cs[2].config_2 = 0x00, .cs[3].config_2 = 0x00, .sdram_cfg[0] = 0x45200000, .sdram_cfg[1] = 0x00401070, .timing_cfg[0] = 0x80770010, .timing_cfg[1] = 0xB8BC02D5, .timing_cfg[2] = 0x005951A5, .timing_cfg[3] = 0x02111100, .timing_cfg[4] = 0x00220002, .timing_cfg[5] = 0x06401400, .timing_cfg[7] = 0x25540000, .timing_cfg[8] = 0x05447A00, .dq_map[0] = 0x1692672C, .dq_map[1] = 0x8C99D5A0, .dq_map[2] = 0x0E50EB14, .dq_map[3] = 0xC8000000, .sdram_mode[0] = 0x01010631, .sdram_mode[1] = 0x00100000, .sdram_mode[2] = 0x00, .sdram_mode[3] = 0x00, .sdram_mode[4] = 0x00, .sdram_mode[5] = 0x00, .sdram_mode[6] = 0x00, .sdram_mode[7] = 0x00, .sdram_mode[8] = 0x0701, .sdram_mode[9] = 0x08800000, .sdram_mode[10] = 0x00, .sdram_mode[11] = 0x00, .sdram_mode[12] = 0x00, .sdram_mode[13] = 0x00, .sdram_mode[14] = 0x00, .sdram_mode[15] = 0x00, .md_cntl = 0x00, .interval = 0x1FFE07FF, .data_init = 0xDEADBEEF, .clk_cntl = 0x02800000, .init_addr = 0x00, .ddr_sr_cntr = 0x0, .init_ext_addr = 0x00, .zq_cntl = 0x8A090905, .wrlvl_cntl[0] = 0x86750609, .wrlvl_cntl[1] = 0x09060603, .wrlvl_cntl[2] = 0x030D0D00, .cdr[0] = 0x800C0000, .cdr[1] = 0x81, }; ``` Re: LS1046A custom board: BL2: Failed to load image Have you found what was the cause of "ERROR: Found training error(s): 0x3000 ERROR: Error: Waiting for D_INIT timeout."? I'm facing the same issue. Re: LS1046A custom board: BL2: Failed to load image There is no SPD on my target board. I did as you said. I have configured DDR according to the data sheet but it is failing again. Here is my DDR registers configuration: const struct ddr_cfg_regs static_2100 = { .cs[0].bnds = 0x01FF, .cs[1].bnds = 0x0200023F, .cs[0].config = 0x80010512, .cs[1].config = 0x0202, .cs[0].config_2 = 0x00, .cs[1].config_2 = 0x00, .cs[2].bnds = 0x0240027F, .cs[3].bnds = 0x028002BF, .cs[2].config = 0x0202, .cs[3].config = 0x0202, .cs[2].config_2 = 0x00, .cs[3].config_2 = 0x00, .timing_cfg[0] = 0xFF770010, .timing_cfg[1] = 0xF8FC1265, .timing_cfg[2] = 0x005951A0, .timing_cfg[3] = 0x021D1100, .timing_cfg[4] = 0x0022D502, .timing_cfg[5] = 0x06401400, .timing_cfg[6] = 0x00000000, .timing_cfg[7] = 0x25540000, .timing_cfg[8] = 0x05447A00, .timing_cfg[9] = 0x00000000, .sdram_cfg[0] = 0x45208000, .sdram_cfg[1] = 0x00401060, .sdram_cfg[2] = 0x00, .dq_map[0] = 0x1692672C, .dq_map[1] = 0x8C99D588, .dq_map[2] = 0x0E50C594, .dq_map[3] = 0x48000000, .sdram_mode[0] = 0x01010631, .sdram_mode[1] = 0x00100000, .sdram_mode[2] = 0x00, .sdram_mode[3] = 0x00, .sdram_mode[4] = 0x00, .sdram_mode[5] = 0x00, .sdram_mode[6] = 0x00, .sdram_mode[7] = 0x00, .sdram_mode[8] = 0x0701, .sdram_mode[9] = 0x08800000, .sdram_mode[10] = 0x00, .sdram_mode[11] = 0x00, .sdram_mode[12] = 0x00, .sdram_mode[13] = 0x00, .sdram_mode[14] = 0x00, .sdram_mode[15] = 0x00, .md_cntl = 0x00, .interval = 0x1FFE07FF, .data_init = 0xDEADBEEF, .clk_cntl = 0x02400000, .init_addr = 0x00, .ddr_sr_cntr = 0x0, .init_ext_addr = 0x00, .zq_cntl = 0x8A090705, .wrlvl_cntl[0] = 0x86750605, .wrlvl_cntl[1] = 0x05060607, .wrlvl_cntl[2] = 0x07080804, .sdram_rcw[0] = 0x00, .sdram_rcw[1] = 0x00, .sdram_rcw[2] = 0x00, .sdram_rcw[3] = 0x00, .sdram_rcw[4] = 0x00, .sdram_rcw[5] = 0x00, .cdr[0] = 0x80080000, .cdr[1] = 0x80, .err_disable = 0x00, .err_int_en = 0x00, }; When DRAM data initialization ( D_INIT bit is set to 1)  i get the following output: INFO: RCW BOOT SRC is IFC NOR INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: total size 8 GB INFO: Need to wait up to 2680 ms ERROR: Found training error(s): 0x3000 ERROR: Error: Waiting for D_INIT timeout. ERROR: Writing DDR register(s) failed ERROR: Programing DDRC error ERROR: DDR init failed. NOTICE: Incorrect DRAM0 size is defined in platfor_def.h ERROR: mmap_add_region_check() failed. error -22 ASSERT: lib/xlat_tables_v2/xlat_tables_internal.c:753 When DRAM data initialization ( D_INIT bit is set to 0): INFO: RCW BOOT SRC is IFC NOR INFO: RCW BOOT SRC is IFC NOR INFO: platform clock 700000000 INFO: DDR PLL1 1600000000 INFO: DDR PLL2 0 INFO: Time before programming controller 0 ms INFO: Program controller registers WARNING: Warning: Optimal CPO value not set. INFO: Reading debug[9] as 0x10101010 INFO: Reading debug[10] as 0x10101010 INFO: Reading debug[11] as 0x10101010 INFO: Reading debug[12] as 0x10101010 INFO: cpo_min 0x10 INFO: cpo_max 0x10 INFO: debug[28] 0x70006f WARNING: Warning: A009942 requires setting cpo_sample to 0x37 INFO: *0x1080000 = 0x1ff INFO: *0x1080008 = 0x200023f INFO: *0x1080010 = 0x240027f INFO: *0x1080018 = 0x28002bf INFO: *0x1080080 = 0x80010512 INFO: *0x1080084 = 0x202 INFO: *0x1080088 = 0x202 INFO: *0x108008c = 0x202 INFO: *0x1080100 = 0x21d1100 INFO: *0x1080104 = 0xff770010 INFO: *0x1080108 = 0xf8fc1265 INFO: *0x108010c = 0x5951a0 INFO: *0x1080110 = 0xc5208000 INFO: *0x1080114 = 0x401060 INFO: *0x1080118 = 0x1010631 INFO: *0x108011c = 0x100000 INFO: *0x1080120 = 0x1000 INFO: *0x1080124 = 0x1ffe07ff INFO: *0x1080128 = 0xdeadbeef INFO: *0x1080130 = 0x2400000 INFO: *0x1080160 = 0x22d502 INFO: *0x1080164 = 0x6401400 INFO: *0x108016c = 0x25540000 INFO: *0x1080170 = 0x8a090705 INFO: *0x1080174 = 0xc6750605 INFO: *0x1080190 = 0x5060607 INFO: *0x1080194 = 0x7080804 INFO: *0x1080220 = 0x701 INFO: *0x1080224 = 0x8800000 INFO: *0x1080250 = 0x5447a00 INFO: *0x1080270 = 0x80000000 INFO: *0x1080280 = 0x444844 INFO: *0x1080284 = 0x1488f482 INFO: *0x1080288 = 0xffffffff INFO: *0x108028c = 0xffff73ff INFO: *0x1080290 = 0x1 INFO: *0x1080400 = 0x1692672c INFO: *0x1080404 = 0x8c99d588 INFO: *0x1080408 = 0xe50c594 INFO: *0x108040c = 0x48000000 INFO: *0x1080b20 = 0x8080 INFO: *0x1080b24 = 0x80000000 INFO: *0x1080b28 = 0x80080000 INFO: *0x1080b2c = 0x80 INFO: *0x1080bf8 = 0x20502 INFO: *0x1080bfc = 0x100 INFO: *0x1080e40 = 0x80 INFO: *0x1080f04 = 0x2000 INFO: *0x1080f08 = 0xd INFO: *0x1080f0c = 0x14000c20 INFO: *0x1080f24 = 0x10101010 INFO: *0x1080f28 = 0x10101010 INFO: *0x1080f2c = 0x10101010 INFO: *0x1080f30 = 0x10101010 INFO: *0x1080f34 = 0x10104000 INFO: *0x1080f48 = 0x1 INFO: *0x1080f4c = 0x11000000 INFO: *0x1080f50 = 0xf000f00 INFO: *0x1080f54 = 0xf000e00 INFO: *0x1080f58 = 0xc000c00 INFO: *0x1080f5c = 0xb000b00 INFO: *0x1080f60 = 0x8000000 INFO: *0x1080f64 = 0x9000 INFO: *0x1080f68 = 0x20 INFO: *0x1080f70 = 0x70006f INFO: *0x1080f94 = 0x80000000 NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off INFO: Time used by DDR driver 1029 ms NOTICE: BL2: v1.5(debug): NOTICE: BL2: Built : 07:08:39, Jul 1 2024 INFO: Configuring TrustZone Controller INFO: Value of region base = ffe00000 INFO: Value of region base = 1ffe00000 INFO: Value of region base = fbe00000 INFO: Value of region base = a80000000 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 WARNING: Firmware Image Package header check failed. WARNING: Failed to obtain reference to image id=3 (-2) ERROR: BL2: Failed to load image (-2) Authentication failure Re: LS1046A custom board: BL2: Failed to load image In QCVS DDR tool, if there is SPD on your target board, please create a QCVS DDR project with "reading from SPD" method, then do validation. If no SPD, please fill the "Properties" panel according to your DDR datasheet, then start validation. After all the validation in DDRv tool passing, please generate files used in atf.

当引导加载程序存在时，LPC1768 从 DeepSleep 中唤醒 我有一块带有 LPC1768 的定制板，我需要使用深度睡眠模式。一切按默认方式正常工作，但是当我安装引导加载程序并且我需要使用深度睡眠的主程序有一个偏移时，当我唤醒 MCU 时，它会清除 ctach IRQ 并随着电流增加而唤醒，它仍然卡在某处...可能进入了错误的地址。我不知道如何调试，因为调试器在深度睡眠下不工作。 有什么想法吗？

S32G399A STM问题 大家好， 我遇到了 STM1 计时器的问题。我配置了两个计数器：Counter_1 以 1ms 的频率运行 STM0（CH0），Counter_2 以 1us 的频率运行 STM1（CH0）。STM0 计数器工作正常，但 STM1 未按预期更新。它不是每 1us 更新一次，而是每 15-25s 更新一次。 配置详细信息： STM0 和 STM1 的时钟：133.33333 MHz 预分频器 (PSC)：1 比较值：0x208D5 表示 1ms（STM0），0x85 表示 1us（STM1） 中断优先级：STM0为4，STM1为5 回复：S32G399A STM问题 好的，我可以这样做，但问题是，如果我同时使用它们 1 毫秒，它们就可以工作。所以这就是我产生怀疑的原因。无论如何，我会这么做并让你知道 如果你从代码中发现任何东西，请告诉我

S32DS IPCF config When I use S32DS to test IPCF M7,before I update code where can I config IPCF info?Like set address,etc.Thanks Re: S32DS IPCF config Hi, This information is provided under Config Tools, inside the Peripherals tab: Please, let us know.

S32K312 freertos hardfault 我的工程用了freertos，如果我单独开了can的使用并不会跑到这个地址，但是如果开了pwm或adc就会进入这个地址然后直接hardfault，但是如果不调试只是烧录，功能却是正常的，请问一下这个是为什么呢 回复：S32K312 Freertos硬故障 更改优化级别解决了这个问题，谢谢你的回复     回复：S32K312 Freertos硬故障 我发现即使使用 GCC 进行编译，一开始也会出现错误：在地址“0x0”处中断，没有可用的调试信息，或者在程序代码之外。 但我们很快就会进入main()函数。使用IAR的相同代码将进入bus_fault()函数，并且无法提供准确的故障信息。 使 OPTIMZATION LEVEL = O3，我的 GCC 项目也遇到了与 IAR 项目相同的情况，但是 O0 没有。 你能给我一些指导吗？ 感谢你的回复。           Re: S32K312 freertos hardfault 我尝试将同样的配置和代码挪回S32DS中开发，虽然一开始也会蹦到0x0地址但是马上又会回到main中，可以继续使用。 Re: S32K312 freertos hardfault 关于IMPRECISERR的具体定位还有更多吗，调试过程中也会偶尔出现IACCVIOL，并没有开启看门狗功能，是我的自定义功能，例程参考了ADC+DMA+PIT和can过滤器设置的demo，感谢您的回复。 回复：S32K312 Freertos硬故障 Hello, Google translate: 我的项目使用freertos。如果我单独打开can功能的话，是不会去这个地址的。但是，如果我打开pwm或adc，它将直接进入该地址并进行硬故障。但如果我不调试，只是烧录，功能是正常的。这是为什么呢？ 在我看来这似乎是一些同步问题。你使用看门狗之类的吗？这是示例项目还是你自己定制的？ 要调试硬故障，请按照以下步骤操作： https://community.nxp.com/t5/S32K-Knowledge-Base/如何在ARM-Cortex-M-V7M-MCU-S32K3XX上调试故障异常/ta-p/1595570 您还可以使用： https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 顺祝商祺！ Peter 回复：S32K312 Freertos硬故障 Hello, 不幸的是，我无法根据提供的信息识别问题。 您能否按照硬故障调试指南来查找问题的根源？ https://community.nxp.com/t5/S32K-Knowledge-Base/如何在ARM-Cortex-M-V7M-MCU-S32K3XX上调试故障异常/ta-p/1595570 您也可以在论坛上使用英语吗，因为谷歌的翻译不是很准确。 顺祝商祺！ Peter 回复：S32K312 Freertos硬故障 感谢你的回复。我根据文档分析了这个问题，但是尝试了很久却没有得出结论。使用iar工具链会出现问题，但使用GCC则不会。如果可能的话，您能帮我检查一下我的代码吗？ 另一个问题是，生成的 ICF 文件中没有 HEAP 的定义，但它在 LD 文件中。如果可以的话，请教我如何在IAR环境中修改HEAP   IAR :9.50.2 感谢您的回复。 回复：S32K312 Freertos硬故障 Hello, 另一个问题是，生成的 ICF 文件中没有 HEAP 的定义，但它在 LD 文件中。如果可以的话，请教我如何在IAR环境中修改HEAP 不幸的是，我不能，因为我不了解 IAR 编译器。请参阅其文档。 你能帮我检查一下我的代码吗？ 我可以用 GCC 检查它，但它正如你表达的那样工作。 此外，如果不知道使用了哪个版本的插件，我就无法生成/编译您的程序。 我也没有在您与我共享的项目中找到任何输出文件。没有精灵也没有 s3 记录。 仅地图文件。 顺祝商祺！ Peter

S32K344 resets every three days or RTC system clock returns to initial value every three days (S32K344) I implemented a function where the RTC system clock was set to an initial value (2025-3-11 15:25:0), and then the current system time was obtained every 0.5 seconds and stored on the SD card. I tested continuously for 7 days, but after 7 days, I found that the logs in the SD card would return to the initial value of 2025-3-11 15:25:0 every time it reached [2025-3-13, 4:41:57]. Is it because the system reset or is it just an issue with RTC? Re: S32K344 resets every three days or RTC system clock returns to initial value every three days I have sent you the code via private message. Re: S32K344 resets every three days or RTC system clock returns to initial value every three days My code size exceeds 25MB, is there any other way to send it to you? Re: S32K344 resets every three days or RTC system clock returns to initial value every three days Hi @SCoder41, Just from the log, I am unable to pinpoint if the issue is mainly the RTC or the MCU. Could you share the code (either here, or by a private message). If not, could you share exactly what the code does?  Also, if the reset source is not a SW reset, (i.e. hardware reset), the counter value will be reset. You must configure either SIRC or SXOSC, and perform SW reset to avoid resetting the counter: Solved: Does the S32K312 RTC support system time keeping at reset? - NXP Community Best regards, Julián

iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hello, I have a custom board with a iMX8QM, and need to use a dual link MIPI-DSI for a 1920x1080p@60 LCD screen.  How should the device tree be structured to use two DSI ports for a single LCD panel?  The DS90UB941 Serializer accepts even data on channel 1 and odd data on channel 2.  I've tried structuring my device tree as shown below, but I get DRM errors and the video device is never created.  If I put the panel inside the MIPI node the errors go away, but that seems to only work for single-channel DSI.  How should the device tree be structured to support dual-channel DSI for a LCD? panel1: panel1 { #address-cells = <1>; #size-cells = <0>; status = "okay"; compatible = "raydium,rm67191"; reg = <0>; dsi-lanes = <4>; video-mode = <2>; width-mm = <292>; height-mm = <109>; port@0 { reg = <0>; panel1_input: endpoint { remote-endpoint = <&mipi0_out>; }; }; port@1 { reg = <1>; panel1_input2: endpoint { remote-endpoint = <&mipi1_out>; }; }; }; &mipi0_dphy { status = "okay"; }; &mipi1_dphy { status = "okay"; }; &mipi0_dsi_host { status = "okay"; fsl,clock-drop-level = <2>; ports { port@1 { reg = <1>; mipi0_out: endpoint { remote-endpoint = <&panel1_input>; }; }; }; }; &mipi1_dsi_host { status = "okay"; fsl,clock-drop-level = <2>; ports { port@1 { reg = <1>; mipi1_out: endpoint { remote-endpoint = <&panel1_input2>; }; }; }; }; Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hi @joanxie, I'm connecting to the DS90UB941 via I2C and setting the necessary registers in the device tree.  I was under the impression that I would need to output even data on one DSI channel and odd data on the second DSI channel, but after talking with TI it turns out that I can supply a single channel DSI as you suggested and the serializer will automatically adjust based on the PCLK frequency.  Therefore, I think this topic can be closed.  Thank you! Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer how do you connect DS90UB941? I don't find you set this in the dts file, and one mipi dsi can support 148Mhz, why do you need to use dual mipi dsi? and you couldn't combine dual mipi dsi into one to support display Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hi @joanxie, yes that is true, but the max pixel clock the TI DS90UB941 serializer can support is 105MHz, so it requires using two DSI channels to support up to 210MHz pixel clock.  For 1920x1080p@60 the pixel clock required is 147.5MHz, so that is why I must split it into two DSI channels. How should the device tree be structured to support this? Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer why do you need to set as this? one mipi dsi can support 1080p@60 already， why do you need to connect with 2 mipi dsi interface?

s32k118 CAN Rx割り込み 皆さん、こんにちは s32k118 MCUを使用しており、CANバスとインターフェースする必要があります。CAN_Receive()関数を使用して100ミリ秒ごとにCANバスをポーリングして、バスからメッセージを取得してきましたが、残念ながら、100ミリ秒ごとにバスに複数のメッセージがあるため、多くのメッセージを見逃しています。 最終的な目標は、受信したすべてのメッセージを CAN メッセージのキューに非同期的に追加し、定期的に解析できるようにすることです。私は、MCUがバス上のメッセージを検出するたびにトリガーされるCAN Rx割り込みを使用してこれを達成したいと考えていました。残念ながら、そのようなISRを設定することはできません。 CAN0_ORed_0_31_MB_IRQn IRQで、interrupt_managerコンポーネントを使用してISRを設定しようとしました。しかし、私のISRは、main()関数でCAN_Receive()を呼び出し た後に のみトリガーされているようです。これは、ISR内のすべてのCAN_Receive()関数を排他的に望んでいたため、私の要件を満たしていません。さらに、一度トリガーされた後、コードはISRを何度も繰り返し呼び出すことで行き詰まっているように見えます。 CAN_InstallEventCallback()でコールバック関数をインストールしようとしましたが、ここでも、コールバック関数はCAN_Receive()またはCAN_Send()を呼び出した後に のみ呼び出されます。したがって、繰り返しになりますが、バスからのすべてのメッセージをキャッチするためにコールバックに頼ることはできないようです。 最後に、Rx FIFO 機能を使用し、すべてのメッセージをバッファ タイプの形式でメールボックス 0 に正常に追加します。これが私が必要とするものです...ただし、最大6メッセージに制限されています。 一度に ~16 個のメッセージをバッファリングする必要があると予想しています。 ポーリング、ISR、コールバックで直面した問題を説明するために、「CAN_Example」プロジェクトを添付しました。問題がさらに明確になることを願っています。 このタスク、つまり、将来の解析のために受信 CAN メッセージをバッファリングするというタスクは、どのように実現すればよいですか? 日時:s32k118 CAN Rx割り込み おかげで、これで問題は解決します! 私が見逃していた重要なポイントは、コールバックが正しく機能するために、各メールボックスで少なくとも1回はFLEXCAN_DRV_Receive() 、 FLEXCAN_DRV_RxFifo() 、またはCAN_Receive()を呼び出すことだったようです。 日時:s32k118 CAN Rx割り込み Hi@ArushThomas 以下のリンクのデモでは、MBまたはFIFO割り込みを使用してCANフレームを送受信する方法を示しています。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753

how to change ls1028ardb emmc actual clock ? Hi： Recently, I've installed the ls1028ardb edge 2.0 image onto the official evaluation board. However, through /sys/kernel/debug/mmc1/ios, I found that the actual clock of emmc is lower than expected. For example, even if the HS200 mode is set, the actual clock is only 83M. Could you please advise on how to adjust the actual clock of emmc? clock: 200000000 Hz actual clock: 83333333 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) Re: how to change ls1028ardb emmc actual clock ? Okay, I'll check the driver code Re: how to change ls1028ardb emmc actual clock ? the actual driver has support for HS400 mode. For steps please review the subject "15.6.3.8 HS400" into the LS1028ARM. Re: how to change ls1028ardb emmc actual clock ? Hi： Thank you for your reply. Currently, some customers have mass-produced according to this version of BSP, and they need to solve this problem based on the current version. Is there a similar patch available? Re: how to change ls1028ardb emmc actual clock ? The actual driver has support for the HS400 mode. Please use the LLDP 6.1.55, with this one you don't have to add any patch driver or modify the dts. please note:  root@localhost:~# cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 150000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 10 (mmc HS400) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)  Technical parameters of the eSDHC HS400 mode are provided in the QorIQ LS1028A/LS1018A Data Sheet. Due to A-011334: Limited clock dividers for HS400 mode, maximum SDHC_CLK frequency supported in HS400 (VDD=1.0v) mode is 150 MHz. Re: how to change ls1028ardb emmc actual clock ? Hi： Thank you for your reply. I have already notice this. How should we modify it to hs400? Does the default driver support hs400? Re: how to change ls1028ardb emmc actual clock ? The LS1028ARDB eSDHC2 interface is connected to an 8 GB eMMC device, MTFC8GAKAJCN (from Micron) on the board. The eMMC memory can support x1, x4 and x8 data width and data rate of HS400 mode. for details please review the subject "15.6.3.8 HS400" into the LS1028ARM

s32k118 CAN Rx Interrupt Hi all, I am using the s32k118 MCU and need to interface with a CAN bus. I've been polling the CAN bus every 100ms with the CAN_Receive() function to retrieve any messages from the bus, but unfortunately I do miss a lot of messages, since there are more than one message on the bus every 100ms. My end goal is to asynchronously add all received messages to a Queue of CAN messages, which I can parse periodically. I was hoping to accomplish this with a CAN Rx Interrupt, which would be triggered whenever the MCU detects a message on the bus. Unfortunately, I'm not able to set up such an ISR. I've tried setting up an ISR with the interrupt_manager component, on the CAN0_ORed_0_31_MB_IRQn IRQ. But it seems my ISR is being triggered only after I call CAN_Receive() in my main() function. This does not meet my requirements, as I was hoping to all the CAN_Receive() function exclusively in the ISR. Furthermore, after being triggered once, the code appears to get stuck in continuously calling the ISR over and over. I tried installing a callback function with CAN_InstallEventCallback(), but again, the callback function is only called after I call CAN_Receive() or CAN_Send(). So again, it doesn't seem like I can depend on the Callback to catch all messages from the bus. Finally, I used the Rx FIFO feature, which does successfully add all messages to a the Mailbox 0 in a buffer-type format. This is what I need... except it's limited to a maximum of 6 messages.  I'm anticipating a need for ~16 messages to be buffered at a time. To illustrate the issues I've faced with Polling, ISR and Callback, I've attached a "CAN_Example" project. Hope it serves to further clarify the problem. How do I accomplish this task, of buffering incoming CAN messages for future parsing? Re: s32k118 CAN Rx Interrupt Thanks, that solves the issue! Seems like the key point I'd missed was to call FLEXCAN_DRV_Receive(),  FLEXCAN_DRV_RxFifo() or CAN_Receive() at least once on each Mailbox, for the Callback to work properly. Re: s32k118 CAN Rx Interrupt Hi@ArushThomas You can refer to the demo in the link below which shows how to receive or transmit CAN frames using MB or FIFO interrupts. https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753

S32K358 Check formated HSE key catalog Hi, I'm working on a project use HSE APIs using S32K358. My project requires multiple NVM keyslots. Before using these keys, the key catalog must be formatted with requested key size, key type, key flags. I can check those params using HSE_SRV_ID_GET_KEY_INFO service. But it returns zero for size, type, flags after key catalog formatted. Is there any solution to check the current key catalog information? Thanks a lot. Re: S32K358 Check formated HSE key catalog Hi, Understood. It seems impossible to format only NVM key catalog. Thanks. Re: S32K358 Check formated HSE key catalog Hi @HaiHoangSoftware  I can't see such option. Service HSE_SRV_ID_FORMAT_KEY_CATALOGS obviously requires both pointers to hseKeyGroupCfgEntry_t structures (i.e. to NVM and RAM catalog) in hseFormatKeyCatalogsSrv_t. But I can't see a reason to do that anyway. RAM catalog is empty after each reset, so it's not a big deal to reformat also RAM catalog. Just use the same configuration of RAM catalog when calling HSE_SRV_ID_FORMAT_KEY_CATALOGS. Regards, Lukas Re: S32K358 Check formated HSE key catalog Hi, Is this possible to format only NVM key catalog? Thanks. Re: S32K358 Check formated HSE key catalog Hi, Very clear for now. Thanks a lot. Re: S32K358 Check formated HSE key catalog Yes, that's what I meant. There's no reason to have a service for this because the catalogs are statically configured and user should know the configuration. "there no way to read key catalog information from previous software" - you are talking about development phase now. It's responsibility of user to know how the catalogs were formatted. Or the catalogs can be simply formatted again if needed during development. But in the field, this is not an option - the catalogs can be formatted only in CUST_DEL life cycle. So, if you update the software in field, still the same catalogs must be used. There's no way to update the catalogs in OEM_PROD or IN_FILED life cycle. Regards, Lukas Re: S32K358 Check formated HSE key catalog Hi, Do you mean if the previous software has already formatted the key catalog with different length but not import the key, there no way to read key catalog information from previous software? Re: S32K358 Check formated HSE key catalog Hi @HaiHoangSoftware  There's no such service which would allow you to read the catalog information. Service HSE_SRV_ID_GET_KEY_INFO works only for loaded keys, not for empty keys. But because the catalogs are statically configured, you can simply read constant hseKeyGroupCfgEntry_t structures which you have already defined for catalog formatting. Or you can create own data structure (constant in flash) which will contain details about the catalogs and which you can read in runtime if needed. Regards, Lukas

[config tool 24.12] Is DDR tool available for Ubuntu Hi experts, I'm using the config tool, version 24.12, with Ubuntu 24.04.2 LTS OS. But it keeps to showing the error: unable to locate python. Any suggestions? BR Ben Re: [config tool 24.12] Is DDR tool available for Ubuntu Maybe not related but I have the same issue on macOS. I thought that issue was my installation because of that message. Can this be fixed that tool is not enabled on unsupported platforms? Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi Rita,  Sure, same to you. BR Ben Re: [config tool 24.12] Is DDR tool available for Ubuntu Dear BenSu, @BenSu I am also shocked at it, I am always run this tool in the windows and do not met problem, It works very stably. Yesterday I run it on the linux, I met the same problem with you, so I contact the expert make the tool, he told me that some functions such as DDR tool can not work on the linux. So please use this DDR tool in the windows system. Hope this can do help for you Wish you have a nice day Best Regards Rita Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi Rita, Thanks for the update. I am shocked that it doesn't work on Linux OS. For my understanding, your guy create a tool with eclipse and python, and make it works on WIndows OS. But it can't work on Linux OS. It's fun, right? BR Ben Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi @BenSu , I have tested in my side and confirm with our tool design team that for the DDR configure and test function only and work on windows, can not work on the linux. So, please change to use the ddr tool in the windows. Wish you have a nice day Best Regards Rita Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi Rita, I just simply select the preset. BR Ben Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi @BenSu , What your action cause this error? I just run it on the windows do not use it on the Linux by now. Wish you have a nice day Best Regards Rita Re: [config tool 24.12] Is DDR tool available for Ubuntu Hi Rita, Of course. That's a very simple installation steps: download the bin file, chmod and execute it as the root user. I don't see anything wrong with the installation steps. BR Ben Re: [config tool 24.12] Is DDR tool available for Ubuntu Have you following the steps in our guide document: IMXIUG.pdf

Program not starting after power on Hi, Kind of a stupid question, but I can seem to find why this doesn't work. I am using a S32K144W. When debugging everything works fine and I can develop my application. However, when I disconnect the debugger (JLink) and power cycle my board, nothing happens. Pressing the reset button doesn't work. The application doesn't start. When I attach my debugger and start the gdb server, the application does run when pressing the reset button. Can you provide any pointer to why this is and how to solve this problem? Thanks! Re: Program not starting after power on Hi @Senlent , Thanks for your reply. After some more testing the issue seemed to be the fact that I went to VLPS power mode. No idea why it works when the debugging is connected. Re: Program not starting after power on Hi@peacefulcarrot I have encountered some similar problems, and the reason for the failure was that the clock did not run properly.You can check if there is any problem with the clock configuration

s32k118 CAN Rx中断 大家好， 我正在使用 s32k118 MCU 并且需要与 CAN 总线连接。我一直使用 CAN_Receive() 函数每 100 毫秒轮询一次 CAN 总线，以从总线中检索任何消息，但不幸的是，我确实错过了很多消息，因为每 100 毫秒总线上就会出现多条消息。 我的最终目标是将所有接收到的消息异步添加到 CAN 消息队列中，以便我可以定期解析这些消息。我希望通过 CAN Rx 中断来实现这一点，只要 MCU 检测到总线上的消息，就会触发该中断。不幸的是，我无法设置这样的 ISR。 我尝试在 CAN0_ORed_0_31_MB_IRQn IRQ 上使用 interrupt_manager 组件设置 ISR。但似乎只有在我调用 main() 函数中的 CAN_Receive()后我的 ISR 才会被触发。这不符合我的要求，因为我希望在 ISR 中专门使用 CAN_Receive() 函数。此外，在触发一次之后，代码似乎陷入不断重复调用 ISR 的状态。 我尝试使用 CAN_InstallEventCallback() 安装回调函数，但同样，只有在调用 CAN_Receive() 或 CAN_Send()后才会调用回调函数。所以，再次看来，我似乎不能依靠回调来捕获来自总线的所有消息。 最后，我使用了 Rx FIFO 功能，该功能确实成功地将所有消息以缓冲区格式添加到邮箱 0。这就是我需要的...除了最多 6 条消息。 我预计一次需要缓冲大约 16 条消息。 为了说明我在轮询、ISR 和回调方面遇到的问题，我附加了一个“CAN_Example”项目。希望它有助于进一步澄清问题。 我如何完成这项任务，即缓冲传入的 CAN 消息以供将来解析？ 回复：s32k118 CAN Rx中断 谢谢，问题解决了！ 似乎我错过的关键点是在每个邮箱上至少调用一次FLEXCAN_DRV_Receive()、 FLEXCAN_DRV_RxFifo() 或 CAN_Receive()，以使回调正常工作。 回复：s32k118 CAN Rx中断 你好@ArushThomas 您可以参考下面链接中的演示，其中展示了如何使用 MB 或 FIFO 中断接收或传输 CAN 帧。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753

FRDM-K22F board show no virtual serial port and stuck on bootloader mode Hello, I encountered an issue with my FRDM-K22F development board. After connecting the board to my Windows 10 system, it only shows as "mbed Serial Port (COM3)" in Device Manager. According to the user guide, it should also appear as a virtual serial port, but it does not. This prevents me from updating the CDC driver and running the quick demo using Tera Term. Initially, the RGB LED glows green. I believe this problem can be resolved by updating the firmware (OpenSDA v2.1) using the drag-and-drop method. However, the board is now stuck in bootloader mode, displaying a "BOOTLOADER" drive in File Explorer. Despite attempting the following steps, it remains in bootloader mode: Long press (2 seconds) the reset button. Disconnect and reconnect the USB cable to power cycle the board. The RGB LED no longer glows in bootloader mode. I have attached the quick user guide and a screenshot of File Explorer. I am currently unable to provide a photo of Device Manager in normal mode, as the board is stuck in bootloader mode and only shows as "Portable device -> BOOTLOADER." What I need assistance with: How to exit bootloader mode and return to application (normal) mode. How to enable the virtual serial port in Device Manager and update the CDC driver. Thank you for your help. Freedom Development Platform Re: FRDM-K22F board show no virtual serial port and stuck on bootloader mode Thanks for your help. Now I can change the firmware of the probe. Re: FRDM-K22F board show no virtual serial port and stuck on bootloader mode The K22 is using the same OpenSDA v2.x as on the K64, so you could check out this: https://mcuoneclipse.com/2016/06/26/how-to-recover-the-opensda-v2-x-bootloader/ with downloading the firmware file from ttp://www.nxp.com/opensda  If you have an old board with an old bootloader, you have to update the bootloader first. See https://mcuoneclipse.com/2014/11/01/illustrated-step-by-step-instructions-updating-the-freescale-freedom-board-firmware/ Re: FRDM-KE02Z40M board show no virtual serial port and stuck on bootloader mode Hi, Thank you for your response. Here are my observations: The baud rate should be 115200, not 15200. I did not receive any response in Tera Term when using this setting. The board is already in bootloader mode. I need assistance on how to exit bootloader mode and return the board to normal mode. Thank you for your help. Re: FRDM-KE02Z40M board show no virtual serial port and stuck on bootloader mode Hi, On the device manager of PC, it shows as "mbed Serial Port (COM3)", the COM3 is the virtual COM port of KE02, if you connect a Putty, and set baud rate as 15200, can you see any output? If you want to change the firmware of the probe, pls follow up the process: https://www.nxp.com/design/design-center/software/sensor-toolbox/opensda-serial-and-debug-adapter:OPENSDA#FRDM-KE02Z If you want for OpenSDA enters bootloader mode, It is used to place the OpenSDA circuit into Bootloader mode by holding down the RESET pushbutton while plugging the USB cable to USB connector J6. Once the OpenSDA enters bootloader mode, other OpenSDA applications such as debug application can be programmed. Hope it can help you BR XiangJun Rong

SNVS LP battery fail detection I'm trying to get the recovery from power fail routines for my new application up and running and I am finding the SNVS LP documentation frustrating. Obviously, I need to know if the RTC value is valid before I decide to write a default value, and I look to the Digital Low-Voltage Detector for this purpose. (I.MX RT1160 reference manual, page 2020). Configuring the reference value for LPLVDR is straightforward, but I am not happy about the references to the LP status register. According to the manual we should clear the low voltage event in this register after setting LPLVDR, yet there is no record of where this bit is in the register. Most bits are unidentified and marked as reserved. From what I can see, this situation is the same for other devices using the SNVS module.  Anyway, if we look into the SNVS_LP_Init() routine in the SDK, the implication is that the low voltage event is bit 8, as defined by SNVS_LPSR_LVD_MASK. But despite what the manual states it is set on initialisation, not cleared. And there is no function or macro to check for a valid state at power up, so what is it we are looking for to know if the battery has failed? Should it remain set after initialisation? Do I just ignore it and check LPLVDR directly? I could just see how it seems to work, but I really need to understand how NXP intended it to work so I can make sure my application is reliable. Regards. Sacha. Re: SNVS LP battery fail detection Thanks Edwin, I have requested access to this documentation. To be fair to NXP, there is a note in the reference manual stating that information on security related bit fields is available in the security reference manual. I just don't see why the SNVS reset state bit would be classed as secure. Besides, it would still be nice to have a macro in the SDK to simply check this state. Regards. Sacha. Re: SNVS LP battery fail detection Hi @Sacha, Please look for a better description of the SNVS registers under the Security Reference Manual, which can be downloaded here (the file is the same for both the RT1160 and RT1170): That said, you will see the SRM states that this bit is 1 on reset, not cleared. After initialization, this bit is cleared with the SNVS_LPSR_LVD_MASK: BR, Edwin. Re: SNVS LP battery fail detection Sorry. I meant bit 3, not bit 8. But my comments/ questions still stand.

LINデモとフリーマスターを一緒に実行することは可能ですか? LINデモの例を使用してFreemasterでデモンストレーションしたいのですが、どちらも同じLPUART周辺機器を使用していることを知りました。 何をすべきか?